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1 /*
2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31 */
32 #ifndef MLX5_IFC_H
33 #define MLX5_IFC_H
34 
35 #include "mlx5_ifc_fpga.h"
36 
37 enum {
38 	MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
39 	MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
40 	MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
41 	MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
42 	MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
43 	MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
44 	MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
45 	MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
46 	MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
47 	MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
48 	MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
49 	MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
50 	MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
51 	MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
52 	MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
53 	MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
54 	MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
55 	MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
56 	MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57 	MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58 	MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
59 	MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
60 	MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
61 	MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb,
62 	MLX5_EVENT_TYPE_CODING_FPGA_ERROR                          = 0x20,
63 };
64 
65 enum {
66 	MLX5_MODIFY_TIR_BITMASK_LRO                   = 0x0,
67 	MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE        = 0x1,
68 	MLX5_MODIFY_TIR_BITMASK_HASH                  = 0x2,
69 	MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN   = 0x3
70 };
71 
72 enum {
73 	MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
74 	MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
75 };
76 
77 enum {
78 	MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
79 	MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
80 	MLX5_CMD_OP_INIT_HCA                      = 0x102,
81 	MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
82 	MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
83 	MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
84 	MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
85 	MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
86 	MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
87 	MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
88 	MLX5_CMD_OP_SET_ISSI                      = 0x10b,
89 	MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
90 	MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
91 	MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
92 	MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
93 	MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
94 	MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
95 	MLX5_CMD_OP_CREATE_EQ                     = 0x301,
96 	MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
97 	MLX5_CMD_OP_QUERY_EQ                      = 0x303,
98 	MLX5_CMD_OP_GEN_EQE                       = 0x304,
99 	MLX5_CMD_OP_CREATE_CQ                     = 0x400,
100 	MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
101 	MLX5_CMD_OP_QUERY_CQ                      = 0x402,
102 	MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
103 	MLX5_CMD_OP_CREATE_QP                     = 0x500,
104 	MLX5_CMD_OP_DESTROY_QP                    = 0x501,
105 	MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
106 	MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
107 	MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
108 	MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
109 	MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
110 	MLX5_CMD_OP_2ERR_QP                       = 0x507,
111 	MLX5_CMD_OP_2RST_QP                       = 0x50a,
112 	MLX5_CMD_OP_QUERY_QP                      = 0x50b,
113 	MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
114 	MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
115 	MLX5_CMD_OP_CREATE_PSV                    = 0x600,
116 	MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
117 	MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
118 	MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
119 	MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
120 	MLX5_CMD_OP_ARM_RQ                        = 0x703,
121 	MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
122 	MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
123 	MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
124 	MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
125 	MLX5_CMD_OP_CREATE_DCT                    = 0x710,
126 	MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
127 	MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
128 	MLX5_CMD_OP_QUERY_DCT                     = 0x713,
129 	MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
130 	MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
131 	MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
132 	MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
133 	MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
134 	MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
135 	MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
136 	MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
137 	MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
138 	MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
139 	MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
140 	MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
141 	MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
142 	MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
143 	MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
144 	MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
145 	MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
146 	MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
147 	MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
148 	MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
149 	MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
150 	MLX5_CMD_OP_SET_PP_RATE_LIMIT             = 0x780,
151 	MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
152 	MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
153 	MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
154 	MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
155 	MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
156 	MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
157 	MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
158 	MLX5_CMD_OP_ALLOC_PD                      = 0x800,
159 	MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
160 	MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
161 	MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
162 	MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
163 	MLX5_CMD_OP_ACCESS_REG                    = 0x805,
164 	MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
165 	MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
166 	MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
167 	MLX5_CMD_OP_MAD_IFC                       = 0x50d,
168 	MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
169 	MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
170 	MLX5_CMD_OP_NOP                           = 0x80d,
171 	MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
172 	MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
173 	MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
174 	MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
175 	MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
176 	MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
177 	MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
178 	MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
179 	MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
180 	MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
181 	MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
182 	MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
183 	MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
184 	MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
185 	MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
186 	MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
187 	MLX5_CMD_OP_CREATE_LAG                    = 0x840,
188 	MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
189 	MLX5_CMD_OP_QUERY_LAG                     = 0x842,
190 	MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
191 	MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
192 	MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
193 	MLX5_CMD_OP_CREATE_TIR                    = 0x900,
194 	MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
195 	MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
196 	MLX5_CMD_OP_QUERY_TIR                     = 0x903,
197 	MLX5_CMD_OP_CREATE_SQ                     = 0x904,
198 	MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
199 	MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
200 	MLX5_CMD_OP_QUERY_SQ                      = 0x907,
201 	MLX5_CMD_OP_CREATE_RQ                     = 0x908,
202 	MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
203 	MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
204 	MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
205 	MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
206 	MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
207 	MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
208 	MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
209 	MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
210 	MLX5_CMD_OP_CREATE_TIS                    = 0x912,
211 	MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
212 	MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
213 	MLX5_CMD_OP_QUERY_TIS                     = 0x915,
214 	MLX5_CMD_OP_CREATE_RQT                    = 0x916,
215 	MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
216 	MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
217 	MLX5_CMD_OP_QUERY_RQT                     = 0x919,
218 	MLX5_CMD_OP_SET_FLOW_TABLE_ROOT		  = 0x92f,
219 	MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
220 	MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
221 	MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
222 	MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
223 	MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
224 	MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
225 	MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
226 	MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
227 	MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
228 	MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
229 	MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
230 	MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
231 	MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
232 	MLX5_CMD_OP_ALLOC_ENCAP_HEADER            = 0x93d,
233 	MLX5_CMD_OP_DEALLOC_ENCAP_HEADER          = 0x93e,
234 	MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT   = 0x940,
235 	MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
236 	MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
237 	MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
238 	MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
239 	MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
240 	MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
241 	MLX5_CMD_OP_MAX
242 };
243 
244 struct mlx5_ifc_flow_table_fields_supported_bits {
245 	u8         outer_dmac[0x1];
246 	u8         outer_smac[0x1];
247 	u8         outer_ether_type[0x1];
248 	u8         outer_ip_version[0x1];
249 	u8         outer_first_prio[0x1];
250 	u8         outer_first_cfi[0x1];
251 	u8         outer_first_vid[0x1];
252 	u8         outer_ipv4_ttl[0x1];
253 	u8         outer_second_prio[0x1];
254 	u8         outer_second_cfi[0x1];
255 	u8         outer_second_vid[0x1];
256 	u8         reserved_at_b[0x1];
257 	u8         outer_sip[0x1];
258 	u8         outer_dip[0x1];
259 	u8         outer_frag[0x1];
260 	u8         outer_ip_protocol[0x1];
261 	u8         outer_ip_ecn[0x1];
262 	u8         outer_ip_dscp[0x1];
263 	u8         outer_udp_sport[0x1];
264 	u8         outer_udp_dport[0x1];
265 	u8         outer_tcp_sport[0x1];
266 	u8         outer_tcp_dport[0x1];
267 	u8         outer_tcp_flags[0x1];
268 	u8         outer_gre_protocol[0x1];
269 	u8         outer_gre_key[0x1];
270 	u8         outer_vxlan_vni[0x1];
271 	u8         reserved_at_1a[0x5];
272 	u8         source_eswitch_port[0x1];
273 
274 	u8         inner_dmac[0x1];
275 	u8         inner_smac[0x1];
276 	u8         inner_ether_type[0x1];
277 	u8         inner_ip_version[0x1];
278 	u8         inner_first_prio[0x1];
279 	u8         inner_first_cfi[0x1];
280 	u8         inner_first_vid[0x1];
281 	u8         reserved_at_27[0x1];
282 	u8         inner_second_prio[0x1];
283 	u8         inner_second_cfi[0x1];
284 	u8         inner_second_vid[0x1];
285 	u8         reserved_at_2b[0x1];
286 	u8         inner_sip[0x1];
287 	u8         inner_dip[0x1];
288 	u8         inner_frag[0x1];
289 	u8         inner_ip_protocol[0x1];
290 	u8         inner_ip_ecn[0x1];
291 	u8         inner_ip_dscp[0x1];
292 	u8         inner_udp_sport[0x1];
293 	u8         inner_udp_dport[0x1];
294 	u8         inner_tcp_sport[0x1];
295 	u8         inner_tcp_dport[0x1];
296 	u8         inner_tcp_flags[0x1];
297 	u8         reserved_at_37[0x9];
298 	u8         reserved_at_40[0x1a];
299 	u8         bth_dst_qp[0x1];
300 
301 	u8         reserved_at_5b[0x25];
302 };
303 
304 struct mlx5_ifc_flow_table_prop_layout_bits {
305 	u8         ft_support[0x1];
306 	u8         reserved_at_1[0x1];
307 	u8         flow_counter[0x1];
308 	u8	   flow_modify_en[0x1];
309 	u8         modify_root[0x1];
310 	u8         identified_miss_table_mode[0x1];
311 	u8         flow_table_modify[0x1];
312 	u8         encap[0x1];
313 	u8         decap[0x1];
314 	u8         reserved_at_9[0x17];
315 
316 	u8         reserved_at_20[0x2];
317 	u8         log_max_ft_size[0x6];
318 	u8         log_max_modify_header_context[0x8];
319 	u8         max_modify_header_actions[0x8];
320 	u8         max_ft_level[0x8];
321 
322 	u8         reserved_at_40[0x20];
323 
324 	u8         reserved_at_60[0x18];
325 	u8         log_max_ft_num[0x8];
326 
327 	u8         reserved_at_80[0x18];
328 	u8         log_max_destination[0x8];
329 
330 	u8         log_max_flow_counter[0x8];
331 	u8         reserved_at_a8[0x10];
332 	u8         log_max_flow[0x8];
333 
334 	u8         reserved_at_c0[0x40];
335 
336 	struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
337 
338 	struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
339 };
340 
341 struct mlx5_ifc_odp_per_transport_service_cap_bits {
342 	u8         send[0x1];
343 	u8         receive[0x1];
344 	u8         write[0x1];
345 	u8         read[0x1];
346 	u8         atomic[0x1];
347 	u8         srq_receive[0x1];
348 	u8         reserved_at_6[0x1a];
349 };
350 
351 struct mlx5_ifc_ipv4_layout_bits {
352 	u8         reserved_at_0[0x60];
353 
354 	u8         ipv4[0x20];
355 };
356 
357 struct mlx5_ifc_ipv6_layout_bits {
358 	u8         ipv6[16][0x8];
359 };
360 
361 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
362 	struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
363 	struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
364 	u8         reserved_at_0[0x80];
365 };
366 
367 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
368 	u8         smac_47_16[0x20];
369 
370 	u8         smac_15_0[0x10];
371 	u8         ethertype[0x10];
372 
373 	u8         dmac_47_16[0x20];
374 
375 	u8         dmac_15_0[0x10];
376 	u8         first_prio[0x3];
377 	u8         first_cfi[0x1];
378 	u8         first_vid[0xc];
379 
380 	u8         ip_protocol[0x8];
381 	u8         ip_dscp[0x6];
382 	u8         ip_ecn[0x2];
383 	u8         cvlan_tag[0x1];
384 	u8         svlan_tag[0x1];
385 	u8         frag[0x1];
386 	u8         ip_version[0x4];
387 	u8         tcp_flags[0x9];
388 
389 	u8         tcp_sport[0x10];
390 	u8         tcp_dport[0x10];
391 
392 	u8         reserved_at_c0[0x18];
393 	u8         ttl_hoplimit[0x8];
394 
395 	u8         udp_sport[0x10];
396 	u8         udp_dport[0x10];
397 
398 	union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
399 
400 	union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
401 };
402 
403 struct mlx5_ifc_fte_match_set_misc_bits {
404 	u8         reserved_at_0[0x8];
405 	u8         source_sqn[0x18];
406 
407 	u8         reserved_at_20[0x10];
408 	u8         source_port[0x10];
409 
410 	u8         outer_second_prio[0x3];
411 	u8         outer_second_cfi[0x1];
412 	u8         outer_second_vid[0xc];
413 	u8         inner_second_prio[0x3];
414 	u8         inner_second_cfi[0x1];
415 	u8         inner_second_vid[0xc];
416 
417 	u8         outer_second_cvlan_tag[0x1];
418 	u8         inner_second_cvlan_tag[0x1];
419 	u8         outer_second_svlan_tag[0x1];
420 	u8         inner_second_svlan_tag[0x1];
421 	u8         reserved_at_64[0xc];
422 	u8         gre_protocol[0x10];
423 
424 	u8         gre_key_h[0x18];
425 	u8         gre_key_l[0x8];
426 
427 	u8         vxlan_vni[0x18];
428 	u8         reserved_at_b8[0x8];
429 
430 	u8         reserved_at_c0[0x20];
431 
432 	u8         reserved_at_e0[0xc];
433 	u8         outer_ipv6_flow_label[0x14];
434 
435 	u8         reserved_at_100[0xc];
436 	u8         inner_ipv6_flow_label[0x14];
437 
438 	u8         reserved_at_120[0x28];
439 	u8         bth_dst_qp[0x18];
440 	u8         reserved_at_160[0xa0];
441 };
442 
443 struct mlx5_ifc_cmd_pas_bits {
444 	u8         pa_h[0x20];
445 
446 	u8         pa_l[0x14];
447 	u8         reserved_at_34[0xc];
448 };
449 
450 struct mlx5_ifc_uint64_bits {
451 	u8         hi[0x20];
452 
453 	u8         lo[0x20];
454 };
455 
456 enum {
457 	MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
458 	MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
459 	MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
460 	MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
461 	MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
462 	MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
463 	MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
464 	MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
465 	MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
466 	MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
467 };
468 
469 struct mlx5_ifc_ads_bits {
470 	u8         fl[0x1];
471 	u8         free_ar[0x1];
472 	u8         reserved_at_2[0xe];
473 	u8         pkey_index[0x10];
474 
475 	u8         reserved_at_20[0x8];
476 	u8         grh[0x1];
477 	u8         mlid[0x7];
478 	u8         rlid[0x10];
479 
480 	u8         ack_timeout[0x5];
481 	u8         reserved_at_45[0x3];
482 	u8         src_addr_index[0x8];
483 	u8         reserved_at_50[0x4];
484 	u8         stat_rate[0x4];
485 	u8         hop_limit[0x8];
486 
487 	u8         reserved_at_60[0x4];
488 	u8         tclass[0x8];
489 	u8         flow_label[0x14];
490 
491 	u8         rgid_rip[16][0x8];
492 
493 	u8         reserved_at_100[0x4];
494 	u8         f_dscp[0x1];
495 	u8         f_ecn[0x1];
496 	u8         reserved_at_106[0x1];
497 	u8         f_eth_prio[0x1];
498 	u8         ecn[0x2];
499 	u8         dscp[0x6];
500 	u8         udp_sport[0x10];
501 
502 	u8         dei_cfi[0x1];
503 	u8         eth_prio[0x3];
504 	u8         sl[0x4];
505 	u8         port[0x8];
506 	u8         rmac_47_32[0x10];
507 
508 	u8         rmac_31_0[0x20];
509 };
510 
511 struct mlx5_ifc_flow_table_nic_cap_bits {
512 	u8         nic_rx_multi_path_tirs[0x1];
513 	u8         nic_rx_multi_path_tirs_fts[0x1];
514 	u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
515 	u8         reserved_at_3[0x1fd];
516 
517 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
518 
519 	u8         reserved_at_400[0x200];
520 
521 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
522 
523 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
524 
525 	u8         reserved_at_a00[0x200];
526 
527 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
528 
529 	u8         reserved_at_e00[0x7200];
530 };
531 
532 struct mlx5_ifc_flow_table_eswitch_cap_bits {
533 	u8     reserved_at_0[0x200];
534 
535 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
536 
537 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
538 
539 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
540 
541 	u8      reserved_at_800[0x7800];
542 };
543 
544 struct mlx5_ifc_e_switch_cap_bits {
545 	u8         vport_svlan_strip[0x1];
546 	u8         vport_cvlan_strip[0x1];
547 	u8         vport_svlan_insert[0x1];
548 	u8         vport_cvlan_insert_if_not_exist[0x1];
549 	u8         vport_cvlan_insert_overwrite[0x1];
550 	u8         reserved_at_5[0x19];
551 	u8         nic_vport_node_guid_modify[0x1];
552 	u8         nic_vport_port_guid_modify[0x1];
553 
554 	u8         vxlan_encap_decap[0x1];
555 	u8         nvgre_encap_decap[0x1];
556 	u8         reserved_at_22[0x9];
557 	u8         log_max_encap_headers[0x5];
558 	u8         reserved_2b[0x6];
559 	u8         max_encap_header_size[0xa];
560 
561 	u8         reserved_40[0x7c0];
562 
563 };
564 
565 struct mlx5_ifc_qos_cap_bits {
566 	u8         packet_pacing[0x1];
567 	u8         esw_scheduling[0x1];
568 	u8         esw_bw_share[0x1];
569 	u8         esw_rate_limit[0x1];
570 	u8         reserved_at_4[0x1c];
571 
572 	u8         reserved_at_20[0x20];
573 
574 	u8         packet_pacing_max_rate[0x20];
575 
576 	u8         packet_pacing_min_rate[0x20];
577 
578 	u8         reserved_at_80[0x10];
579 	u8         packet_pacing_rate_table_size[0x10];
580 
581 	u8         esw_element_type[0x10];
582 	u8         esw_tsar_type[0x10];
583 
584 	u8         reserved_at_c0[0x10];
585 	u8         max_qos_para_vport[0x10];
586 
587 	u8         max_tsar_bw_share[0x20];
588 
589 	u8         reserved_at_100[0x700];
590 };
591 
592 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
593 	u8         csum_cap[0x1];
594 	u8         vlan_cap[0x1];
595 	u8         lro_cap[0x1];
596 	u8         lro_psh_flag[0x1];
597 	u8         lro_time_stamp[0x1];
598 	u8         reserved_at_5[0x2];
599 	u8         wqe_vlan_insert[0x1];
600 	u8         self_lb_en_modifiable[0x1];
601 	u8         reserved_at_9[0x2];
602 	u8         max_lso_cap[0x5];
603 	u8         multi_pkt_send_wqe[0x2];
604 	u8	   wqe_inline_mode[0x2];
605 	u8         rss_ind_tbl_cap[0x4];
606 	u8         reg_umr_sq[0x1];
607 	u8         scatter_fcs[0x1];
608 	u8         enhanced_multi_pkt_send_wqe[0x1];
609 	u8         tunnel_lso_const_out_ip_id[0x1];
610 	u8         reserved_at_1c[0x2];
611 	u8         tunnel_stateless_gre[0x1];
612 	u8         tunnel_stateless_vxlan[0x1];
613 
614 	u8         swp[0x1];
615 	u8         swp_csum[0x1];
616 	u8         swp_lso[0x1];
617 	u8         reserved_at_23[0x1d];
618 
619 	u8         reserved_at_40[0x10];
620 	u8         lro_min_mss_size[0x10];
621 
622 	u8         reserved_at_60[0x120];
623 
624 	u8         lro_timer_supported_periods[4][0x20];
625 
626 	u8         reserved_at_200[0x600];
627 };
628 
629 struct mlx5_ifc_roce_cap_bits {
630 	u8         roce_apm[0x1];
631 	u8         reserved_at_1[0x1f];
632 
633 	u8         reserved_at_20[0x60];
634 
635 	u8         reserved_at_80[0xc];
636 	u8         l3_type[0x4];
637 	u8         reserved_at_90[0x8];
638 	u8         roce_version[0x8];
639 
640 	u8         reserved_at_a0[0x10];
641 	u8         r_roce_dest_udp_port[0x10];
642 
643 	u8         r_roce_max_src_udp_port[0x10];
644 	u8         r_roce_min_src_udp_port[0x10];
645 
646 	u8         reserved_at_e0[0x10];
647 	u8         roce_address_table_size[0x10];
648 
649 	u8         reserved_at_100[0x700];
650 };
651 
652 enum {
653 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
654 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
655 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
656 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
657 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
658 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
659 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
660 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
661 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
662 };
663 
664 enum {
665 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
666 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
667 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
668 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
669 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
670 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
671 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
672 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
673 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
674 };
675 
676 struct mlx5_ifc_atomic_caps_bits {
677 	u8         reserved_at_0[0x40];
678 
679 	u8         atomic_req_8B_endianness_mode[0x2];
680 	u8         reserved_at_42[0x4];
681 	u8         supported_atomic_req_8B_endianness_mode_1[0x1];
682 
683 	u8         reserved_at_47[0x19];
684 
685 	u8         reserved_at_60[0x20];
686 
687 	u8         reserved_at_80[0x10];
688 	u8         atomic_operations[0x10];
689 
690 	u8         reserved_at_a0[0x10];
691 	u8         atomic_size_qp[0x10];
692 
693 	u8         reserved_at_c0[0x10];
694 	u8         atomic_size_dc[0x10];
695 
696 	u8         reserved_at_e0[0x720];
697 };
698 
699 struct mlx5_ifc_odp_cap_bits {
700 	u8         reserved_at_0[0x40];
701 
702 	u8         sig[0x1];
703 	u8         reserved_at_41[0x1f];
704 
705 	u8         reserved_at_60[0x20];
706 
707 	struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
708 
709 	struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
710 
711 	struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
712 
713 	u8         reserved_at_e0[0x720];
714 };
715 
716 struct mlx5_ifc_calc_op {
717 	u8        reserved_at_0[0x10];
718 	u8        reserved_at_10[0x9];
719 	u8        op_swap_endianness[0x1];
720 	u8        op_min[0x1];
721 	u8        op_xor[0x1];
722 	u8        op_or[0x1];
723 	u8        op_and[0x1];
724 	u8        op_max[0x1];
725 	u8        op_add[0x1];
726 };
727 
728 struct mlx5_ifc_vector_calc_cap_bits {
729 	u8         calc_matrix[0x1];
730 	u8         reserved_at_1[0x1f];
731 	u8         reserved_at_20[0x8];
732 	u8         max_vec_count[0x8];
733 	u8         reserved_at_30[0xd];
734 	u8         max_chunk_size[0x3];
735 	struct mlx5_ifc_calc_op calc0;
736 	struct mlx5_ifc_calc_op calc1;
737 	struct mlx5_ifc_calc_op calc2;
738 	struct mlx5_ifc_calc_op calc3;
739 
740 	u8         reserved_at_e0[0x720];
741 };
742 
743 enum {
744 	MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
745 	MLX5_WQ_TYPE_CYCLIC       = 0x1,
746 	MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
747 };
748 
749 enum {
750 	MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
751 	MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
752 };
753 
754 enum {
755 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
756 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
757 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
758 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
759 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
760 };
761 
762 enum {
763 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
764 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
765 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
766 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
767 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
768 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
769 };
770 
771 enum {
772 	MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
773 	MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
774 };
775 
776 enum {
777 	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
778 	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
779 	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
780 };
781 
782 enum {
783 	MLX5_CAP_PORT_TYPE_IB  = 0x0,
784 	MLX5_CAP_PORT_TYPE_ETH = 0x1,
785 };
786 
787 enum {
788 	MLX5_CAP_UMR_FENCE_STRONG	= 0x0,
789 	MLX5_CAP_UMR_FENCE_SMALL	= 0x1,
790 	MLX5_CAP_UMR_FENCE_NONE		= 0x2,
791 };
792 
793 struct mlx5_ifc_cmd_hca_cap_bits {
794 	u8         reserved_at_0[0x80];
795 
796 	u8         log_max_srq_sz[0x8];
797 	u8         log_max_qp_sz[0x8];
798 	u8         reserved_at_90[0xb];
799 	u8         log_max_qp[0x5];
800 
801 	u8         reserved_at_a0[0xb];
802 	u8         log_max_srq[0x5];
803 	u8         reserved_at_b0[0x10];
804 
805 	u8         reserved_at_c0[0x8];
806 	u8         log_max_cq_sz[0x8];
807 	u8         reserved_at_d0[0xb];
808 	u8         log_max_cq[0x5];
809 
810 	u8         log_max_eq_sz[0x8];
811 	u8         reserved_at_e8[0x2];
812 	u8         log_max_mkey[0x6];
813 	u8         reserved_at_f0[0xc];
814 	u8         log_max_eq[0x4];
815 
816 	u8         max_indirection[0x8];
817 	u8         fixed_buffer_size[0x1];
818 	u8         log_max_mrw_sz[0x7];
819 	u8         force_teardown[0x1];
820 	u8         reserved_at_111[0x1];
821 	u8         log_max_bsf_list_size[0x6];
822 	u8         umr_extended_translation_offset[0x1];
823 	u8         null_mkey[0x1];
824 	u8         log_max_klm_list_size[0x6];
825 
826 	u8         reserved_at_120[0xa];
827 	u8         log_max_ra_req_dc[0x6];
828 	u8         reserved_at_130[0xa];
829 	u8         log_max_ra_res_dc[0x6];
830 
831 	u8         reserved_at_140[0xa];
832 	u8         log_max_ra_req_qp[0x6];
833 	u8         reserved_at_150[0xa];
834 	u8         log_max_ra_res_qp[0x6];
835 
836 	u8         end_pad[0x1];
837 	u8         cc_query_allowed[0x1];
838 	u8         cc_modify_allowed[0x1];
839 	u8         start_pad[0x1];
840 	u8         cache_line_128byte[0x1];
841 	u8         reserved_at_165[0xb];
842 	u8         gid_table_size[0x10];
843 
844 	u8         out_of_seq_cnt[0x1];
845 	u8         vport_counters[0x1];
846 	u8         retransmission_q_counters[0x1];
847 	u8         reserved_at_183[0x1];
848 	u8         modify_rq_counter_set_id[0x1];
849 	u8         rq_delay_drop[0x1];
850 	u8         max_qp_cnt[0xa];
851 	u8         pkey_table_size[0x10];
852 
853 	u8         vport_group_manager[0x1];
854 	u8         vhca_group_manager[0x1];
855 	u8         ib_virt[0x1];
856 	u8         eth_virt[0x1];
857 	u8         reserved_at_1a4[0x1];
858 	u8         ets[0x1];
859 	u8         nic_flow_table[0x1];
860 	u8         eswitch_manager[0x1];
861 	u8	   early_vf_enable[0x1];
862 	u8         mcam_reg[0x1];
863 	u8         pcam_reg[0x1];
864 	u8         local_ca_ack_delay[0x5];
865 	u8         port_module_event[0x1];
866 	u8         enhanced_error_q_counters[0x1];
867 	u8         ports_check[0x1];
868 	u8         reserved_at_1b3[0x1];
869 	u8         disable_link_up[0x1];
870 	u8         beacon_led[0x1];
871 	u8         port_type[0x2];
872 	u8         num_ports[0x8];
873 
874 	u8         reserved_at_1c0[0x1];
875 	u8         pps[0x1];
876 	u8         pps_modify[0x1];
877 	u8         log_max_msg[0x5];
878 	u8         reserved_at_1c8[0x4];
879 	u8         max_tc[0x4];
880 	u8         reserved_at_1d0[0x1];
881 	u8         dcbx[0x1];
882 	u8         general_notification_event[0x1];
883 	u8         reserved_at_1d3[0x2];
884 	u8         fpga[0x1];
885 	u8         rol_s[0x1];
886 	u8         rol_g[0x1];
887 	u8         reserved_at_1d8[0x1];
888 	u8         wol_s[0x1];
889 	u8         wol_g[0x1];
890 	u8         wol_a[0x1];
891 	u8         wol_b[0x1];
892 	u8         wol_m[0x1];
893 	u8         wol_u[0x1];
894 	u8         wol_p[0x1];
895 
896 	u8         stat_rate_support[0x10];
897 	u8         reserved_at_1f0[0xc];
898 	u8         cqe_version[0x4];
899 
900 	u8         compact_address_vector[0x1];
901 	u8         striding_rq[0x1];
902 	u8         reserved_at_202[0x1];
903 	u8         ipoib_enhanced_offloads[0x1];
904 	u8         ipoib_basic_offloads[0x1];
905 	u8         reserved_at_205[0x5];
906 	u8         umr_fence[0x2];
907 	u8         reserved_at_20c[0x3];
908 	u8         drain_sigerr[0x1];
909 	u8         cmdif_checksum[0x2];
910 	u8         sigerr_cqe[0x1];
911 	u8         reserved_at_213[0x1];
912 	u8         wq_signature[0x1];
913 	u8         sctr_data_cqe[0x1];
914 	u8         reserved_at_216[0x1];
915 	u8         sho[0x1];
916 	u8         tph[0x1];
917 	u8         rf[0x1];
918 	u8         dct[0x1];
919 	u8         qos[0x1];
920 	u8         eth_net_offloads[0x1];
921 	u8         roce[0x1];
922 	u8         atomic[0x1];
923 	u8         reserved_at_21f[0x1];
924 
925 	u8         cq_oi[0x1];
926 	u8         cq_resize[0x1];
927 	u8         cq_moderation[0x1];
928 	u8         reserved_at_223[0x3];
929 	u8         cq_eq_remap[0x1];
930 	u8         pg[0x1];
931 	u8         block_lb_mc[0x1];
932 	u8         reserved_at_229[0x1];
933 	u8         scqe_break_moderation[0x1];
934 	u8         cq_period_start_from_cqe[0x1];
935 	u8         cd[0x1];
936 	u8         reserved_at_22d[0x1];
937 	u8         apm[0x1];
938 	u8         vector_calc[0x1];
939 	u8         umr_ptr_rlky[0x1];
940 	u8	   imaicl[0x1];
941 	u8         reserved_at_232[0x4];
942 	u8         qkv[0x1];
943 	u8         pkv[0x1];
944 	u8         set_deth_sqpn[0x1];
945 	u8         reserved_at_239[0x3];
946 	u8         xrc[0x1];
947 	u8         ud[0x1];
948 	u8         uc[0x1];
949 	u8         rc[0x1];
950 
951 	u8         uar_4k[0x1];
952 	u8         reserved_at_241[0x9];
953 	u8         uar_sz[0x6];
954 	u8         reserved_at_250[0x8];
955 	u8         log_pg_sz[0x8];
956 
957 	u8         bf[0x1];
958 	u8         driver_version[0x1];
959 	u8         pad_tx_eth_packet[0x1];
960 	u8         reserved_at_263[0x8];
961 	u8         log_bf_reg_size[0x5];
962 
963 	u8         reserved_at_270[0xb];
964 	u8         lag_master[0x1];
965 	u8         num_lag_ports[0x4];
966 
967 	u8         reserved_at_280[0x10];
968 	u8         max_wqe_sz_sq[0x10];
969 
970 	u8         reserved_at_2a0[0x10];
971 	u8         max_wqe_sz_rq[0x10];
972 
973 	u8         max_flow_counter_31_16[0x10];
974 	u8         max_wqe_sz_sq_dc[0x10];
975 
976 	u8         reserved_at_2e0[0x7];
977 	u8         max_qp_mcg[0x19];
978 
979 	u8         reserved_at_300[0x18];
980 	u8         log_max_mcg[0x8];
981 
982 	u8         reserved_at_320[0x3];
983 	u8         log_max_transport_domain[0x5];
984 	u8         reserved_at_328[0x3];
985 	u8         log_max_pd[0x5];
986 	u8         reserved_at_330[0xb];
987 	u8         log_max_xrcd[0x5];
988 
989 	u8         reserved_at_340[0x8];
990 	u8         log_max_flow_counter_bulk[0x8];
991 	u8         max_flow_counter_15_0[0x10];
992 
993 
994 	u8         reserved_at_360[0x3];
995 	u8         log_max_rq[0x5];
996 	u8         reserved_at_368[0x3];
997 	u8         log_max_sq[0x5];
998 	u8         reserved_at_370[0x3];
999 	u8         log_max_tir[0x5];
1000 	u8         reserved_at_378[0x3];
1001 	u8         log_max_tis[0x5];
1002 
1003 	u8         basic_cyclic_rcv_wqe[0x1];
1004 	u8         reserved_at_381[0x2];
1005 	u8         log_max_rmp[0x5];
1006 	u8         reserved_at_388[0x3];
1007 	u8         log_max_rqt[0x5];
1008 	u8         reserved_at_390[0x3];
1009 	u8         log_max_rqt_size[0x5];
1010 	u8         reserved_at_398[0x3];
1011 	u8         log_max_tis_per_sq[0x5];
1012 
1013 	u8         reserved_at_3a0[0x3];
1014 	u8         log_max_stride_sz_rq[0x5];
1015 	u8         reserved_at_3a8[0x3];
1016 	u8         log_min_stride_sz_rq[0x5];
1017 	u8         reserved_at_3b0[0x3];
1018 	u8         log_max_stride_sz_sq[0x5];
1019 	u8         reserved_at_3b8[0x3];
1020 	u8         log_min_stride_sz_sq[0x5];
1021 
1022 	u8         reserved_at_3c0[0x1b];
1023 	u8         log_max_wq_sz[0x5];
1024 
1025 	u8         nic_vport_change_event[0x1];
1026 	u8         disable_local_lb_uc[0x1];
1027 	u8         disable_local_lb_mc[0x1];
1028 	u8         reserved_at_3e3[0x8];
1029 	u8         log_max_vlan_list[0x5];
1030 	u8         reserved_at_3f0[0x3];
1031 	u8         log_max_current_mc_list[0x5];
1032 	u8         reserved_at_3f8[0x3];
1033 	u8         log_max_current_uc_list[0x5];
1034 
1035 	u8         reserved_at_400[0x80];
1036 
1037 	u8         reserved_at_480[0x3];
1038 	u8         log_max_l2_table[0x5];
1039 	u8         reserved_at_488[0x8];
1040 	u8         log_uar_page_sz[0x10];
1041 
1042 	u8         reserved_at_4a0[0x20];
1043 	u8         device_frequency_mhz[0x20];
1044 	u8         device_frequency_khz[0x20];
1045 
1046 	u8         reserved_at_500[0x20];
1047 	u8	   num_of_uars_per_page[0x20];
1048 	u8         reserved_at_540[0x40];
1049 
1050 	u8         reserved_at_580[0x3f];
1051 	u8         cqe_compression[0x1];
1052 
1053 	u8         cqe_compression_timeout[0x10];
1054 	u8         cqe_compression_max_num[0x10];
1055 
1056 	u8         reserved_at_5e0[0x10];
1057 	u8         tag_matching[0x1];
1058 	u8         rndv_offload_rc[0x1];
1059 	u8         rndv_offload_dc[0x1];
1060 	u8         log_tag_matching_list_sz[0x5];
1061 	u8         reserved_at_5f8[0x3];
1062 	u8         log_max_xrq[0x5];
1063 
1064 	u8         reserved_at_600[0x200];
1065 };
1066 
1067 enum mlx5_flow_destination_type {
1068 	MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
1069 	MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
1070 	MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
1071 
1072 	MLX5_FLOW_DESTINATION_TYPE_COUNTER      = 0x100,
1073 };
1074 
1075 struct mlx5_ifc_dest_format_struct_bits {
1076 	u8         destination_type[0x8];
1077 	u8         destination_id[0x18];
1078 
1079 	u8         reserved_at_20[0x20];
1080 };
1081 
1082 struct mlx5_ifc_flow_counter_list_bits {
1083 	u8         flow_counter_id[0x20];
1084 
1085 	u8         reserved_at_20[0x20];
1086 };
1087 
1088 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1089 	struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1090 	struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1091 	u8         reserved_at_0[0x40];
1092 };
1093 
1094 struct mlx5_ifc_fte_match_param_bits {
1095 	struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1096 
1097 	struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1098 
1099 	struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1100 
1101 	u8         reserved_at_600[0xa00];
1102 };
1103 
1104 enum {
1105 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1106 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1107 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1108 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1109 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1110 };
1111 
1112 struct mlx5_ifc_rx_hash_field_select_bits {
1113 	u8         l3_prot_type[0x1];
1114 	u8         l4_prot_type[0x1];
1115 	u8         selected_fields[0x1e];
1116 };
1117 
1118 enum {
1119 	MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
1120 	MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
1121 };
1122 
1123 enum {
1124 	MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
1125 	MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
1126 };
1127 
1128 struct mlx5_ifc_wq_bits {
1129 	u8         wq_type[0x4];
1130 	u8         wq_signature[0x1];
1131 	u8         end_padding_mode[0x2];
1132 	u8         cd_slave[0x1];
1133 	u8         reserved_at_8[0x18];
1134 
1135 	u8         hds_skip_first_sge[0x1];
1136 	u8         log2_hds_buf_size[0x3];
1137 	u8         reserved_at_24[0x7];
1138 	u8         page_offset[0x5];
1139 	u8         lwm[0x10];
1140 
1141 	u8         reserved_at_40[0x8];
1142 	u8         pd[0x18];
1143 
1144 	u8         reserved_at_60[0x8];
1145 	u8         uar_page[0x18];
1146 
1147 	u8         dbr_addr[0x40];
1148 
1149 	u8         hw_counter[0x20];
1150 
1151 	u8         sw_counter[0x20];
1152 
1153 	u8         reserved_at_100[0xc];
1154 	u8         log_wq_stride[0x4];
1155 	u8         reserved_at_110[0x3];
1156 	u8         log_wq_pg_sz[0x5];
1157 	u8         reserved_at_118[0x3];
1158 	u8         log_wq_sz[0x5];
1159 
1160 	u8         reserved_at_120[0x15];
1161 	u8         log_wqe_num_of_strides[0x3];
1162 	u8         two_byte_shift_en[0x1];
1163 	u8         reserved_at_139[0x4];
1164 	u8         log_wqe_stride_size[0x3];
1165 
1166 	u8         reserved_at_140[0x4c0];
1167 
1168 	struct mlx5_ifc_cmd_pas_bits pas[0];
1169 };
1170 
1171 struct mlx5_ifc_rq_num_bits {
1172 	u8         reserved_at_0[0x8];
1173 	u8         rq_num[0x18];
1174 };
1175 
1176 struct mlx5_ifc_mac_address_layout_bits {
1177 	u8         reserved_at_0[0x10];
1178 	u8         mac_addr_47_32[0x10];
1179 
1180 	u8         mac_addr_31_0[0x20];
1181 };
1182 
1183 struct mlx5_ifc_vlan_layout_bits {
1184 	u8         reserved_at_0[0x14];
1185 	u8         vlan[0x0c];
1186 
1187 	u8         reserved_at_20[0x20];
1188 };
1189 
1190 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1191 	u8         reserved_at_0[0xa0];
1192 
1193 	u8         min_time_between_cnps[0x20];
1194 
1195 	u8         reserved_at_c0[0x12];
1196 	u8         cnp_dscp[0x6];
1197 	u8         reserved_at_d8[0x4];
1198 	u8         cnp_prio_mode[0x1];
1199 	u8         cnp_802p_prio[0x3];
1200 
1201 	u8         reserved_at_e0[0x720];
1202 };
1203 
1204 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1205 	u8         reserved_at_0[0x60];
1206 
1207 	u8         reserved_at_60[0x4];
1208 	u8         clamp_tgt_rate[0x1];
1209 	u8         reserved_at_65[0x3];
1210 	u8         clamp_tgt_rate_after_time_inc[0x1];
1211 	u8         reserved_at_69[0x17];
1212 
1213 	u8         reserved_at_80[0x20];
1214 
1215 	u8         rpg_time_reset[0x20];
1216 
1217 	u8         rpg_byte_reset[0x20];
1218 
1219 	u8         rpg_threshold[0x20];
1220 
1221 	u8         rpg_max_rate[0x20];
1222 
1223 	u8         rpg_ai_rate[0x20];
1224 
1225 	u8         rpg_hai_rate[0x20];
1226 
1227 	u8         rpg_gd[0x20];
1228 
1229 	u8         rpg_min_dec_fac[0x20];
1230 
1231 	u8         rpg_min_rate[0x20];
1232 
1233 	u8         reserved_at_1c0[0xe0];
1234 
1235 	u8         rate_to_set_on_first_cnp[0x20];
1236 
1237 	u8         dce_tcp_g[0x20];
1238 
1239 	u8         dce_tcp_rtt[0x20];
1240 
1241 	u8         rate_reduce_monitor_period[0x20];
1242 
1243 	u8         reserved_at_320[0x20];
1244 
1245 	u8         initial_alpha_value[0x20];
1246 
1247 	u8         reserved_at_360[0x4a0];
1248 };
1249 
1250 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1251 	u8         reserved_at_0[0x80];
1252 
1253 	u8         rppp_max_rps[0x20];
1254 
1255 	u8         rpg_time_reset[0x20];
1256 
1257 	u8         rpg_byte_reset[0x20];
1258 
1259 	u8         rpg_threshold[0x20];
1260 
1261 	u8         rpg_max_rate[0x20];
1262 
1263 	u8         rpg_ai_rate[0x20];
1264 
1265 	u8         rpg_hai_rate[0x20];
1266 
1267 	u8         rpg_gd[0x20];
1268 
1269 	u8         rpg_min_dec_fac[0x20];
1270 
1271 	u8         rpg_min_rate[0x20];
1272 
1273 	u8         reserved_at_1c0[0x640];
1274 };
1275 
1276 enum {
1277 	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1278 	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1279 	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1280 };
1281 
1282 struct mlx5_ifc_resize_field_select_bits {
1283 	u8         resize_field_select[0x20];
1284 };
1285 
1286 enum {
1287 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1288 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1289 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1290 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1291 };
1292 
1293 struct mlx5_ifc_modify_field_select_bits {
1294 	u8         modify_field_select[0x20];
1295 };
1296 
1297 struct mlx5_ifc_field_select_r_roce_np_bits {
1298 	u8         field_select_r_roce_np[0x20];
1299 };
1300 
1301 struct mlx5_ifc_field_select_r_roce_rp_bits {
1302 	u8         field_select_r_roce_rp[0x20];
1303 };
1304 
1305 enum {
1306 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1307 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1308 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1309 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1310 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1311 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1312 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1313 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1314 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1315 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1316 };
1317 
1318 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1319 	u8         field_select_8021qaurp[0x20];
1320 };
1321 
1322 struct mlx5_ifc_phys_layer_cntrs_bits {
1323 	u8         time_since_last_clear_high[0x20];
1324 
1325 	u8         time_since_last_clear_low[0x20];
1326 
1327 	u8         symbol_errors_high[0x20];
1328 
1329 	u8         symbol_errors_low[0x20];
1330 
1331 	u8         sync_headers_errors_high[0x20];
1332 
1333 	u8         sync_headers_errors_low[0x20];
1334 
1335 	u8         edpl_bip_errors_lane0_high[0x20];
1336 
1337 	u8         edpl_bip_errors_lane0_low[0x20];
1338 
1339 	u8         edpl_bip_errors_lane1_high[0x20];
1340 
1341 	u8         edpl_bip_errors_lane1_low[0x20];
1342 
1343 	u8         edpl_bip_errors_lane2_high[0x20];
1344 
1345 	u8         edpl_bip_errors_lane2_low[0x20];
1346 
1347 	u8         edpl_bip_errors_lane3_high[0x20];
1348 
1349 	u8         edpl_bip_errors_lane3_low[0x20];
1350 
1351 	u8         fc_fec_corrected_blocks_lane0_high[0x20];
1352 
1353 	u8         fc_fec_corrected_blocks_lane0_low[0x20];
1354 
1355 	u8         fc_fec_corrected_blocks_lane1_high[0x20];
1356 
1357 	u8         fc_fec_corrected_blocks_lane1_low[0x20];
1358 
1359 	u8         fc_fec_corrected_blocks_lane2_high[0x20];
1360 
1361 	u8         fc_fec_corrected_blocks_lane2_low[0x20];
1362 
1363 	u8         fc_fec_corrected_blocks_lane3_high[0x20];
1364 
1365 	u8         fc_fec_corrected_blocks_lane3_low[0x20];
1366 
1367 	u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
1368 
1369 	u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
1370 
1371 	u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
1372 
1373 	u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
1374 
1375 	u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
1376 
1377 	u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
1378 
1379 	u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
1380 
1381 	u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
1382 
1383 	u8         rs_fec_corrected_blocks_high[0x20];
1384 
1385 	u8         rs_fec_corrected_blocks_low[0x20];
1386 
1387 	u8         rs_fec_uncorrectable_blocks_high[0x20];
1388 
1389 	u8         rs_fec_uncorrectable_blocks_low[0x20];
1390 
1391 	u8         rs_fec_no_errors_blocks_high[0x20];
1392 
1393 	u8         rs_fec_no_errors_blocks_low[0x20];
1394 
1395 	u8         rs_fec_single_error_blocks_high[0x20];
1396 
1397 	u8         rs_fec_single_error_blocks_low[0x20];
1398 
1399 	u8         rs_fec_corrected_symbols_total_high[0x20];
1400 
1401 	u8         rs_fec_corrected_symbols_total_low[0x20];
1402 
1403 	u8         rs_fec_corrected_symbols_lane0_high[0x20];
1404 
1405 	u8         rs_fec_corrected_symbols_lane0_low[0x20];
1406 
1407 	u8         rs_fec_corrected_symbols_lane1_high[0x20];
1408 
1409 	u8         rs_fec_corrected_symbols_lane1_low[0x20];
1410 
1411 	u8         rs_fec_corrected_symbols_lane2_high[0x20];
1412 
1413 	u8         rs_fec_corrected_symbols_lane2_low[0x20];
1414 
1415 	u8         rs_fec_corrected_symbols_lane3_high[0x20];
1416 
1417 	u8         rs_fec_corrected_symbols_lane3_low[0x20];
1418 
1419 	u8         link_down_events[0x20];
1420 
1421 	u8         successful_recovery_events[0x20];
1422 
1423 	u8         reserved_at_640[0x180];
1424 };
1425 
1426 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1427 	u8         time_since_last_clear_high[0x20];
1428 
1429 	u8         time_since_last_clear_low[0x20];
1430 
1431 	u8         phy_received_bits_high[0x20];
1432 
1433 	u8         phy_received_bits_low[0x20];
1434 
1435 	u8         phy_symbol_errors_high[0x20];
1436 
1437 	u8         phy_symbol_errors_low[0x20];
1438 
1439 	u8         phy_corrected_bits_high[0x20];
1440 
1441 	u8         phy_corrected_bits_low[0x20];
1442 
1443 	u8         phy_corrected_bits_lane0_high[0x20];
1444 
1445 	u8         phy_corrected_bits_lane0_low[0x20];
1446 
1447 	u8         phy_corrected_bits_lane1_high[0x20];
1448 
1449 	u8         phy_corrected_bits_lane1_low[0x20];
1450 
1451 	u8         phy_corrected_bits_lane2_high[0x20];
1452 
1453 	u8         phy_corrected_bits_lane2_low[0x20];
1454 
1455 	u8         phy_corrected_bits_lane3_high[0x20];
1456 
1457 	u8         phy_corrected_bits_lane3_low[0x20];
1458 
1459 	u8         reserved_at_200[0x5c0];
1460 };
1461 
1462 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1463 	u8	   symbol_error_counter[0x10];
1464 
1465 	u8         link_error_recovery_counter[0x8];
1466 
1467 	u8         link_downed_counter[0x8];
1468 
1469 	u8         port_rcv_errors[0x10];
1470 
1471 	u8         port_rcv_remote_physical_errors[0x10];
1472 
1473 	u8         port_rcv_switch_relay_errors[0x10];
1474 
1475 	u8         port_xmit_discards[0x10];
1476 
1477 	u8         port_xmit_constraint_errors[0x8];
1478 
1479 	u8         port_rcv_constraint_errors[0x8];
1480 
1481 	u8         reserved_at_70[0x8];
1482 
1483 	u8         link_overrun_errors[0x8];
1484 
1485 	u8	   reserved_at_80[0x10];
1486 
1487 	u8         vl_15_dropped[0x10];
1488 
1489 	u8	   reserved_at_a0[0x80];
1490 
1491 	u8         port_xmit_wait[0x20];
1492 };
1493 
1494 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1495 	u8         transmit_queue_high[0x20];
1496 
1497 	u8         transmit_queue_low[0x20];
1498 
1499 	u8         reserved_at_40[0x780];
1500 };
1501 
1502 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1503 	u8         rx_octets_high[0x20];
1504 
1505 	u8         rx_octets_low[0x20];
1506 
1507 	u8         reserved_at_40[0xc0];
1508 
1509 	u8         rx_frames_high[0x20];
1510 
1511 	u8         rx_frames_low[0x20];
1512 
1513 	u8         tx_octets_high[0x20];
1514 
1515 	u8         tx_octets_low[0x20];
1516 
1517 	u8         reserved_at_180[0xc0];
1518 
1519 	u8         tx_frames_high[0x20];
1520 
1521 	u8         tx_frames_low[0x20];
1522 
1523 	u8         rx_pause_high[0x20];
1524 
1525 	u8         rx_pause_low[0x20];
1526 
1527 	u8         rx_pause_duration_high[0x20];
1528 
1529 	u8         rx_pause_duration_low[0x20];
1530 
1531 	u8         tx_pause_high[0x20];
1532 
1533 	u8         tx_pause_low[0x20];
1534 
1535 	u8         tx_pause_duration_high[0x20];
1536 
1537 	u8         tx_pause_duration_low[0x20];
1538 
1539 	u8         rx_pause_transition_high[0x20];
1540 
1541 	u8         rx_pause_transition_low[0x20];
1542 
1543 	u8         reserved_at_3c0[0x400];
1544 };
1545 
1546 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1547 	u8         port_transmit_wait_high[0x20];
1548 
1549 	u8         port_transmit_wait_low[0x20];
1550 
1551 	u8         reserved_at_40[0x100];
1552 
1553 	u8         rx_buffer_almost_full_high[0x20];
1554 
1555 	u8         rx_buffer_almost_full_low[0x20];
1556 
1557 	u8         rx_buffer_full_high[0x20];
1558 
1559 	u8         rx_buffer_full_low[0x20];
1560 
1561 	u8         reserved_at_1c0[0x600];
1562 };
1563 
1564 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1565 	u8         dot3stats_alignment_errors_high[0x20];
1566 
1567 	u8         dot3stats_alignment_errors_low[0x20];
1568 
1569 	u8         dot3stats_fcs_errors_high[0x20];
1570 
1571 	u8         dot3stats_fcs_errors_low[0x20];
1572 
1573 	u8         dot3stats_single_collision_frames_high[0x20];
1574 
1575 	u8         dot3stats_single_collision_frames_low[0x20];
1576 
1577 	u8         dot3stats_multiple_collision_frames_high[0x20];
1578 
1579 	u8         dot3stats_multiple_collision_frames_low[0x20];
1580 
1581 	u8         dot3stats_sqe_test_errors_high[0x20];
1582 
1583 	u8         dot3stats_sqe_test_errors_low[0x20];
1584 
1585 	u8         dot3stats_deferred_transmissions_high[0x20];
1586 
1587 	u8         dot3stats_deferred_transmissions_low[0x20];
1588 
1589 	u8         dot3stats_late_collisions_high[0x20];
1590 
1591 	u8         dot3stats_late_collisions_low[0x20];
1592 
1593 	u8         dot3stats_excessive_collisions_high[0x20];
1594 
1595 	u8         dot3stats_excessive_collisions_low[0x20];
1596 
1597 	u8         dot3stats_internal_mac_transmit_errors_high[0x20];
1598 
1599 	u8         dot3stats_internal_mac_transmit_errors_low[0x20];
1600 
1601 	u8         dot3stats_carrier_sense_errors_high[0x20];
1602 
1603 	u8         dot3stats_carrier_sense_errors_low[0x20];
1604 
1605 	u8         dot3stats_frame_too_longs_high[0x20];
1606 
1607 	u8         dot3stats_frame_too_longs_low[0x20];
1608 
1609 	u8         dot3stats_internal_mac_receive_errors_high[0x20];
1610 
1611 	u8         dot3stats_internal_mac_receive_errors_low[0x20];
1612 
1613 	u8         dot3stats_symbol_errors_high[0x20];
1614 
1615 	u8         dot3stats_symbol_errors_low[0x20];
1616 
1617 	u8         dot3control_in_unknown_opcodes_high[0x20];
1618 
1619 	u8         dot3control_in_unknown_opcodes_low[0x20];
1620 
1621 	u8         dot3in_pause_frames_high[0x20];
1622 
1623 	u8         dot3in_pause_frames_low[0x20];
1624 
1625 	u8         dot3out_pause_frames_high[0x20];
1626 
1627 	u8         dot3out_pause_frames_low[0x20];
1628 
1629 	u8         reserved_at_400[0x3c0];
1630 };
1631 
1632 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1633 	u8         ether_stats_drop_events_high[0x20];
1634 
1635 	u8         ether_stats_drop_events_low[0x20];
1636 
1637 	u8         ether_stats_octets_high[0x20];
1638 
1639 	u8         ether_stats_octets_low[0x20];
1640 
1641 	u8         ether_stats_pkts_high[0x20];
1642 
1643 	u8         ether_stats_pkts_low[0x20];
1644 
1645 	u8         ether_stats_broadcast_pkts_high[0x20];
1646 
1647 	u8         ether_stats_broadcast_pkts_low[0x20];
1648 
1649 	u8         ether_stats_multicast_pkts_high[0x20];
1650 
1651 	u8         ether_stats_multicast_pkts_low[0x20];
1652 
1653 	u8         ether_stats_crc_align_errors_high[0x20];
1654 
1655 	u8         ether_stats_crc_align_errors_low[0x20];
1656 
1657 	u8         ether_stats_undersize_pkts_high[0x20];
1658 
1659 	u8         ether_stats_undersize_pkts_low[0x20];
1660 
1661 	u8         ether_stats_oversize_pkts_high[0x20];
1662 
1663 	u8         ether_stats_oversize_pkts_low[0x20];
1664 
1665 	u8         ether_stats_fragments_high[0x20];
1666 
1667 	u8         ether_stats_fragments_low[0x20];
1668 
1669 	u8         ether_stats_jabbers_high[0x20];
1670 
1671 	u8         ether_stats_jabbers_low[0x20];
1672 
1673 	u8         ether_stats_collisions_high[0x20];
1674 
1675 	u8         ether_stats_collisions_low[0x20];
1676 
1677 	u8         ether_stats_pkts64octets_high[0x20];
1678 
1679 	u8         ether_stats_pkts64octets_low[0x20];
1680 
1681 	u8         ether_stats_pkts65to127octets_high[0x20];
1682 
1683 	u8         ether_stats_pkts65to127octets_low[0x20];
1684 
1685 	u8         ether_stats_pkts128to255octets_high[0x20];
1686 
1687 	u8         ether_stats_pkts128to255octets_low[0x20];
1688 
1689 	u8         ether_stats_pkts256to511octets_high[0x20];
1690 
1691 	u8         ether_stats_pkts256to511octets_low[0x20];
1692 
1693 	u8         ether_stats_pkts512to1023octets_high[0x20];
1694 
1695 	u8         ether_stats_pkts512to1023octets_low[0x20];
1696 
1697 	u8         ether_stats_pkts1024to1518octets_high[0x20];
1698 
1699 	u8         ether_stats_pkts1024to1518octets_low[0x20];
1700 
1701 	u8         ether_stats_pkts1519to2047octets_high[0x20];
1702 
1703 	u8         ether_stats_pkts1519to2047octets_low[0x20];
1704 
1705 	u8         ether_stats_pkts2048to4095octets_high[0x20];
1706 
1707 	u8         ether_stats_pkts2048to4095octets_low[0x20];
1708 
1709 	u8         ether_stats_pkts4096to8191octets_high[0x20];
1710 
1711 	u8         ether_stats_pkts4096to8191octets_low[0x20];
1712 
1713 	u8         ether_stats_pkts8192to10239octets_high[0x20];
1714 
1715 	u8         ether_stats_pkts8192to10239octets_low[0x20];
1716 
1717 	u8         reserved_at_540[0x280];
1718 };
1719 
1720 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1721 	u8         if_in_octets_high[0x20];
1722 
1723 	u8         if_in_octets_low[0x20];
1724 
1725 	u8         if_in_ucast_pkts_high[0x20];
1726 
1727 	u8         if_in_ucast_pkts_low[0x20];
1728 
1729 	u8         if_in_discards_high[0x20];
1730 
1731 	u8         if_in_discards_low[0x20];
1732 
1733 	u8         if_in_errors_high[0x20];
1734 
1735 	u8         if_in_errors_low[0x20];
1736 
1737 	u8         if_in_unknown_protos_high[0x20];
1738 
1739 	u8         if_in_unknown_protos_low[0x20];
1740 
1741 	u8         if_out_octets_high[0x20];
1742 
1743 	u8         if_out_octets_low[0x20];
1744 
1745 	u8         if_out_ucast_pkts_high[0x20];
1746 
1747 	u8         if_out_ucast_pkts_low[0x20];
1748 
1749 	u8         if_out_discards_high[0x20];
1750 
1751 	u8         if_out_discards_low[0x20];
1752 
1753 	u8         if_out_errors_high[0x20];
1754 
1755 	u8         if_out_errors_low[0x20];
1756 
1757 	u8         if_in_multicast_pkts_high[0x20];
1758 
1759 	u8         if_in_multicast_pkts_low[0x20];
1760 
1761 	u8         if_in_broadcast_pkts_high[0x20];
1762 
1763 	u8         if_in_broadcast_pkts_low[0x20];
1764 
1765 	u8         if_out_multicast_pkts_high[0x20];
1766 
1767 	u8         if_out_multicast_pkts_low[0x20];
1768 
1769 	u8         if_out_broadcast_pkts_high[0x20];
1770 
1771 	u8         if_out_broadcast_pkts_low[0x20];
1772 
1773 	u8         reserved_at_340[0x480];
1774 };
1775 
1776 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1777 	u8         a_frames_transmitted_ok_high[0x20];
1778 
1779 	u8         a_frames_transmitted_ok_low[0x20];
1780 
1781 	u8         a_frames_received_ok_high[0x20];
1782 
1783 	u8         a_frames_received_ok_low[0x20];
1784 
1785 	u8         a_frame_check_sequence_errors_high[0x20];
1786 
1787 	u8         a_frame_check_sequence_errors_low[0x20];
1788 
1789 	u8         a_alignment_errors_high[0x20];
1790 
1791 	u8         a_alignment_errors_low[0x20];
1792 
1793 	u8         a_octets_transmitted_ok_high[0x20];
1794 
1795 	u8         a_octets_transmitted_ok_low[0x20];
1796 
1797 	u8         a_octets_received_ok_high[0x20];
1798 
1799 	u8         a_octets_received_ok_low[0x20];
1800 
1801 	u8         a_multicast_frames_xmitted_ok_high[0x20];
1802 
1803 	u8         a_multicast_frames_xmitted_ok_low[0x20];
1804 
1805 	u8         a_broadcast_frames_xmitted_ok_high[0x20];
1806 
1807 	u8         a_broadcast_frames_xmitted_ok_low[0x20];
1808 
1809 	u8         a_multicast_frames_received_ok_high[0x20];
1810 
1811 	u8         a_multicast_frames_received_ok_low[0x20];
1812 
1813 	u8         a_broadcast_frames_received_ok_high[0x20];
1814 
1815 	u8         a_broadcast_frames_received_ok_low[0x20];
1816 
1817 	u8         a_in_range_length_errors_high[0x20];
1818 
1819 	u8         a_in_range_length_errors_low[0x20];
1820 
1821 	u8         a_out_of_range_length_field_high[0x20];
1822 
1823 	u8         a_out_of_range_length_field_low[0x20];
1824 
1825 	u8         a_frame_too_long_errors_high[0x20];
1826 
1827 	u8         a_frame_too_long_errors_low[0x20];
1828 
1829 	u8         a_symbol_error_during_carrier_high[0x20];
1830 
1831 	u8         a_symbol_error_during_carrier_low[0x20];
1832 
1833 	u8         a_mac_control_frames_transmitted_high[0x20];
1834 
1835 	u8         a_mac_control_frames_transmitted_low[0x20];
1836 
1837 	u8         a_mac_control_frames_received_high[0x20];
1838 
1839 	u8         a_mac_control_frames_received_low[0x20];
1840 
1841 	u8         a_unsupported_opcodes_received_high[0x20];
1842 
1843 	u8         a_unsupported_opcodes_received_low[0x20];
1844 
1845 	u8         a_pause_mac_ctrl_frames_received_high[0x20];
1846 
1847 	u8         a_pause_mac_ctrl_frames_received_low[0x20];
1848 
1849 	u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
1850 
1851 	u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
1852 
1853 	u8         reserved_at_4c0[0x300];
1854 };
1855 
1856 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
1857 	u8         life_time_counter_high[0x20];
1858 
1859 	u8         life_time_counter_low[0x20];
1860 
1861 	u8         rx_errors[0x20];
1862 
1863 	u8         tx_errors[0x20];
1864 
1865 	u8         l0_to_recovery_eieos[0x20];
1866 
1867 	u8         l0_to_recovery_ts[0x20];
1868 
1869 	u8         l0_to_recovery_framing[0x20];
1870 
1871 	u8         l0_to_recovery_retrain[0x20];
1872 
1873 	u8         crc_error_dllp[0x20];
1874 
1875 	u8         crc_error_tlp[0x20];
1876 
1877 	u8         tx_overflow_buffer_pkt_high[0x20];
1878 
1879 	u8         tx_overflow_buffer_pkt_low[0x20];
1880 
1881 	u8         outbound_stalled_reads[0x20];
1882 
1883 	u8         outbound_stalled_writes[0x20];
1884 
1885 	u8         outbound_stalled_reads_events[0x20];
1886 
1887 	u8         outbound_stalled_writes_events[0x20];
1888 
1889 	u8         reserved_at_200[0x5c0];
1890 };
1891 
1892 struct mlx5_ifc_cmd_inter_comp_event_bits {
1893 	u8         command_completion_vector[0x20];
1894 
1895 	u8         reserved_at_20[0xc0];
1896 };
1897 
1898 struct mlx5_ifc_stall_vl_event_bits {
1899 	u8         reserved_at_0[0x18];
1900 	u8         port_num[0x1];
1901 	u8         reserved_at_19[0x3];
1902 	u8         vl[0x4];
1903 
1904 	u8         reserved_at_20[0xa0];
1905 };
1906 
1907 struct mlx5_ifc_db_bf_congestion_event_bits {
1908 	u8         event_subtype[0x8];
1909 	u8         reserved_at_8[0x8];
1910 	u8         congestion_level[0x8];
1911 	u8         reserved_at_18[0x8];
1912 
1913 	u8         reserved_at_20[0xa0];
1914 };
1915 
1916 struct mlx5_ifc_gpio_event_bits {
1917 	u8         reserved_at_0[0x60];
1918 
1919 	u8         gpio_event_hi[0x20];
1920 
1921 	u8         gpio_event_lo[0x20];
1922 
1923 	u8         reserved_at_a0[0x40];
1924 };
1925 
1926 struct mlx5_ifc_port_state_change_event_bits {
1927 	u8         reserved_at_0[0x40];
1928 
1929 	u8         port_num[0x4];
1930 	u8         reserved_at_44[0x1c];
1931 
1932 	u8         reserved_at_60[0x80];
1933 };
1934 
1935 struct mlx5_ifc_dropped_packet_logged_bits {
1936 	u8         reserved_at_0[0xe0];
1937 };
1938 
1939 enum {
1940 	MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
1941 	MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
1942 };
1943 
1944 struct mlx5_ifc_cq_error_bits {
1945 	u8         reserved_at_0[0x8];
1946 	u8         cqn[0x18];
1947 
1948 	u8         reserved_at_20[0x20];
1949 
1950 	u8         reserved_at_40[0x18];
1951 	u8         syndrome[0x8];
1952 
1953 	u8         reserved_at_60[0x80];
1954 };
1955 
1956 struct mlx5_ifc_rdma_page_fault_event_bits {
1957 	u8         bytes_committed[0x20];
1958 
1959 	u8         r_key[0x20];
1960 
1961 	u8         reserved_at_40[0x10];
1962 	u8         packet_len[0x10];
1963 
1964 	u8         rdma_op_len[0x20];
1965 
1966 	u8         rdma_va[0x40];
1967 
1968 	u8         reserved_at_c0[0x5];
1969 	u8         rdma[0x1];
1970 	u8         write[0x1];
1971 	u8         requestor[0x1];
1972 	u8         qp_number[0x18];
1973 };
1974 
1975 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1976 	u8         bytes_committed[0x20];
1977 
1978 	u8         reserved_at_20[0x10];
1979 	u8         wqe_index[0x10];
1980 
1981 	u8         reserved_at_40[0x10];
1982 	u8         len[0x10];
1983 
1984 	u8         reserved_at_60[0x60];
1985 
1986 	u8         reserved_at_c0[0x5];
1987 	u8         rdma[0x1];
1988 	u8         write_read[0x1];
1989 	u8         requestor[0x1];
1990 	u8         qpn[0x18];
1991 };
1992 
1993 struct mlx5_ifc_qp_events_bits {
1994 	u8         reserved_at_0[0xa0];
1995 
1996 	u8         type[0x8];
1997 	u8         reserved_at_a8[0x18];
1998 
1999 	u8         reserved_at_c0[0x8];
2000 	u8         qpn_rqn_sqn[0x18];
2001 };
2002 
2003 struct mlx5_ifc_dct_events_bits {
2004 	u8         reserved_at_0[0xc0];
2005 
2006 	u8         reserved_at_c0[0x8];
2007 	u8         dct_number[0x18];
2008 };
2009 
2010 struct mlx5_ifc_comp_event_bits {
2011 	u8         reserved_at_0[0xc0];
2012 
2013 	u8         reserved_at_c0[0x8];
2014 	u8         cq_number[0x18];
2015 };
2016 
2017 enum {
2018 	MLX5_QPC_STATE_RST        = 0x0,
2019 	MLX5_QPC_STATE_INIT       = 0x1,
2020 	MLX5_QPC_STATE_RTR        = 0x2,
2021 	MLX5_QPC_STATE_RTS        = 0x3,
2022 	MLX5_QPC_STATE_SQER       = 0x4,
2023 	MLX5_QPC_STATE_ERR        = 0x6,
2024 	MLX5_QPC_STATE_SQD        = 0x7,
2025 	MLX5_QPC_STATE_SUSPENDED  = 0x9,
2026 };
2027 
2028 enum {
2029 	MLX5_QPC_ST_RC            = 0x0,
2030 	MLX5_QPC_ST_UC            = 0x1,
2031 	MLX5_QPC_ST_UD            = 0x2,
2032 	MLX5_QPC_ST_XRC           = 0x3,
2033 	MLX5_QPC_ST_DCI           = 0x5,
2034 	MLX5_QPC_ST_QP0           = 0x7,
2035 	MLX5_QPC_ST_QP1           = 0x8,
2036 	MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
2037 	MLX5_QPC_ST_REG_UMR       = 0xc,
2038 };
2039 
2040 enum {
2041 	MLX5_QPC_PM_STATE_ARMED     = 0x0,
2042 	MLX5_QPC_PM_STATE_REARM     = 0x1,
2043 	MLX5_QPC_PM_STATE_RESERVED  = 0x2,
2044 	MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
2045 };
2046 
2047 enum {
2048 	MLX5_QPC_OFFLOAD_TYPE_RNDV  = 0x1,
2049 };
2050 
2051 enum {
2052 	MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
2053 	MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
2054 };
2055 
2056 enum {
2057 	MLX5_QPC_MTU_256_BYTES        = 0x1,
2058 	MLX5_QPC_MTU_512_BYTES        = 0x2,
2059 	MLX5_QPC_MTU_1K_BYTES         = 0x3,
2060 	MLX5_QPC_MTU_2K_BYTES         = 0x4,
2061 	MLX5_QPC_MTU_4K_BYTES         = 0x5,
2062 	MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
2063 };
2064 
2065 enum {
2066 	MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
2067 	MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
2068 	MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
2069 	MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
2070 	MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
2071 	MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
2072 	MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
2073 	MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
2074 };
2075 
2076 enum {
2077 	MLX5_QPC_CS_REQ_DISABLE    = 0x0,
2078 	MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
2079 	MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
2080 };
2081 
2082 enum {
2083 	MLX5_QPC_CS_RES_DISABLE    = 0x0,
2084 	MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
2085 	MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
2086 };
2087 
2088 struct mlx5_ifc_qpc_bits {
2089 	u8         state[0x4];
2090 	u8         lag_tx_port_affinity[0x4];
2091 	u8         st[0x8];
2092 	u8         reserved_at_10[0x3];
2093 	u8         pm_state[0x2];
2094 	u8         reserved_at_15[0x3];
2095 	u8         offload_type[0x4];
2096 	u8         end_padding_mode[0x2];
2097 	u8         reserved_at_1e[0x2];
2098 
2099 	u8         wq_signature[0x1];
2100 	u8         block_lb_mc[0x1];
2101 	u8         atomic_like_write_en[0x1];
2102 	u8         latency_sensitive[0x1];
2103 	u8         reserved_at_24[0x1];
2104 	u8         drain_sigerr[0x1];
2105 	u8         reserved_at_26[0x2];
2106 	u8         pd[0x18];
2107 
2108 	u8         mtu[0x3];
2109 	u8         log_msg_max[0x5];
2110 	u8         reserved_at_48[0x1];
2111 	u8         log_rq_size[0x4];
2112 	u8         log_rq_stride[0x3];
2113 	u8         no_sq[0x1];
2114 	u8         log_sq_size[0x4];
2115 	u8         reserved_at_55[0x6];
2116 	u8         rlky[0x1];
2117 	u8         ulp_stateless_offload_mode[0x4];
2118 
2119 	u8         counter_set_id[0x8];
2120 	u8         uar_page[0x18];
2121 
2122 	u8         reserved_at_80[0x8];
2123 	u8         user_index[0x18];
2124 
2125 	u8         reserved_at_a0[0x3];
2126 	u8         log_page_size[0x5];
2127 	u8         remote_qpn[0x18];
2128 
2129 	struct mlx5_ifc_ads_bits primary_address_path;
2130 
2131 	struct mlx5_ifc_ads_bits secondary_address_path;
2132 
2133 	u8         log_ack_req_freq[0x4];
2134 	u8         reserved_at_384[0x4];
2135 	u8         log_sra_max[0x3];
2136 	u8         reserved_at_38b[0x2];
2137 	u8         retry_count[0x3];
2138 	u8         rnr_retry[0x3];
2139 	u8         reserved_at_393[0x1];
2140 	u8         fre[0x1];
2141 	u8         cur_rnr_retry[0x3];
2142 	u8         cur_retry_count[0x3];
2143 	u8         reserved_at_39b[0x5];
2144 
2145 	u8         reserved_at_3a0[0x20];
2146 
2147 	u8         reserved_at_3c0[0x8];
2148 	u8         next_send_psn[0x18];
2149 
2150 	u8         reserved_at_3e0[0x8];
2151 	u8         cqn_snd[0x18];
2152 
2153 	u8         reserved_at_400[0x8];
2154 	u8         deth_sqpn[0x18];
2155 
2156 	u8         reserved_at_420[0x20];
2157 
2158 	u8         reserved_at_440[0x8];
2159 	u8         last_acked_psn[0x18];
2160 
2161 	u8         reserved_at_460[0x8];
2162 	u8         ssn[0x18];
2163 
2164 	u8         reserved_at_480[0x8];
2165 	u8         log_rra_max[0x3];
2166 	u8         reserved_at_48b[0x1];
2167 	u8         atomic_mode[0x4];
2168 	u8         rre[0x1];
2169 	u8         rwe[0x1];
2170 	u8         rae[0x1];
2171 	u8         reserved_at_493[0x1];
2172 	u8         page_offset[0x6];
2173 	u8         reserved_at_49a[0x3];
2174 	u8         cd_slave_receive[0x1];
2175 	u8         cd_slave_send[0x1];
2176 	u8         cd_master[0x1];
2177 
2178 	u8         reserved_at_4a0[0x3];
2179 	u8         min_rnr_nak[0x5];
2180 	u8         next_rcv_psn[0x18];
2181 
2182 	u8         reserved_at_4c0[0x8];
2183 	u8         xrcd[0x18];
2184 
2185 	u8         reserved_at_4e0[0x8];
2186 	u8         cqn_rcv[0x18];
2187 
2188 	u8         dbr_addr[0x40];
2189 
2190 	u8         q_key[0x20];
2191 
2192 	u8         reserved_at_560[0x5];
2193 	u8         rq_type[0x3];
2194 	u8         srqn_rmpn_xrqn[0x18];
2195 
2196 	u8         reserved_at_580[0x8];
2197 	u8         rmsn[0x18];
2198 
2199 	u8         hw_sq_wqebb_counter[0x10];
2200 	u8         sw_sq_wqebb_counter[0x10];
2201 
2202 	u8         hw_rq_counter[0x20];
2203 
2204 	u8         sw_rq_counter[0x20];
2205 
2206 	u8         reserved_at_600[0x20];
2207 
2208 	u8         reserved_at_620[0xf];
2209 	u8         cgs[0x1];
2210 	u8         cs_req[0x8];
2211 	u8         cs_res[0x8];
2212 
2213 	u8         dc_access_key[0x40];
2214 
2215 	u8         reserved_at_680[0xc0];
2216 };
2217 
2218 struct mlx5_ifc_roce_addr_layout_bits {
2219 	u8         source_l3_address[16][0x8];
2220 
2221 	u8         reserved_at_80[0x3];
2222 	u8         vlan_valid[0x1];
2223 	u8         vlan_id[0xc];
2224 	u8         source_mac_47_32[0x10];
2225 
2226 	u8         source_mac_31_0[0x20];
2227 
2228 	u8         reserved_at_c0[0x14];
2229 	u8         roce_l3_type[0x4];
2230 	u8         roce_version[0x8];
2231 
2232 	u8         reserved_at_e0[0x20];
2233 };
2234 
2235 union mlx5_ifc_hca_cap_union_bits {
2236 	struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2237 	struct mlx5_ifc_odp_cap_bits odp_cap;
2238 	struct mlx5_ifc_atomic_caps_bits atomic_caps;
2239 	struct mlx5_ifc_roce_cap_bits roce_cap;
2240 	struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2241 	struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2242 	struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2243 	struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2244 	struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2245 	struct mlx5_ifc_qos_cap_bits qos_cap;
2246 	struct mlx5_ifc_fpga_cap_bits fpga_cap;
2247 	u8         reserved_at_0[0x8000];
2248 };
2249 
2250 enum {
2251 	MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
2252 	MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
2253 	MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
2254 	MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
2255 	MLX5_FLOW_CONTEXT_ACTION_ENCAP     = 0x10,
2256 	MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
2257 	MLX5_FLOW_CONTEXT_ACTION_MOD_HDR   = 0x40,
2258 };
2259 
2260 struct mlx5_ifc_flow_context_bits {
2261 	u8         reserved_at_0[0x20];
2262 
2263 	u8         group_id[0x20];
2264 
2265 	u8         reserved_at_40[0x8];
2266 	u8         flow_tag[0x18];
2267 
2268 	u8         reserved_at_60[0x10];
2269 	u8         action[0x10];
2270 
2271 	u8         reserved_at_80[0x8];
2272 	u8         destination_list_size[0x18];
2273 
2274 	u8         reserved_at_a0[0x8];
2275 	u8         flow_counter_list_size[0x18];
2276 
2277 	u8         encap_id[0x20];
2278 
2279 	u8         modify_header_id[0x20];
2280 
2281 	u8         reserved_at_100[0x100];
2282 
2283 	struct mlx5_ifc_fte_match_param_bits match_value;
2284 
2285 	u8         reserved_at_1200[0x600];
2286 
2287 	union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2288 };
2289 
2290 enum {
2291 	MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
2292 	MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
2293 };
2294 
2295 struct mlx5_ifc_xrc_srqc_bits {
2296 	u8         state[0x4];
2297 	u8         log_xrc_srq_size[0x4];
2298 	u8         reserved_at_8[0x18];
2299 
2300 	u8         wq_signature[0x1];
2301 	u8         cont_srq[0x1];
2302 	u8         reserved_at_22[0x1];
2303 	u8         rlky[0x1];
2304 	u8         basic_cyclic_rcv_wqe[0x1];
2305 	u8         log_rq_stride[0x3];
2306 	u8         xrcd[0x18];
2307 
2308 	u8         page_offset[0x6];
2309 	u8         reserved_at_46[0x2];
2310 	u8         cqn[0x18];
2311 
2312 	u8         reserved_at_60[0x20];
2313 
2314 	u8         user_index_equal_xrc_srqn[0x1];
2315 	u8         reserved_at_81[0x1];
2316 	u8         log_page_size[0x6];
2317 	u8         user_index[0x18];
2318 
2319 	u8         reserved_at_a0[0x20];
2320 
2321 	u8         reserved_at_c0[0x8];
2322 	u8         pd[0x18];
2323 
2324 	u8         lwm[0x10];
2325 	u8         wqe_cnt[0x10];
2326 
2327 	u8         reserved_at_100[0x40];
2328 
2329 	u8         db_record_addr_h[0x20];
2330 
2331 	u8         db_record_addr_l[0x1e];
2332 	u8         reserved_at_17e[0x2];
2333 
2334 	u8         reserved_at_180[0x80];
2335 };
2336 
2337 struct mlx5_ifc_traffic_counter_bits {
2338 	u8         packets[0x40];
2339 
2340 	u8         octets[0x40];
2341 };
2342 
2343 struct mlx5_ifc_tisc_bits {
2344 	u8         strict_lag_tx_port_affinity[0x1];
2345 	u8         reserved_at_1[0x3];
2346 	u8         lag_tx_port_affinity[0x04];
2347 
2348 	u8         reserved_at_8[0x4];
2349 	u8         prio[0x4];
2350 	u8         reserved_at_10[0x10];
2351 
2352 	u8         reserved_at_20[0x100];
2353 
2354 	u8         reserved_at_120[0x8];
2355 	u8         transport_domain[0x18];
2356 
2357 	u8         reserved_at_140[0x8];
2358 	u8         underlay_qpn[0x18];
2359 	u8         reserved_at_160[0x3a0];
2360 };
2361 
2362 enum {
2363 	MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
2364 	MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
2365 };
2366 
2367 enum {
2368 	MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
2369 	MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
2370 };
2371 
2372 enum {
2373 	MLX5_RX_HASH_FN_NONE           = 0x0,
2374 	MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
2375 	MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
2376 };
2377 
2378 enum {
2379 	MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_    = 0x1,
2380 	MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_  = 0x2,
2381 };
2382 
2383 struct mlx5_ifc_tirc_bits {
2384 	u8         reserved_at_0[0x20];
2385 
2386 	u8         disp_type[0x4];
2387 	u8         reserved_at_24[0x1c];
2388 
2389 	u8         reserved_at_40[0x40];
2390 
2391 	u8         reserved_at_80[0x4];
2392 	u8         lro_timeout_period_usecs[0x10];
2393 	u8         lro_enable_mask[0x4];
2394 	u8         lro_max_ip_payload_size[0x8];
2395 
2396 	u8         reserved_at_a0[0x40];
2397 
2398 	u8         reserved_at_e0[0x8];
2399 	u8         inline_rqn[0x18];
2400 
2401 	u8         rx_hash_symmetric[0x1];
2402 	u8         reserved_at_101[0x1];
2403 	u8         tunneled_offload_en[0x1];
2404 	u8         reserved_at_103[0x5];
2405 	u8         indirect_table[0x18];
2406 
2407 	u8         rx_hash_fn[0x4];
2408 	u8         reserved_at_124[0x2];
2409 	u8         self_lb_block[0x2];
2410 	u8         transport_domain[0x18];
2411 
2412 	u8         rx_hash_toeplitz_key[10][0x20];
2413 
2414 	struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2415 
2416 	struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2417 
2418 	u8         reserved_at_2c0[0x4c0];
2419 };
2420 
2421 enum {
2422 	MLX5_SRQC_STATE_GOOD   = 0x0,
2423 	MLX5_SRQC_STATE_ERROR  = 0x1,
2424 };
2425 
2426 struct mlx5_ifc_srqc_bits {
2427 	u8         state[0x4];
2428 	u8         log_srq_size[0x4];
2429 	u8         reserved_at_8[0x18];
2430 
2431 	u8         wq_signature[0x1];
2432 	u8         cont_srq[0x1];
2433 	u8         reserved_at_22[0x1];
2434 	u8         rlky[0x1];
2435 	u8         reserved_at_24[0x1];
2436 	u8         log_rq_stride[0x3];
2437 	u8         xrcd[0x18];
2438 
2439 	u8         page_offset[0x6];
2440 	u8         reserved_at_46[0x2];
2441 	u8         cqn[0x18];
2442 
2443 	u8         reserved_at_60[0x20];
2444 
2445 	u8         reserved_at_80[0x2];
2446 	u8         log_page_size[0x6];
2447 	u8         reserved_at_88[0x18];
2448 
2449 	u8         reserved_at_a0[0x20];
2450 
2451 	u8         reserved_at_c0[0x8];
2452 	u8         pd[0x18];
2453 
2454 	u8         lwm[0x10];
2455 	u8         wqe_cnt[0x10];
2456 
2457 	u8         reserved_at_100[0x40];
2458 
2459 	u8         dbr_addr[0x40];
2460 
2461 	u8         reserved_at_180[0x80];
2462 };
2463 
2464 enum {
2465 	MLX5_SQC_STATE_RST  = 0x0,
2466 	MLX5_SQC_STATE_RDY  = 0x1,
2467 	MLX5_SQC_STATE_ERR  = 0x3,
2468 };
2469 
2470 struct mlx5_ifc_sqc_bits {
2471 	u8         rlky[0x1];
2472 	u8         cd_master[0x1];
2473 	u8         fre[0x1];
2474 	u8         flush_in_error_en[0x1];
2475 	u8         allow_multi_pkt_send_wqe[0x1];
2476 	u8	   min_wqe_inline_mode[0x3];
2477 	u8         state[0x4];
2478 	u8         reg_umr[0x1];
2479 	u8         allow_swp[0x1];
2480 	u8         reserved_at_e[0x12];
2481 
2482 	u8         reserved_at_20[0x8];
2483 	u8         user_index[0x18];
2484 
2485 	u8         reserved_at_40[0x8];
2486 	u8         cqn[0x18];
2487 
2488 	u8         reserved_at_60[0x90];
2489 
2490 	u8         packet_pacing_rate_limit_index[0x10];
2491 	u8         tis_lst_sz[0x10];
2492 	u8         reserved_at_110[0x10];
2493 
2494 	u8         reserved_at_120[0x40];
2495 
2496 	u8         reserved_at_160[0x8];
2497 	u8         tis_num_0[0x18];
2498 
2499 	struct mlx5_ifc_wq_bits wq;
2500 };
2501 
2502 enum {
2503 	SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2504 	SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2505 	SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2506 	SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2507 };
2508 
2509 struct mlx5_ifc_scheduling_context_bits {
2510 	u8         element_type[0x8];
2511 	u8         reserved_at_8[0x18];
2512 
2513 	u8         element_attributes[0x20];
2514 
2515 	u8         parent_element_id[0x20];
2516 
2517 	u8         reserved_at_60[0x40];
2518 
2519 	u8         bw_share[0x20];
2520 
2521 	u8         max_average_bw[0x20];
2522 
2523 	u8         reserved_at_e0[0x120];
2524 };
2525 
2526 struct mlx5_ifc_rqtc_bits {
2527 	u8         reserved_at_0[0xa0];
2528 
2529 	u8         reserved_at_a0[0x10];
2530 	u8         rqt_max_size[0x10];
2531 
2532 	u8         reserved_at_c0[0x10];
2533 	u8         rqt_actual_size[0x10];
2534 
2535 	u8         reserved_at_e0[0x6a0];
2536 
2537 	struct mlx5_ifc_rq_num_bits rq_num[0];
2538 };
2539 
2540 enum {
2541 	MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
2542 	MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
2543 };
2544 
2545 enum {
2546 	MLX5_RQC_STATE_RST  = 0x0,
2547 	MLX5_RQC_STATE_RDY  = 0x1,
2548 	MLX5_RQC_STATE_ERR  = 0x3,
2549 };
2550 
2551 struct mlx5_ifc_rqc_bits {
2552 	u8         rlky[0x1];
2553 	u8	   delay_drop_en[0x1];
2554 	u8         scatter_fcs[0x1];
2555 	u8         vsd[0x1];
2556 	u8         mem_rq_type[0x4];
2557 	u8         state[0x4];
2558 	u8         reserved_at_c[0x1];
2559 	u8         flush_in_error_en[0x1];
2560 	u8         reserved_at_e[0x12];
2561 
2562 	u8         reserved_at_20[0x8];
2563 	u8         user_index[0x18];
2564 
2565 	u8         reserved_at_40[0x8];
2566 	u8         cqn[0x18];
2567 
2568 	u8         counter_set_id[0x8];
2569 	u8         reserved_at_68[0x18];
2570 
2571 	u8         reserved_at_80[0x8];
2572 	u8         rmpn[0x18];
2573 
2574 	u8         reserved_at_a0[0xe0];
2575 
2576 	struct mlx5_ifc_wq_bits wq;
2577 };
2578 
2579 enum {
2580 	MLX5_RMPC_STATE_RDY  = 0x1,
2581 	MLX5_RMPC_STATE_ERR  = 0x3,
2582 };
2583 
2584 struct mlx5_ifc_rmpc_bits {
2585 	u8         reserved_at_0[0x8];
2586 	u8         state[0x4];
2587 	u8         reserved_at_c[0x14];
2588 
2589 	u8         basic_cyclic_rcv_wqe[0x1];
2590 	u8         reserved_at_21[0x1f];
2591 
2592 	u8         reserved_at_40[0x140];
2593 
2594 	struct mlx5_ifc_wq_bits wq;
2595 };
2596 
2597 struct mlx5_ifc_nic_vport_context_bits {
2598 	u8         reserved_at_0[0x5];
2599 	u8         min_wqe_inline_mode[0x3];
2600 	u8         reserved_at_8[0x15];
2601 	u8         disable_mc_local_lb[0x1];
2602 	u8         disable_uc_local_lb[0x1];
2603 	u8         roce_en[0x1];
2604 
2605 	u8         arm_change_event[0x1];
2606 	u8         reserved_at_21[0x1a];
2607 	u8         event_on_mtu[0x1];
2608 	u8         event_on_promisc_change[0x1];
2609 	u8         event_on_vlan_change[0x1];
2610 	u8         event_on_mc_address_change[0x1];
2611 	u8         event_on_uc_address_change[0x1];
2612 
2613 	u8         reserved_at_40[0xf0];
2614 
2615 	u8         mtu[0x10];
2616 
2617 	u8         system_image_guid[0x40];
2618 	u8         port_guid[0x40];
2619 	u8         node_guid[0x40];
2620 
2621 	u8         reserved_at_200[0x140];
2622 	u8         qkey_violation_counter[0x10];
2623 	u8         reserved_at_350[0x430];
2624 
2625 	u8         promisc_uc[0x1];
2626 	u8         promisc_mc[0x1];
2627 	u8         promisc_all[0x1];
2628 	u8         reserved_at_783[0x2];
2629 	u8         allowed_list_type[0x3];
2630 	u8         reserved_at_788[0xc];
2631 	u8         allowed_list_size[0xc];
2632 
2633 	struct mlx5_ifc_mac_address_layout_bits permanent_address;
2634 
2635 	u8         reserved_at_7e0[0x20];
2636 
2637 	u8         current_uc_mac_address[0][0x40];
2638 };
2639 
2640 enum {
2641 	MLX5_MKC_ACCESS_MODE_PA    = 0x0,
2642 	MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
2643 	MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
2644 	MLX5_MKC_ACCESS_MODE_KSM   = 0x3,
2645 };
2646 
2647 struct mlx5_ifc_mkc_bits {
2648 	u8         reserved_at_0[0x1];
2649 	u8         free[0x1];
2650 	u8         reserved_at_2[0xd];
2651 	u8         small_fence_on_rdma_read_response[0x1];
2652 	u8         umr_en[0x1];
2653 	u8         a[0x1];
2654 	u8         rw[0x1];
2655 	u8         rr[0x1];
2656 	u8         lw[0x1];
2657 	u8         lr[0x1];
2658 	u8         access_mode[0x2];
2659 	u8         reserved_at_18[0x8];
2660 
2661 	u8         qpn[0x18];
2662 	u8         mkey_7_0[0x8];
2663 
2664 	u8         reserved_at_40[0x20];
2665 
2666 	u8         length64[0x1];
2667 	u8         bsf_en[0x1];
2668 	u8         sync_umr[0x1];
2669 	u8         reserved_at_63[0x2];
2670 	u8         expected_sigerr_count[0x1];
2671 	u8         reserved_at_66[0x1];
2672 	u8         en_rinval[0x1];
2673 	u8         pd[0x18];
2674 
2675 	u8         start_addr[0x40];
2676 
2677 	u8         len[0x40];
2678 
2679 	u8         bsf_octword_size[0x20];
2680 
2681 	u8         reserved_at_120[0x80];
2682 
2683 	u8         translations_octword_size[0x20];
2684 
2685 	u8         reserved_at_1c0[0x1b];
2686 	u8         log_page_size[0x5];
2687 
2688 	u8         reserved_at_1e0[0x20];
2689 };
2690 
2691 struct mlx5_ifc_pkey_bits {
2692 	u8         reserved_at_0[0x10];
2693 	u8         pkey[0x10];
2694 };
2695 
2696 struct mlx5_ifc_array128_auto_bits {
2697 	u8         array128_auto[16][0x8];
2698 };
2699 
2700 struct mlx5_ifc_hca_vport_context_bits {
2701 	u8         field_select[0x20];
2702 
2703 	u8         reserved_at_20[0xe0];
2704 
2705 	u8         sm_virt_aware[0x1];
2706 	u8         has_smi[0x1];
2707 	u8         has_raw[0x1];
2708 	u8         grh_required[0x1];
2709 	u8         reserved_at_104[0xc];
2710 	u8         port_physical_state[0x4];
2711 	u8         vport_state_policy[0x4];
2712 	u8         port_state[0x4];
2713 	u8         vport_state[0x4];
2714 
2715 	u8         reserved_at_120[0x20];
2716 
2717 	u8         system_image_guid[0x40];
2718 
2719 	u8         port_guid[0x40];
2720 
2721 	u8         node_guid[0x40];
2722 
2723 	u8         cap_mask1[0x20];
2724 
2725 	u8         cap_mask1_field_select[0x20];
2726 
2727 	u8         cap_mask2[0x20];
2728 
2729 	u8         cap_mask2_field_select[0x20];
2730 
2731 	u8         reserved_at_280[0x80];
2732 
2733 	u8         lid[0x10];
2734 	u8         reserved_at_310[0x4];
2735 	u8         init_type_reply[0x4];
2736 	u8         lmc[0x3];
2737 	u8         subnet_timeout[0x5];
2738 
2739 	u8         sm_lid[0x10];
2740 	u8         sm_sl[0x4];
2741 	u8         reserved_at_334[0xc];
2742 
2743 	u8         qkey_violation_counter[0x10];
2744 	u8         pkey_violation_counter[0x10];
2745 
2746 	u8         reserved_at_360[0xca0];
2747 };
2748 
2749 struct mlx5_ifc_esw_vport_context_bits {
2750 	u8         reserved_at_0[0x3];
2751 	u8         vport_svlan_strip[0x1];
2752 	u8         vport_cvlan_strip[0x1];
2753 	u8         vport_svlan_insert[0x1];
2754 	u8         vport_cvlan_insert[0x2];
2755 	u8         reserved_at_8[0x18];
2756 
2757 	u8         reserved_at_20[0x20];
2758 
2759 	u8         svlan_cfi[0x1];
2760 	u8         svlan_pcp[0x3];
2761 	u8         svlan_id[0xc];
2762 	u8         cvlan_cfi[0x1];
2763 	u8         cvlan_pcp[0x3];
2764 	u8         cvlan_id[0xc];
2765 
2766 	u8         reserved_at_60[0x7a0];
2767 };
2768 
2769 enum {
2770 	MLX5_EQC_STATUS_OK                = 0x0,
2771 	MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
2772 };
2773 
2774 enum {
2775 	MLX5_EQC_ST_ARMED  = 0x9,
2776 	MLX5_EQC_ST_FIRED  = 0xa,
2777 };
2778 
2779 struct mlx5_ifc_eqc_bits {
2780 	u8         status[0x4];
2781 	u8         reserved_at_4[0x9];
2782 	u8         ec[0x1];
2783 	u8         oi[0x1];
2784 	u8         reserved_at_f[0x5];
2785 	u8         st[0x4];
2786 	u8         reserved_at_18[0x8];
2787 
2788 	u8         reserved_at_20[0x20];
2789 
2790 	u8         reserved_at_40[0x14];
2791 	u8         page_offset[0x6];
2792 	u8         reserved_at_5a[0x6];
2793 
2794 	u8         reserved_at_60[0x3];
2795 	u8         log_eq_size[0x5];
2796 	u8         uar_page[0x18];
2797 
2798 	u8         reserved_at_80[0x20];
2799 
2800 	u8         reserved_at_a0[0x18];
2801 	u8         intr[0x8];
2802 
2803 	u8         reserved_at_c0[0x3];
2804 	u8         log_page_size[0x5];
2805 	u8         reserved_at_c8[0x18];
2806 
2807 	u8         reserved_at_e0[0x60];
2808 
2809 	u8         reserved_at_140[0x8];
2810 	u8         consumer_counter[0x18];
2811 
2812 	u8         reserved_at_160[0x8];
2813 	u8         producer_counter[0x18];
2814 
2815 	u8         reserved_at_180[0x80];
2816 };
2817 
2818 enum {
2819 	MLX5_DCTC_STATE_ACTIVE    = 0x0,
2820 	MLX5_DCTC_STATE_DRAINING  = 0x1,
2821 	MLX5_DCTC_STATE_DRAINED   = 0x2,
2822 };
2823 
2824 enum {
2825 	MLX5_DCTC_CS_RES_DISABLE    = 0x0,
2826 	MLX5_DCTC_CS_RES_NA         = 0x1,
2827 	MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
2828 };
2829 
2830 enum {
2831 	MLX5_DCTC_MTU_256_BYTES  = 0x1,
2832 	MLX5_DCTC_MTU_512_BYTES  = 0x2,
2833 	MLX5_DCTC_MTU_1K_BYTES   = 0x3,
2834 	MLX5_DCTC_MTU_2K_BYTES   = 0x4,
2835 	MLX5_DCTC_MTU_4K_BYTES   = 0x5,
2836 };
2837 
2838 struct mlx5_ifc_dctc_bits {
2839 	u8         reserved_at_0[0x4];
2840 	u8         state[0x4];
2841 	u8         reserved_at_8[0x18];
2842 
2843 	u8         reserved_at_20[0x8];
2844 	u8         user_index[0x18];
2845 
2846 	u8         reserved_at_40[0x8];
2847 	u8         cqn[0x18];
2848 
2849 	u8         counter_set_id[0x8];
2850 	u8         atomic_mode[0x4];
2851 	u8         rre[0x1];
2852 	u8         rwe[0x1];
2853 	u8         rae[0x1];
2854 	u8         atomic_like_write_en[0x1];
2855 	u8         latency_sensitive[0x1];
2856 	u8         rlky[0x1];
2857 	u8         free_ar[0x1];
2858 	u8         reserved_at_73[0xd];
2859 
2860 	u8         reserved_at_80[0x8];
2861 	u8         cs_res[0x8];
2862 	u8         reserved_at_90[0x3];
2863 	u8         min_rnr_nak[0x5];
2864 	u8         reserved_at_98[0x8];
2865 
2866 	u8         reserved_at_a0[0x8];
2867 	u8         srqn_xrqn[0x18];
2868 
2869 	u8         reserved_at_c0[0x8];
2870 	u8         pd[0x18];
2871 
2872 	u8         tclass[0x8];
2873 	u8         reserved_at_e8[0x4];
2874 	u8         flow_label[0x14];
2875 
2876 	u8         dc_access_key[0x40];
2877 
2878 	u8         reserved_at_140[0x5];
2879 	u8         mtu[0x3];
2880 	u8         port[0x8];
2881 	u8         pkey_index[0x10];
2882 
2883 	u8         reserved_at_160[0x8];
2884 	u8         my_addr_index[0x8];
2885 	u8         reserved_at_170[0x8];
2886 	u8         hop_limit[0x8];
2887 
2888 	u8         dc_access_key_violation_count[0x20];
2889 
2890 	u8         reserved_at_1a0[0x14];
2891 	u8         dei_cfi[0x1];
2892 	u8         eth_prio[0x3];
2893 	u8         ecn[0x2];
2894 	u8         dscp[0x6];
2895 
2896 	u8         reserved_at_1c0[0x40];
2897 };
2898 
2899 enum {
2900 	MLX5_CQC_STATUS_OK             = 0x0,
2901 	MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
2902 	MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
2903 };
2904 
2905 enum {
2906 	MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
2907 	MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
2908 };
2909 
2910 enum {
2911 	MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
2912 	MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
2913 	MLX5_CQC_ST_FIRED                                 = 0xa,
2914 };
2915 
2916 enum {
2917 	MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
2918 	MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
2919 	MLX5_CQ_PERIOD_NUM_MODES
2920 };
2921 
2922 struct mlx5_ifc_cqc_bits {
2923 	u8         status[0x4];
2924 	u8         reserved_at_4[0x4];
2925 	u8         cqe_sz[0x3];
2926 	u8         cc[0x1];
2927 	u8         reserved_at_c[0x1];
2928 	u8         scqe_break_moderation_en[0x1];
2929 	u8         oi[0x1];
2930 	u8         cq_period_mode[0x2];
2931 	u8         cqe_comp_en[0x1];
2932 	u8         mini_cqe_res_format[0x2];
2933 	u8         st[0x4];
2934 	u8         reserved_at_18[0x8];
2935 
2936 	u8         reserved_at_20[0x20];
2937 
2938 	u8         reserved_at_40[0x14];
2939 	u8         page_offset[0x6];
2940 	u8         reserved_at_5a[0x6];
2941 
2942 	u8         reserved_at_60[0x3];
2943 	u8         log_cq_size[0x5];
2944 	u8         uar_page[0x18];
2945 
2946 	u8         reserved_at_80[0x4];
2947 	u8         cq_period[0xc];
2948 	u8         cq_max_count[0x10];
2949 
2950 	u8         reserved_at_a0[0x18];
2951 	u8         c_eqn[0x8];
2952 
2953 	u8         reserved_at_c0[0x3];
2954 	u8         log_page_size[0x5];
2955 	u8         reserved_at_c8[0x18];
2956 
2957 	u8         reserved_at_e0[0x20];
2958 
2959 	u8         reserved_at_100[0x8];
2960 	u8         last_notified_index[0x18];
2961 
2962 	u8         reserved_at_120[0x8];
2963 	u8         last_solicit_index[0x18];
2964 
2965 	u8         reserved_at_140[0x8];
2966 	u8         consumer_counter[0x18];
2967 
2968 	u8         reserved_at_160[0x8];
2969 	u8         producer_counter[0x18];
2970 
2971 	u8         reserved_at_180[0x40];
2972 
2973 	u8         dbr_addr[0x40];
2974 };
2975 
2976 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2977 	struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2978 	struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2979 	struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
2980 	u8         reserved_at_0[0x800];
2981 };
2982 
2983 struct mlx5_ifc_query_adapter_param_block_bits {
2984 	u8         reserved_at_0[0xc0];
2985 
2986 	u8         reserved_at_c0[0x8];
2987 	u8         ieee_vendor_id[0x18];
2988 
2989 	u8         reserved_at_e0[0x10];
2990 	u8         vsd_vendor_id[0x10];
2991 
2992 	u8         vsd[208][0x8];
2993 
2994 	u8         vsd_contd_psid[16][0x8];
2995 };
2996 
2997 enum {
2998 	MLX5_XRQC_STATE_GOOD   = 0x0,
2999 	MLX5_XRQC_STATE_ERROR  = 0x1,
3000 };
3001 
3002 enum {
3003 	MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3004 	MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
3005 };
3006 
3007 enum {
3008 	MLX5_XRQC_OFFLOAD_RNDV = 0x1,
3009 };
3010 
3011 struct mlx5_ifc_tag_matching_topology_context_bits {
3012 	u8         log_matching_list_sz[0x4];
3013 	u8         reserved_at_4[0xc];
3014 	u8         append_next_index[0x10];
3015 
3016 	u8         sw_phase_cnt[0x10];
3017 	u8         hw_phase_cnt[0x10];
3018 
3019 	u8         reserved_at_40[0x40];
3020 };
3021 
3022 struct mlx5_ifc_xrqc_bits {
3023 	u8         state[0x4];
3024 	u8         rlkey[0x1];
3025 	u8         reserved_at_5[0xf];
3026 	u8         topology[0x4];
3027 	u8         reserved_at_18[0x4];
3028 	u8         offload[0x4];
3029 
3030 	u8         reserved_at_20[0x8];
3031 	u8         user_index[0x18];
3032 
3033 	u8         reserved_at_40[0x8];
3034 	u8         cqn[0x18];
3035 
3036 	u8         reserved_at_60[0xa0];
3037 
3038 	struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3039 
3040 	u8         reserved_at_180[0x280];
3041 
3042 	struct mlx5_ifc_wq_bits wq;
3043 };
3044 
3045 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3046 	struct mlx5_ifc_modify_field_select_bits modify_field_select;
3047 	struct mlx5_ifc_resize_field_select_bits resize_field_select;
3048 	u8         reserved_at_0[0x20];
3049 };
3050 
3051 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3052 	struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3053 	struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3054 	struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
3055 	u8         reserved_at_0[0x20];
3056 };
3057 
3058 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3059 	struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3060 	struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3061 	struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3062 	struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3063 	struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3064 	struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3065 	struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
3066 	struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
3067 	struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
3068 	struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
3069 	u8         reserved_at_0[0x7c0];
3070 };
3071 
3072 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3073 	struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3074 	u8         reserved_at_0[0x7c0];
3075 };
3076 
3077 union mlx5_ifc_event_auto_bits {
3078 	struct mlx5_ifc_comp_event_bits comp_event;
3079 	struct mlx5_ifc_dct_events_bits dct_events;
3080 	struct mlx5_ifc_qp_events_bits qp_events;
3081 	struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3082 	struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3083 	struct mlx5_ifc_cq_error_bits cq_error;
3084 	struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3085 	struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3086 	struct mlx5_ifc_gpio_event_bits gpio_event;
3087 	struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3088 	struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3089 	struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3090 	u8         reserved_at_0[0xe0];
3091 };
3092 
3093 struct mlx5_ifc_health_buffer_bits {
3094 	u8         reserved_at_0[0x100];
3095 
3096 	u8         assert_existptr[0x20];
3097 
3098 	u8         assert_callra[0x20];
3099 
3100 	u8         reserved_at_140[0x40];
3101 
3102 	u8         fw_version[0x20];
3103 
3104 	u8         hw_id[0x20];
3105 
3106 	u8         reserved_at_1c0[0x20];
3107 
3108 	u8         irisc_index[0x8];
3109 	u8         synd[0x8];
3110 	u8         ext_synd[0x10];
3111 };
3112 
3113 struct mlx5_ifc_register_loopback_control_bits {
3114 	u8         no_lb[0x1];
3115 	u8         reserved_at_1[0x7];
3116 	u8         port[0x8];
3117 	u8         reserved_at_10[0x10];
3118 
3119 	u8         reserved_at_20[0x60];
3120 };
3121 
3122 struct mlx5_ifc_vport_tc_element_bits {
3123 	u8         traffic_class[0x4];
3124 	u8         reserved_at_4[0xc];
3125 	u8         vport_number[0x10];
3126 };
3127 
3128 struct mlx5_ifc_vport_element_bits {
3129 	u8         reserved_at_0[0x10];
3130 	u8         vport_number[0x10];
3131 };
3132 
3133 enum {
3134 	TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3135 	TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3136 	TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3137 };
3138 
3139 struct mlx5_ifc_tsar_element_bits {
3140 	u8         reserved_at_0[0x8];
3141 	u8         tsar_type[0x8];
3142 	u8         reserved_at_10[0x10];
3143 };
3144 
3145 enum {
3146 	MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3147 	MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3148 };
3149 
3150 struct mlx5_ifc_teardown_hca_out_bits {
3151 	u8         status[0x8];
3152 	u8         reserved_at_8[0x18];
3153 
3154 	u8         syndrome[0x20];
3155 
3156 	u8         reserved_at_40[0x3f];
3157 
3158 	u8         force_state[0x1];
3159 };
3160 
3161 enum {
3162 	MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
3163 	MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE     = 0x1,
3164 };
3165 
3166 struct mlx5_ifc_teardown_hca_in_bits {
3167 	u8         opcode[0x10];
3168 	u8         reserved_at_10[0x10];
3169 
3170 	u8         reserved_at_20[0x10];
3171 	u8         op_mod[0x10];
3172 
3173 	u8         reserved_at_40[0x10];
3174 	u8         profile[0x10];
3175 
3176 	u8         reserved_at_60[0x20];
3177 };
3178 
3179 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3180 	u8         status[0x8];
3181 	u8         reserved_at_8[0x18];
3182 
3183 	u8         syndrome[0x20];
3184 
3185 	u8         reserved_at_40[0x40];
3186 };
3187 
3188 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3189 	u8         opcode[0x10];
3190 	u8         reserved_at_10[0x10];
3191 
3192 	u8         reserved_at_20[0x10];
3193 	u8         op_mod[0x10];
3194 
3195 	u8         reserved_at_40[0x8];
3196 	u8         qpn[0x18];
3197 
3198 	u8         reserved_at_60[0x20];
3199 
3200 	u8         opt_param_mask[0x20];
3201 
3202 	u8         reserved_at_a0[0x20];
3203 
3204 	struct mlx5_ifc_qpc_bits qpc;
3205 
3206 	u8         reserved_at_800[0x80];
3207 };
3208 
3209 struct mlx5_ifc_sqd2rts_qp_out_bits {
3210 	u8         status[0x8];
3211 	u8         reserved_at_8[0x18];
3212 
3213 	u8         syndrome[0x20];
3214 
3215 	u8         reserved_at_40[0x40];
3216 };
3217 
3218 struct mlx5_ifc_sqd2rts_qp_in_bits {
3219 	u8         opcode[0x10];
3220 	u8         reserved_at_10[0x10];
3221 
3222 	u8         reserved_at_20[0x10];
3223 	u8         op_mod[0x10];
3224 
3225 	u8         reserved_at_40[0x8];
3226 	u8         qpn[0x18];
3227 
3228 	u8         reserved_at_60[0x20];
3229 
3230 	u8         opt_param_mask[0x20];
3231 
3232 	u8         reserved_at_a0[0x20];
3233 
3234 	struct mlx5_ifc_qpc_bits qpc;
3235 
3236 	u8         reserved_at_800[0x80];
3237 };
3238 
3239 struct mlx5_ifc_set_roce_address_out_bits {
3240 	u8         status[0x8];
3241 	u8         reserved_at_8[0x18];
3242 
3243 	u8         syndrome[0x20];
3244 
3245 	u8         reserved_at_40[0x40];
3246 };
3247 
3248 struct mlx5_ifc_set_roce_address_in_bits {
3249 	u8         opcode[0x10];
3250 	u8         reserved_at_10[0x10];
3251 
3252 	u8         reserved_at_20[0x10];
3253 	u8         op_mod[0x10];
3254 
3255 	u8         roce_address_index[0x10];
3256 	u8         reserved_at_50[0x10];
3257 
3258 	u8         reserved_at_60[0x20];
3259 
3260 	struct mlx5_ifc_roce_addr_layout_bits roce_address;
3261 };
3262 
3263 struct mlx5_ifc_set_mad_demux_out_bits {
3264 	u8         status[0x8];
3265 	u8         reserved_at_8[0x18];
3266 
3267 	u8         syndrome[0x20];
3268 
3269 	u8         reserved_at_40[0x40];
3270 };
3271 
3272 enum {
3273 	MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
3274 	MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
3275 };
3276 
3277 struct mlx5_ifc_set_mad_demux_in_bits {
3278 	u8         opcode[0x10];
3279 	u8         reserved_at_10[0x10];
3280 
3281 	u8         reserved_at_20[0x10];
3282 	u8         op_mod[0x10];
3283 
3284 	u8         reserved_at_40[0x20];
3285 
3286 	u8         reserved_at_60[0x6];
3287 	u8         demux_mode[0x2];
3288 	u8         reserved_at_68[0x18];
3289 };
3290 
3291 struct mlx5_ifc_set_l2_table_entry_out_bits {
3292 	u8         status[0x8];
3293 	u8         reserved_at_8[0x18];
3294 
3295 	u8         syndrome[0x20];
3296 
3297 	u8         reserved_at_40[0x40];
3298 };
3299 
3300 struct mlx5_ifc_set_l2_table_entry_in_bits {
3301 	u8         opcode[0x10];
3302 	u8         reserved_at_10[0x10];
3303 
3304 	u8         reserved_at_20[0x10];
3305 	u8         op_mod[0x10];
3306 
3307 	u8         reserved_at_40[0x60];
3308 
3309 	u8         reserved_at_a0[0x8];
3310 	u8         table_index[0x18];
3311 
3312 	u8         reserved_at_c0[0x20];
3313 
3314 	u8         reserved_at_e0[0x13];
3315 	u8         vlan_valid[0x1];
3316 	u8         vlan[0xc];
3317 
3318 	struct mlx5_ifc_mac_address_layout_bits mac_address;
3319 
3320 	u8         reserved_at_140[0xc0];
3321 };
3322 
3323 struct mlx5_ifc_set_issi_out_bits {
3324 	u8         status[0x8];
3325 	u8         reserved_at_8[0x18];
3326 
3327 	u8         syndrome[0x20];
3328 
3329 	u8         reserved_at_40[0x40];
3330 };
3331 
3332 struct mlx5_ifc_set_issi_in_bits {
3333 	u8         opcode[0x10];
3334 	u8         reserved_at_10[0x10];
3335 
3336 	u8         reserved_at_20[0x10];
3337 	u8         op_mod[0x10];
3338 
3339 	u8         reserved_at_40[0x10];
3340 	u8         current_issi[0x10];
3341 
3342 	u8         reserved_at_60[0x20];
3343 };
3344 
3345 struct mlx5_ifc_set_hca_cap_out_bits {
3346 	u8         status[0x8];
3347 	u8         reserved_at_8[0x18];
3348 
3349 	u8         syndrome[0x20];
3350 
3351 	u8         reserved_at_40[0x40];
3352 };
3353 
3354 struct mlx5_ifc_set_hca_cap_in_bits {
3355 	u8         opcode[0x10];
3356 	u8         reserved_at_10[0x10];
3357 
3358 	u8         reserved_at_20[0x10];
3359 	u8         op_mod[0x10];
3360 
3361 	u8         reserved_at_40[0x40];
3362 
3363 	union mlx5_ifc_hca_cap_union_bits capability;
3364 };
3365 
3366 enum {
3367 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
3368 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
3369 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
3370 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3
3371 };
3372 
3373 struct mlx5_ifc_set_fte_out_bits {
3374 	u8         status[0x8];
3375 	u8         reserved_at_8[0x18];
3376 
3377 	u8         syndrome[0x20];
3378 
3379 	u8         reserved_at_40[0x40];
3380 };
3381 
3382 struct mlx5_ifc_set_fte_in_bits {
3383 	u8         opcode[0x10];
3384 	u8         reserved_at_10[0x10];
3385 
3386 	u8         reserved_at_20[0x10];
3387 	u8         op_mod[0x10];
3388 
3389 	u8         other_vport[0x1];
3390 	u8         reserved_at_41[0xf];
3391 	u8         vport_number[0x10];
3392 
3393 	u8         reserved_at_60[0x20];
3394 
3395 	u8         table_type[0x8];
3396 	u8         reserved_at_88[0x18];
3397 
3398 	u8         reserved_at_a0[0x8];
3399 	u8         table_id[0x18];
3400 
3401 	u8         reserved_at_c0[0x18];
3402 	u8         modify_enable_mask[0x8];
3403 
3404 	u8         reserved_at_e0[0x20];
3405 
3406 	u8         flow_index[0x20];
3407 
3408 	u8         reserved_at_120[0xe0];
3409 
3410 	struct mlx5_ifc_flow_context_bits flow_context;
3411 };
3412 
3413 struct mlx5_ifc_rts2rts_qp_out_bits {
3414 	u8         status[0x8];
3415 	u8         reserved_at_8[0x18];
3416 
3417 	u8         syndrome[0x20];
3418 
3419 	u8         reserved_at_40[0x40];
3420 };
3421 
3422 struct mlx5_ifc_rts2rts_qp_in_bits {
3423 	u8         opcode[0x10];
3424 	u8         reserved_at_10[0x10];
3425 
3426 	u8         reserved_at_20[0x10];
3427 	u8         op_mod[0x10];
3428 
3429 	u8         reserved_at_40[0x8];
3430 	u8         qpn[0x18];
3431 
3432 	u8         reserved_at_60[0x20];
3433 
3434 	u8         opt_param_mask[0x20];
3435 
3436 	u8         reserved_at_a0[0x20];
3437 
3438 	struct mlx5_ifc_qpc_bits qpc;
3439 
3440 	u8         reserved_at_800[0x80];
3441 };
3442 
3443 struct mlx5_ifc_rtr2rts_qp_out_bits {
3444 	u8         status[0x8];
3445 	u8         reserved_at_8[0x18];
3446 
3447 	u8         syndrome[0x20];
3448 
3449 	u8         reserved_at_40[0x40];
3450 };
3451 
3452 struct mlx5_ifc_rtr2rts_qp_in_bits {
3453 	u8         opcode[0x10];
3454 	u8         reserved_at_10[0x10];
3455 
3456 	u8         reserved_at_20[0x10];
3457 	u8         op_mod[0x10];
3458 
3459 	u8         reserved_at_40[0x8];
3460 	u8         qpn[0x18];
3461 
3462 	u8         reserved_at_60[0x20];
3463 
3464 	u8         opt_param_mask[0x20];
3465 
3466 	u8         reserved_at_a0[0x20];
3467 
3468 	struct mlx5_ifc_qpc_bits qpc;
3469 
3470 	u8         reserved_at_800[0x80];
3471 };
3472 
3473 struct mlx5_ifc_rst2init_qp_out_bits {
3474 	u8         status[0x8];
3475 	u8         reserved_at_8[0x18];
3476 
3477 	u8         syndrome[0x20];
3478 
3479 	u8         reserved_at_40[0x40];
3480 };
3481 
3482 struct mlx5_ifc_rst2init_qp_in_bits {
3483 	u8         opcode[0x10];
3484 	u8         reserved_at_10[0x10];
3485 
3486 	u8         reserved_at_20[0x10];
3487 	u8         op_mod[0x10];
3488 
3489 	u8         reserved_at_40[0x8];
3490 	u8         qpn[0x18];
3491 
3492 	u8         reserved_at_60[0x20];
3493 
3494 	u8         opt_param_mask[0x20];
3495 
3496 	u8         reserved_at_a0[0x20];
3497 
3498 	struct mlx5_ifc_qpc_bits qpc;
3499 
3500 	u8         reserved_at_800[0x80];
3501 };
3502 
3503 struct mlx5_ifc_query_xrq_out_bits {
3504 	u8         status[0x8];
3505 	u8         reserved_at_8[0x18];
3506 
3507 	u8         syndrome[0x20];
3508 
3509 	u8         reserved_at_40[0x40];
3510 
3511 	struct mlx5_ifc_xrqc_bits xrq_context;
3512 };
3513 
3514 struct mlx5_ifc_query_xrq_in_bits {
3515 	u8         opcode[0x10];
3516 	u8         reserved_at_10[0x10];
3517 
3518 	u8         reserved_at_20[0x10];
3519 	u8         op_mod[0x10];
3520 
3521 	u8         reserved_at_40[0x8];
3522 	u8         xrqn[0x18];
3523 
3524 	u8         reserved_at_60[0x20];
3525 };
3526 
3527 struct mlx5_ifc_query_xrc_srq_out_bits {
3528 	u8         status[0x8];
3529 	u8         reserved_at_8[0x18];
3530 
3531 	u8         syndrome[0x20];
3532 
3533 	u8         reserved_at_40[0x40];
3534 
3535 	struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3536 
3537 	u8         reserved_at_280[0x600];
3538 
3539 	u8         pas[0][0x40];
3540 };
3541 
3542 struct mlx5_ifc_query_xrc_srq_in_bits {
3543 	u8         opcode[0x10];
3544 	u8         reserved_at_10[0x10];
3545 
3546 	u8         reserved_at_20[0x10];
3547 	u8         op_mod[0x10];
3548 
3549 	u8         reserved_at_40[0x8];
3550 	u8         xrc_srqn[0x18];
3551 
3552 	u8         reserved_at_60[0x20];
3553 };
3554 
3555 enum {
3556 	MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
3557 	MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
3558 };
3559 
3560 struct mlx5_ifc_query_vport_state_out_bits {
3561 	u8         status[0x8];
3562 	u8         reserved_at_8[0x18];
3563 
3564 	u8         syndrome[0x20];
3565 
3566 	u8         reserved_at_40[0x20];
3567 
3568 	u8         reserved_at_60[0x18];
3569 	u8         admin_state[0x4];
3570 	u8         state[0x4];
3571 };
3572 
3573 enum {
3574 	MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT  = 0x0,
3575 	MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT   = 0x1,
3576 };
3577 
3578 struct mlx5_ifc_query_vport_state_in_bits {
3579 	u8         opcode[0x10];
3580 	u8         reserved_at_10[0x10];
3581 
3582 	u8         reserved_at_20[0x10];
3583 	u8         op_mod[0x10];
3584 
3585 	u8         other_vport[0x1];
3586 	u8         reserved_at_41[0xf];
3587 	u8         vport_number[0x10];
3588 
3589 	u8         reserved_at_60[0x20];
3590 };
3591 
3592 struct mlx5_ifc_query_vport_counter_out_bits {
3593 	u8         status[0x8];
3594 	u8         reserved_at_8[0x18];
3595 
3596 	u8         syndrome[0x20];
3597 
3598 	u8         reserved_at_40[0x40];
3599 
3600 	struct mlx5_ifc_traffic_counter_bits received_errors;
3601 
3602 	struct mlx5_ifc_traffic_counter_bits transmit_errors;
3603 
3604 	struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3605 
3606 	struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3607 
3608 	struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3609 
3610 	struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3611 
3612 	struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3613 
3614 	struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3615 
3616 	struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3617 
3618 	struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3619 
3620 	struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3621 
3622 	struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3623 
3624 	u8         reserved_at_680[0xa00];
3625 };
3626 
3627 enum {
3628 	MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
3629 };
3630 
3631 struct mlx5_ifc_query_vport_counter_in_bits {
3632 	u8         opcode[0x10];
3633 	u8         reserved_at_10[0x10];
3634 
3635 	u8         reserved_at_20[0x10];
3636 	u8         op_mod[0x10];
3637 
3638 	u8         other_vport[0x1];
3639 	u8         reserved_at_41[0xb];
3640 	u8	   port_num[0x4];
3641 	u8         vport_number[0x10];
3642 
3643 	u8         reserved_at_60[0x60];
3644 
3645 	u8         clear[0x1];
3646 	u8         reserved_at_c1[0x1f];
3647 
3648 	u8         reserved_at_e0[0x20];
3649 };
3650 
3651 struct mlx5_ifc_query_tis_out_bits {
3652 	u8         status[0x8];
3653 	u8         reserved_at_8[0x18];
3654 
3655 	u8         syndrome[0x20];
3656 
3657 	u8         reserved_at_40[0x40];
3658 
3659 	struct mlx5_ifc_tisc_bits tis_context;
3660 };
3661 
3662 struct mlx5_ifc_query_tis_in_bits {
3663 	u8         opcode[0x10];
3664 	u8         reserved_at_10[0x10];
3665 
3666 	u8         reserved_at_20[0x10];
3667 	u8         op_mod[0x10];
3668 
3669 	u8         reserved_at_40[0x8];
3670 	u8         tisn[0x18];
3671 
3672 	u8         reserved_at_60[0x20];
3673 };
3674 
3675 struct mlx5_ifc_query_tir_out_bits {
3676 	u8         status[0x8];
3677 	u8         reserved_at_8[0x18];
3678 
3679 	u8         syndrome[0x20];
3680 
3681 	u8         reserved_at_40[0xc0];
3682 
3683 	struct mlx5_ifc_tirc_bits tir_context;
3684 };
3685 
3686 struct mlx5_ifc_query_tir_in_bits {
3687 	u8         opcode[0x10];
3688 	u8         reserved_at_10[0x10];
3689 
3690 	u8         reserved_at_20[0x10];
3691 	u8         op_mod[0x10];
3692 
3693 	u8         reserved_at_40[0x8];
3694 	u8         tirn[0x18];
3695 
3696 	u8         reserved_at_60[0x20];
3697 };
3698 
3699 struct mlx5_ifc_query_srq_out_bits {
3700 	u8         status[0x8];
3701 	u8         reserved_at_8[0x18];
3702 
3703 	u8         syndrome[0x20];
3704 
3705 	u8         reserved_at_40[0x40];
3706 
3707 	struct mlx5_ifc_srqc_bits srq_context_entry;
3708 
3709 	u8         reserved_at_280[0x600];
3710 
3711 	u8         pas[0][0x40];
3712 };
3713 
3714 struct mlx5_ifc_query_srq_in_bits {
3715 	u8         opcode[0x10];
3716 	u8         reserved_at_10[0x10];
3717 
3718 	u8         reserved_at_20[0x10];
3719 	u8         op_mod[0x10];
3720 
3721 	u8         reserved_at_40[0x8];
3722 	u8         srqn[0x18];
3723 
3724 	u8         reserved_at_60[0x20];
3725 };
3726 
3727 struct mlx5_ifc_query_sq_out_bits {
3728 	u8         status[0x8];
3729 	u8         reserved_at_8[0x18];
3730 
3731 	u8         syndrome[0x20];
3732 
3733 	u8         reserved_at_40[0xc0];
3734 
3735 	struct mlx5_ifc_sqc_bits sq_context;
3736 };
3737 
3738 struct mlx5_ifc_query_sq_in_bits {
3739 	u8         opcode[0x10];
3740 	u8         reserved_at_10[0x10];
3741 
3742 	u8         reserved_at_20[0x10];
3743 	u8         op_mod[0x10];
3744 
3745 	u8         reserved_at_40[0x8];
3746 	u8         sqn[0x18];
3747 
3748 	u8         reserved_at_60[0x20];
3749 };
3750 
3751 struct mlx5_ifc_query_special_contexts_out_bits {
3752 	u8         status[0x8];
3753 	u8         reserved_at_8[0x18];
3754 
3755 	u8         syndrome[0x20];
3756 
3757 	u8         dump_fill_mkey[0x20];
3758 
3759 	u8         resd_lkey[0x20];
3760 
3761 	u8         null_mkey[0x20];
3762 
3763 	u8         reserved_at_a0[0x60];
3764 };
3765 
3766 struct mlx5_ifc_query_special_contexts_in_bits {
3767 	u8         opcode[0x10];
3768 	u8         reserved_at_10[0x10];
3769 
3770 	u8         reserved_at_20[0x10];
3771 	u8         op_mod[0x10];
3772 
3773 	u8         reserved_at_40[0x40];
3774 };
3775 
3776 struct mlx5_ifc_query_scheduling_element_out_bits {
3777 	u8         opcode[0x10];
3778 	u8         reserved_at_10[0x10];
3779 
3780 	u8         reserved_at_20[0x10];
3781 	u8         op_mod[0x10];
3782 
3783 	u8         reserved_at_40[0xc0];
3784 
3785 	struct mlx5_ifc_scheduling_context_bits scheduling_context;
3786 
3787 	u8         reserved_at_300[0x100];
3788 };
3789 
3790 enum {
3791 	SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
3792 };
3793 
3794 struct mlx5_ifc_query_scheduling_element_in_bits {
3795 	u8         opcode[0x10];
3796 	u8         reserved_at_10[0x10];
3797 
3798 	u8         reserved_at_20[0x10];
3799 	u8         op_mod[0x10];
3800 
3801 	u8         scheduling_hierarchy[0x8];
3802 	u8         reserved_at_48[0x18];
3803 
3804 	u8         scheduling_element_id[0x20];
3805 
3806 	u8         reserved_at_80[0x180];
3807 };
3808 
3809 struct mlx5_ifc_query_rqt_out_bits {
3810 	u8         status[0x8];
3811 	u8         reserved_at_8[0x18];
3812 
3813 	u8         syndrome[0x20];
3814 
3815 	u8         reserved_at_40[0xc0];
3816 
3817 	struct mlx5_ifc_rqtc_bits rqt_context;
3818 };
3819 
3820 struct mlx5_ifc_query_rqt_in_bits {
3821 	u8         opcode[0x10];
3822 	u8         reserved_at_10[0x10];
3823 
3824 	u8         reserved_at_20[0x10];
3825 	u8         op_mod[0x10];
3826 
3827 	u8         reserved_at_40[0x8];
3828 	u8         rqtn[0x18];
3829 
3830 	u8         reserved_at_60[0x20];
3831 };
3832 
3833 struct mlx5_ifc_query_rq_out_bits {
3834 	u8         status[0x8];
3835 	u8         reserved_at_8[0x18];
3836 
3837 	u8         syndrome[0x20];
3838 
3839 	u8         reserved_at_40[0xc0];
3840 
3841 	struct mlx5_ifc_rqc_bits rq_context;
3842 };
3843 
3844 struct mlx5_ifc_query_rq_in_bits {
3845 	u8         opcode[0x10];
3846 	u8         reserved_at_10[0x10];
3847 
3848 	u8         reserved_at_20[0x10];
3849 	u8         op_mod[0x10];
3850 
3851 	u8         reserved_at_40[0x8];
3852 	u8         rqn[0x18];
3853 
3854 	u8         reserved_at_60[0x20];
3855 };
3856 
3857 struct mlx5_ifc_query_roce_address_out_bits {
3858 	u8         status[0x8];
3859 	u8         reserved_at_8[0x18];
3860 
3861 	u8         syndrome[0x20];
3862 
3863 	u8         reserved_at_40[0x40];
3864 
3865 	struct mlx5_ifc_roce_addr_layout_bits roce_address;
3866 };
3867 
3868 struct mlx5_ifc_query_roce_address_in_bits {
3869 	u8         opcode[0x10];
3870 	u8         reserved_at_10[0x10];
3871 
3872 	u8         reserved_at_20[0x10];
3873 	u8         op_mod[0x10];
3874 
3875 	u8         roce_address_index[0x10];
3876 	u8         reserved_at_50[0x10];
3877 
3878 	u8         reserved_at_60[0x20];
3879 };
3880 
3881 struct mlx5_ifc_query_rmp_out_bits {
3882 	u8         status[0x8];
3883 	u8         reserved_at_8[0x18];
3884 
3885 	u8         syndrome[0x20];
3886 
3887 	u8         reserved_at_40[0xc0];
3888 
3889 	struct mlx5_ifc_rmpc_bits rmp_context;
3890 };
3891 
3892 struct mlx5_ifc_query_rmp_in_bits {
3893 	u8         opcode[0x10];
3894 	u8         reserved_at_10[0x10];
3895 
3896 	u8         reserved_at_20[0x10];
3897 	u8         op_mod[0x10];
3898 
3899 	u8         reserved_at_40[0x8];
3900 	u8         rmpn[0x18];
3901 
3902 	u8         reserved_at_60[0x20];
3903 };
3904 
3905 struct mlx5_ifc_query_qp_out_bits {
3906 	u8         status[0x8];
3907 	u8         reserved_at_8[0x18];
3908 
3909 	u8         syndrome[0x20];
3910 
3911 	u8         reserved_at_40[0x40];
3912 
3913 	u8         opt_param_mask[0x20];
3914 
3915 	u8         reserved_at_a0[0x20];
3916 
3917 	struct mlx5_ifc_qpc_bits qpc;
3918 
3919 	u8         reserved_at_800[0x80];
3920 
3921 	u8         pas[0][0x40];
3922 };
3923 
3924 struct mlx5_ifc_query_qp_in_bits {
3925 	u8         opcode[0x10];
3926 	u8         reserved_at_10[0x10];
3927 
3928 	u8         reserved_at_20[0x10];
3929 	u8         op_mod[0x10];
3930 
3931 	u8         reserved_at_40[0x8];
3932 	u8         qpn[0x18];
3933 
3934 	u8         reserved_at_60[0x20];
3935 };
3936 
3937 struct mlx5_ifc_query_q_counter_out_bits {
3938 	u8         status[0x8];
3939 	u8         reserved_at_8[0x18];
3940 
3941 	u8         syndrome[0x20];
3942 
3943 	u8         reserved_at_40[0x40];
3944 
3945 	u8         rx_write_requests[0x20];
3946 
3947 	u8         reserved_at_a0[0x20];
3948 
3949 	u8         rx_read_requests[0x20];
3950 
3951 	u8         reserved_at_e0[0x20];
3952 
3953 	u8         rx_atomic_requests[0x20];
3954 
3955 	u8         reserved_at_120[0x20];
3956 
3957 	u8         rx_dct_connect[0x20];
3958 
3959 	u8         reserved_at_160[0x20];
3960 
3961 	u8         out_of_buffer[0x20];
3962 
3963 	u8         reserved_at_1a0[0x20];
3964 
3965 	u8         out_of_sequence[0x20];
3966 
3967 	u8         reserved_at_1e0[0x20];
3968 
3969 	u8         duplicate_request[0x20];
3970 
3971 	u8         reserved_at_220[0x20];
3972 
3973 	u8         rnr_nak_retry_err[0x20];
3974 
3975 	u8         reserved_at_260[0x20];
3976 
3977 	u8         packet_seq_err[0x20];
3978 
3979 	u8         reserved_at_2a0[0x20];
3980 
3981 	u8         implied_nak_seq_err[0x20];
3982 
3983 	u8         reserved_at_2e0[0x20];
3984 
3985 	u8         local_ack_timeout_err[0x20];
3986 
3987 	u8         reserved_at_320[0xa0];
3988 
3989 	u8         resp_local_length_error[0x20];
3990 
3991 	u8         req_local_length_error[0x20];
3992 
3993 	u8         resp_local_qp_error[0x20];
3994 
3995 	u8         local_operation_error[0x20];
3996 
3997 	u8         resp_local_protection[0x20];
3998 
3999 	u8         req_local_protection[0x20];
4000 
4001 	u8         resp_cqe_error[0x20];
4002 
4003 	u8         req_cqe_error[0x20];
4004 
4005 	u8         req_mw_binding[0x20];
4006 
4007 	u8         req_bad_response[0x20];
4008 
4009 	u8         req_remote_invalid_request[0x20];
4010 
4011 	u8         resp_remote_invalid_request[0x20];
4012 
4013 	u8         req_remote_access_errors[0x20];
4014 
4015 	u8	   resp_remote_access_errors[0x20];
4016 
4017 	u8         req_remote_operation_errors[0x20];
4018 
4019 	u8         req_transport_retries_exceeded[0x20];
4020 
4021 	u8         cq_overflow[0x20];
4022 
4023 	u8         resp_cqe_flush_error[0x20];
4024 
4025 	u8         req_cqe_flush_error[0x20];
4026 
4027 	u8         reserved_at_620[0x1e0];
4028 };
4029 
4030 struct mlx5_ifc_query_q_counter_in_bits {
4031 	u8         opcode[0x10];
4032 	u8         reserved_at_10[0x10];
4033 
4034 	u8         reserved_at_20[0x10];
4035 	u8         op_mod[0x10];
4036 
4037 	u8         reserved_at_40[0x80];
4038 
4039 	u8         clear[0x1];
4040 	u8         reserved_at_c1[0x1f];
4041 
4042 	u8         reserved_at_e0[0x18];
4043 	u8         counter_set_id[0x8];
4044 };
4045 
4046 struct mlx5_ifc_query_pages_out_bits {
4047 	u8         status[0x8];
4048 	u8         reserved_at_8[0x18];
4049 
4050 	u8         syndrome[0x20];
4051 
4052 	u8         reserved_at_40[0x10];
4053 	u8         function_id[0x10];
4054 
4055 	u8         num_pages[0x20];
4056 };
4057 
4058 enum {
4059 	MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
4060 	MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
4061 	MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
4062 };
4063 
4064 struct mlx5_ifc_query_pages_in_bits {
4065 	u8         opcode[0x10];
4066 	u8         reserved_at_10[0x10];
4067 
4068 	u8         reserved_at_20[0x10];
4069 	u8         op_mod[0x10];
4070 
4071 	u8         reserved_at_40[0x10];
4072 	u8         function_id[0x10];
4073 
4074 	u8         reserved_at_60[0x20];
4075 };
4076 
4077 struct mlx5_ifc_query_nic_vport_context_out_bits {
4078 	u8         status[0x8];
4079 	u8         reserved_at_8[0x18];
4080 
4081 	u8         syndrome[0x20];
4082 
4083 	u8         reserved_at_40[0x40];
4084 
4085 	struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4086 };
4087 
4088 struct mlx5_ifc_query_nic_vport_context_in_bits {
4089 	u8         opcode[0x10];
4090 	u8         reserved_at_10[0x10];
4091 
4092 	u8         reserved_at_20[0x10];
4093 	u8         op_mod[0x10];
4094 
4095 	u8         other_vport[0x1];
4096 	u8         reserved_at_41[0xf];
4097 	u8         vport_number[0x10];
4098 
4099 	u8         reserved_at_60[0x5];
4100 	u8         allowed_list_type[0x3];
4101 	u8         reserved_at_68[0x18];
4102 };
4103 
4104 struct mlx5_ifc_query_mkey_out_bits {
4105 	u8         status[0x8];
4106 	u8         reserved_at_8[0x18];
4107 
4108 	u8         syndrome[0x20];
4109 
4110 	u8         reserved_at_40[0x40];
4111 
4112 	struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4113 
4114 	u8         reserved_at_280[0x600];
4115 
4116 	u8         bsf0_klm0_pas_mtt0_1[16][0x8];
4117 
4118 	u8         bsf1_klm1_pas_mtt2_3[16][0x8];
4119 };
4120 
4121 struct mlx5_ifc_query_mkey_in_bits {
4122 	u8         opcode[0x10];
4123 	u8         reserved_at_10[0x10];
4124 
4125 	u8         reserved_at_20[0x10];
4126 	u8         op_mod[0x10];
4127 
4128 	u8         reserved_at_40[0x8];
4129 	u8         mkey_index[0x18];
4130 
4131 	u8         pg_access[0x1];
4132 	u8         reserved_at_61[0x1f];
4133 };
4134 
4135 struct mlx5_ifc_query_mad_demux_out_bits {
4136 	u8         status[0x8];
4137 	u8         reserved_at_8[0x18];
4138 
4139 	u8         syndrome[0x20];
4140 
4141 	u8         reserved_at_40[0x40];
4142 
4143 	u8         mad_dumux_parameters_block[0x20];
4144 };
4145 
4146 struct mlx5_ifc_query_mad_demux_in_bits {
4147 	u8         opcode[0x10];
4148 	u8         reserved_at_10[0x10];
4149 
4150 	u8         reserved_at_20[0x10];
4151 	u8         op_mod[0x10];
4152 
4153 	u8         reserved_at_40[0x40];
4154 };
4155 
4156 struct mlx5_ifc_query_l2_table_entry_out_bits {
4157 	u8         status[0x8];
4158 	u8         reserved_at_8[0x18];
4159 
4160 	u8         syndrome[0x20];
4161 
4162 	u8         reserved_at_40[0xa0];
4163 
4164 	u8         reserved_at_e0[0x13];
4165 	u8         vlan_valid[0x1];
4166 	u8         vlan[0xc];
4167 
4168 	struct mlx5_ifc_mac_address_layout_bits mac_address;
4169 
4170 	u8         reserved_at_140[0xc0];
4171 };
4172 
4173 struct mlx5_ifc_query_l2_table_entry_in_bits {
4174 	u8         opcode[0x10];
4175 	u8         reserved_at_10[0x10];
4176 
4177 	u8         reserved_at_20[0x10];
4178 	u8         op_mod[0x10];
4179 
4180 	u8         reserved_at_40[0x60];
4181 
4182 	u8         reserved_at_a0[0x8];
4183 	u8         table_index[0x18];
4184 
4185 	u8         reserved_at_c0[0x140];
4186 };
4187 
4188 struct mlx5_ifc_query_issi_out_bits {
4189 	u8         status[0x8];
4190 	u8         reserved_at_8[0x18];
4191 
4192 	u8         syndrome[0x20];
4193 
4194 	u8         reserved_at_40[0x10];
4195 	u8         current_issi[0x10];
4196 
4197 	u8         reserved_at_60[0xa0];
4198 
4199 	u8         reserved_at_100[76][0x8];
4200 	u8         supported_issi_dw0[0x20];
4201 };
4202 
4203 struct mlx5_ifc_query_issi_in_bits {
4204 	u8         opcode[0x10];
4205 	u8         reserved_at_10[0x10];
4206 
4207 	u8         reserved_at_20[0x10];
4208 	u8         op_mod[0x10];
4209 
4210 	u8         reserved_at_40[0x40];
4211 };
4212 
4213 struct mlx5_ifc_set_driver_version_out_bits {
4214 	u8         status[0x8];
4215 	u8         reserved_0[0x18];
4216 
4217 	u8         syndrome[0x20];
4218 	u8         reserved_1[0x40];
4219 };
4220 
4221 struct mlx5_ifc_set_driver_version_in_bits {
4222 	u8         opcode[0x10];
4223 	u8         reserved_0[0x10];
4224 
4225 	u8         reserved_1[0x10];
4226 	u8         op_mod[0x10];
4227 
4228 	u8         reserved_2[0x40];
4229 	u8         driver_version[64][0x8];
4230 };
4231 
4232 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4233 	u8         status[0x8];
4234 	u8         reserved_at_8[0x18];
4235 
4236 	u8         syndrome[0x20];
4237 
4238 	u8         reserved_at_40[0x40];
4239 
4240 	struct mlx5_ifc_pkey_bits pkey[0];
4241 };
4242 
4243 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4244 	u8         opcode[0x10];
4245 	u8         reserved_at_10[0x10];
4246 
4247 	u8         reserved_at_20[0x10];
4248 	u8         op_mod[0x10];
4249 
4250 	u8         other_vport[0x1];
4251 	u8         reserved_at_41[0xb];
4252 	u8         port_num[0x4];
4253 	u8         vport_number[0x10];
4254 
4255 	u8         reserved_at_60[0x10];
4256 	u8         pkey_index[0x10];
4257 };
4258 
4259 enum {
4260 	MLX5_HCA_VPORT_SEL_PORT_GUID	= 1 << 0,
4261 	MLX5_HCA_VPORT_SEL_NODE_GUID	= 1 << 1,
4262 	MLX5_HCA_VPORT_SEL_STATE_POLICY	= 1 << 2,
4263 };
4264 
4265 struct mlx5_ifc_query_hca_vport_gid_out_bits {
4266 	u8         status[0x8];
4267 	u8         reserved_at_8[0x18];
4268 
4269 	u8         syndrome[0x20];
4270 
4271 	u8         reserved_at_40[0x20];
4272 
4273 	u8         gids_num[0x10];
4274 	u8         reserved_at_70[0x10];
4275 
4276 	struct mlx5_ifc_array128_auto_bits gid[0];
4277 };
4278 
4279 struct mlx5_ifc_query_hca_vport_gid_in_bits {
4280 	u8         opcode[0x10];
4281 	u8         reserved_at_10[0x10];
4282 
4283 	u8         reserved_at_20[0x10];
4284 	u8         op_mod[0x10];
4285 
4286 	u8         other_vport[0x1];
4287 	u8         reserved_at_41[0xb];
4288 	u8         port_num[0x4];
4289 	u8         vport_number[0x10];
4290 
4291 	u8         reserved_at_60[0x10];
4292 	u8         gid_index[0x10];
4293 };
4294 
4295 struct mlx5_ifc_query_hca_vport_context_out_bits {
4296 	u8         status[0x8];
4297 	u8         reserved_at_8[0x18];
4298 
4299 	u8         syndrome[0x20];
4300 
4301 	u8         reserved_at_40[0x40];
4302 
4303 	struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4304 };
4305 
4306 struct mlx5_ifc_query_hca_vport_context_in_bits {
4307 	u8         opcode[0x10];
4308 	u8         reserved_at_10[0x10];
4309 
4310 	u8         reserved_at_20[0x10];
4311 	u8         op_mod[0x10];
4312 
4313 	u8         other_vport[0x1];
4314 	u8         reserved_at_41[0xb];
4315 	u8         port_num[0x4];
4316 	u8         vport_number[0x10];
4317 
4318 	u8         reserved_at_60[0x20];
4319 };
4320 
4321 struct mlx5_ifc_query_hca_cap_out_bits {
4322 	u8         status[0x8];
4323 	u8         reserved_at_8[0x18];
4324 
4325 	u8         syndrome[0x20];
4326 
4327 	u8         reserved_at_40[0x40];
4328 
4329 	union mlx5_ifc_hca_cap_union_bits capability;
4330 };
4331 
4332 struct mlx5_ifc_query_hca_cap_in_bits {
4333 	u8         opcode[0x10];
4334 	u8         reserved_at_10[0x10];
4335 
4336 	u8         reserved_at_20[0x10];
4337 	u8         op_mod[0x10];
4338 
4339 	u8         reserved_at_40[0x40];
4340 };
4341 
4342 struct mlx5_ifc_query_flow_table_out_bits {
4343 	u8         status[0x8];
4344 	u8         reserved_at_8[0x18];
4345 
4346 	u8         syndrome[0x20];
4347 
4348 	u8         reserved_at_40[0x80];
4349 
4350 	u8         reserved_at_c0[0x8];
4351 	u8         level[0x8];
4352 	u8         reserved_at_d0[0x8];
4353 	u8         log_size[0x8];
4354 
4355 	u8         reserved_at_e0[0x120];
4356 };
4357 
4358 struct mlx5_ifc_query_flow_table_in_bits {
4359 	u8         opcode[0x10];
4360 	u8         reserved_at_10[0x10];
4361 
4362 	u8         reserved_at_20[0x10];
4363 	u8         op_mod[0x10];
4364 
4365 	u8         reserved_at_40[0x40];
4366 
4367 	u8         table_type[0x8];
4368 	u8         reserved_at_88[0x18];
4369 
4370 	u8         reserved_at_a0[0x8];
4371 	u8         table_id[0x18];
4372 
4373 	u8         reserved_at_c0[0x140];
4374 };
4375 
4376 struct mlx5_ifc_query_fte_out_bits {
4377 	u8         status[0x8];
4378 	u8         reserved_at_8[0x18];
4379 
4380 	u8         syndrome[0x20];
4381 
4382 	u8         reserved_at_40[0x1c0];
4383 
4384 	struct mlx5_ifc_flow_context_bits flow_context;
4385 };
4386 
4387 struct mlx5_ifc_query_fte_in_bits {
4388 	u8         opcode[0x10];
4389 	u8         reserved_at_10[0x10];
4390 
4391 	u8         reserved_at_20[0x10];
4392 	u8         op_mod[0x10];
4393 
4394 	u8         reserved_at_40[0x40];
4395 
4396 	u8         table_type[0x8];
4397 	u8         reserved_at_88[0x18];
4398 
4399 	u8         reserved_at_a0[0x8];
4400 	u8         table_id[0x18];
4401 
4402 	u8         reserved_at_c0[0x40];
4403 
4404 	u8         flow_index[0x20];
4405 
4406 	u8         reserved_at_120[0xe0];
4407 };
4408 
4409 enum {
4410 	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
4411 	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
4412 	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
4413 };
4414 
4415 struct mlx5_ifc_query_flow_group_out_bits {
4416 	u8         status[0x8];
4417 	u8         reserved_at_8[0x18];
4418 
4419 	u8         syndrome[0x20];
4420 
4421 	u8         reserved_at_40[0xa0];
4422 
4423 	u8         start_flow_index[0x20];
4424 
4425 	u8         reserved_at_100[0x20];
4426 
4427 	u8         end_flow_index[0x20];
4428 
4429 	u8         reserved_at_140[0xa0];
4430 
4431 	u8         reserved_at_1e0[0x18];
4432 	u8         match_criteria_enable[0x8];
4433 
4434 	struct mlx5_ifc_fte_match_param_bits match_criteria;
4435 
4436 	u8         reserved_at_1200[0xe00];
4437 };
4438 
4439 struct mlx5_ifc_query_flow_group_in_bits {
4440 	u8         opcode[0x10];
4441 	u8         reserved_at_10[0x10];
4442 
4443 	u8         reserved_at_20[0x10];
4444 	u8         op_mod[0x10];
4445 
4446 	u8         reserved_at_40[0x40];
4447 
4448 	u8         table_type[0x8];
4449 	u8         reserved_at_88[0x18];
4450 
4451 	u8         reserved_at_a0[0x8];
4452 	u8         table_id[0x18];
4453 
4454 	u8         group_id[0x20];
4455 
4456 	u8         reserved_at_e0[0x120];
4457 };
4458 
4459 struct mlx5_ifc_query_flow_counter_out_bits {
4460 	u8         status[0x8];
4461 	u8         reserved_at_8[0x18];
4462 
4463 	u8         syndrome[0x20];
4464 
4465 	u8         reserved_at_40[0x40];
4466 
4467 	struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4468 };
4469 
4470 struct mlx5_ifc_query_flow_counter_in_bits {
4471 	u8         opcode[0x10];
4472 	u8         reserved_at_10[0x10];
4473 
4474 	u8         reserved_at_20[0x10];
4475 	u8         op_mod[0x10];
4476 
4477 	u8         reserved_at_40[0x80];
4478 
4479 	u8         clear[0x1];
4480 	u8         reserved_at_c1[0xf];
4481 	u8         num_of_counters[0x10];
4482 
4483 	u8         flow_counter_id[0x20];
4484 };
4485 
4486 struct mlx5_ifc_query_esw_vport_context_out_bits {
4487 	u8         status[0x8];
4488 	u8         reserved_at_8[0x18];
4489 
4490 	u8         syndrome[0x20];
4491 
4492 	u8         reserved_at_40[0x40];
4493 
4494 	struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4495 };
4496 
4497 struct mlx5_ifc_query_esw_vport_context_in_bits {
4498 	u8         opcode[0x10];
4499 	u8         reserved_at_10[0x10];
4500 
4501 	u8         reserved_at_20[0x10];
4502 	u8         op_mod[0x10];
4503 
4504 	u8         other_vport[0x1];
4505 	u8         reserved_at_41[0xf];
4506 	u8         vport_number[0x10];
4507 
4508 	u8         reserved_at_60[0x20];
4509 };
4510 
4511 struct mlx5_ifc_modify_esw_vport_context_out_bits {
4512 	u8         status[0x8];
4513 	u8         reserved_at_8[0x18];
4514 
4515 	u8         syndrome[0x20];
4516 
4517 	u8         reserved_at_40[0x40];
4518 };
4519 
4520 struct mlx5_ifc_esw_vport_context_fields_select_bits {
4521 	u8         reserved_at_0[0x1c];
4522 	u8         vport_cvlan_insert[0x1];
4523 	u8         vport_svlan_insert[0x1];
4524 	u8         vport_cvlan_strip[0x1];
4525 	u8         vport_svlan_strip[0x1];
4526 };
4527 
4528 struct mlx5_ifc_modify_esw_vport_context_in_bits {
4529 	u8         opcode[0x10];
4530 	u8         reserved_at_10[0x10];
4531 
4532 	u8         reserved_at_20[0x10];
4533 	u8         op_mod[0x10];
4534 
4535 	u8         other_vport[0x1];
4536 	u8         reserved_at_41[0xf];
4537 	u8         vport_number[0x10];
4538 
4539 	struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
4540 
4541 	struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4542 };
4543 
4544 struct mlx5_ifc_query_eq_out_bits {
4545 	u8         status[0x8];
4546 	u8         reserved_at_8[0x18];
4547 
4548 	u8         syndrome[0x20];
4549 
4550 	u8         reserved_at_40[0x40];
4551 
4552 	struct mlx5_ifc_eqc_bits eq_context_entry;
4553 
4554 	u8         reserved_at_280[0x40];
4555 
4556 	u8         event_bitmask[0x40];
4557 
4558 	u8         reserved_at_300[0x580];
4559 
4560 	u8         pas[0][0x40];
4561 };
4562 
4563 struct mlx5_ifc_query_eq_in_bits {
4564 	u8         opcode[0x10];
4565 	u8         reserved_at_10[0x10];
4566 
4567 	u8         reserved_at_20[0x10];
4568 	u8         op_mod[0x10];
4569 
4570 	u8         reserved_at_40[0x18];
4571 	u8         eq_number[0x8];
4572 
4573 	u8         reserved_at_60[0x20];
4574 };
4575 
4576 struct mlx5_ifc_encap_header_in_bits {
4577 	u8         reserved_at_0[0x5];
4578 	u8         header_type[0x3];
4579 	u8         reserved_at_8[0xe];
4580 	u8         encap_header_size[0xa];
4581 
4582 	u8         reserved_at_20[0x10];
4583 	u8         encap_header[2][0x8];
4584 
4585 	u8         more_encap_header[0][0x8];
4586 };
4587 
4588 struct mlx5_ifc_query_encap_header_out_bits {
4589 	u8         status[0x8];
4590 	u8         reserved_at_8[0x18];
4591 
4592 	u8         syndrome[0x20];
4593 
4594 	u8         reserved_at_40[0xa0];
4595 
4596 	struct mlx5_ifc_encap_header_in_bits encap_header[0];
4597 };
4598 
4599 struct mlx5_ifc_query_encap_header_in_bits {
4600 	u8         opcode[0x10];
4601 	u8         reserved_at_10[0x10];
4602 
4603 	u8         reserved_at_20[0x10];
4604 	u8         op_mod[0x10];
4605 
4606 	u8         encap_id[0x20];
4607 
4608 	u8         reserved_at_60[0xa0];
4609 };
4610 
4611 struct mlx5_ifc_alloc_encap_header_out_bits {
4612 	u8         status[0x8];
4613 	u8         reserved_at_8[0x18];
4614 
4615 	u8         syndrome[0x20];
4616 
4617 	u8         encap_id[0x20];
4618 
4619 	u8         reserved_at_60[0x20];
4620 };
4621 
4622 struct mlx5_ifc_alloc_encap_header_in_bits {
4623 	u8         opcode[0x10];
4624 	u8         reserved_at_10[0x10];
4625 
4626 	u8         reserved_at_20[0x10];
4627 	u8         op_mod[0x10];
4628 
4629 	u8         reserved_at_40[0xa0];
4630 
4631 	struct mlx5_ifc_encap_header_in_bits encap_header;
4632 };
4633 
4634 struct mlx5_ifc_dealloc_encap_header_out_bits {
4635 	u8         status[0x8];
4636 	u8         reserved_at_8[0x18];
4637 
4638 	u8         syndrome[0x20];
4639 
4640 	u8         reserved_at_40[0x40];
4641 };
4642 
4643 struct mlx5_ifc_dealloc_encap_header_in_bits {
4644 	u8         opcode[0x10];
4645 	u8         reserved_at_10[0x10];
4646 
4647 	u8         reserved_20[0x10];
4648 	u8         op_mod[0x10];
4649 
4650 	u8         encap_id[0x20];
4651 
4652 	u8         reserved_60[0x20];
4653 };
4654 
4655 struct mlx5_ifc_set_action_in_bits {
4656 	u8         action_type[0x4];
4657 	u8         field[0xc];
4658 	u8         reserved_at_10[0x3];
4659 	u8         offset[0x5];
4660 	u8         reserved_at_18[0x3];
4661 	u8         length[0x5];
4662 
4663 	u8         data[0x20];
4664 };
4665 
4666 struct mlx5_ifc_add_action_in_bits {
4667 	u8         action_type[0x4];
4668 	u8         field[0xc];
4669 	u8         reserved_at_10[0x10];
4670 
4671 	u8         data[0x20];
4672 };
4673 
4674 union mlx5_ifc_set_action_in_add_action_in_auto_bits {
4675 	struct mlx5_ifc_set_action_in_bits set_action_in;
4676 	struct mlx5_ifc_add_action_in_bits add_action_in;
4677 	u8         reserved_at_0[0x40];
4678 };
4679 
4680 enum {
4681 	MLX5_ACTION_TYPE_SET   = 0x1,
4682 	MLX5_ACTION_TYPE_ADD   = 0x2,
4683 };
4684 
4685 enum {
4686 	MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16    = 0x1,
4687 	MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0     = 0x2,
4688 	MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE     = 0x3,
4689 	MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16    = 0x4,
4690 	MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0     = 0x5,
4691 	MLX5_ACTION_IN_FIELD_OUT_IP_DSCP       = 0x6,
4692 	MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS     = 0x7,
4693 	MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT     = 0x8,
4694 	MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT     = 0x9,
4695 	MLX5_ACTION_IN_FIELD_OUT_IP_TTL        = 0xa,
4696 	MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT     = 0xb,
4697 	MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT     = 0xc,
4698 	MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96  = 0xd,
4699 	MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64   = 0xe,
4700 	MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32   = 0xf,
4701 	MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0    = 0x10,
4702 	MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96  = 0x11,
4703 	MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64   = 0x12,
4704 	MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32   = 0x13,
4705 	MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0    = 0x14,
4706 	MLX5_ACTION_IN_FIELD_OUT_SIPV4         = 0x15,
4707 	MLX5_ACTION_IN_FIELD_OUT_DIPV4         = 0x16,
4708 	MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
4709 };
4710 
4711 struct mlx5_ifc_alloc_modify_header_context_out_bits {
4712 	u8         status[0x8];
4713 	u8         reserved_at_8[0x18];
4714 
4715 	u8         syndrome[0x20];
4716 
4717 	u8         modify_header_id[0x20];
4718 
4719 	u8         reserved_at_60[0x20];
4720 };
4721 
4722 struct mlx5_ifc_alloc_modify_header_context_in_bits {
4723 	u8         opcode[0x10];
4724 	u8         reserved_at_10[0x10];
4725 
4726 	u8         reserved_at_20[0x10];
4727 	u8         op_mod[0x10];
4728 
4729 	u8         reserved_at_40[0x20];
4730 
4731 	u8         table_type[0x8];
4732 	u8         reserved_at_68[0x10];
4733 	u8         num_of_actions[0x8];
4734 
4735 	union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0];
4736 };
4737 
4738 struct mlx5_ifc_dealloc_modify_header_context_out_bits {
4739 	u8         status[0x8];
4740 	u8         reserved_at_8[0x18];
4741 
4742 	u8         syndrome[0x20];
4743 
4744 	u8         reserved_at_40[0x40];
4745 };
4746 
4747 struct mlx5_ifc_dealloc_modify_header_context_in_bits {
4748 	u8         opcode[0x10];
4749 	u8         reserved_at_10[0x10];
4750 
4751 	u8         reserved_at_20[0x10];
4752 	u8         op_mod[0x10];
4753 
4754 	u8         modify_header_id[0x20];
4755 
4756 	u8         reserved_at_60[0x20];
4757 };
4758 
4759 struct mlx5_ifc_query_dct_out_bits {
4760 	u8         status[0x8];
4761 	u8         reserved_at_8[0x18];
4762 
4763 	u8         syndrome[0x20];
4764 
4765 	u8         reserved_at_40[0x40];
4766 
4767 	struct mlx5_ifc_dctc_bits dct_context_entry;
4768 
4769 	u8         reserved_at_280[0x180];
4770 };
4771 
4772 struct mlx5_ifc_query_dct_in_bits {
4773 	u8         opcode[0x10];
4774 	u8         reserved_at_10[0x10];
4775 
4776 	u8         reserved_at_20[0x10];
4777 	u8         op_mod[0x10];
4778 
4779 	u8         reserved_at_40[0x8];
4780 	u8         dctn[0x18];
4781 
4782 	u8         reserved_at_60[0x20];
4783 };
4784 
4785 struct mlx5_ifc_query_cq_out_bits {
4786 	u8         status[0x8];
4787 	u8         reserved_at_8[0x18];
4788 
4789 	u8         syndrome[0x20];
4790 
4791 	u8         reserved_at_40[0x40];
4792 
4793 	struct mlx5_ifc_cqc_bits cq_context;
4794 
4795 	u8         reserved_at_280[0x600];
4796 
4797 	u8         pas[0][0x40];
4798 };
4799 
4800 struct mlx5_ifc_query_cq_in_bits {
4801 	u8         opcode[0x10];
4802 	u8         reserved_at_10[0x10];
4803 
4804 	u8         reserved_at_20[0x10];
4805 	u8         op_mod[0x10];
4806 
4807 	u8         reserved_at_40[0x8];
4808 	u8         cqn[0x18];
4809 
4810 	u8         reserved_at_60[0x20];
4811 };
4812 
4813 struct mlx5_ifc_query_cong_status_out_bits {
4814 	u8         status[0x8];
4815 	u8         reserved_at_8[0x18];
4816 
4817 	u8         syndrome[0x20];
4818 
4819 	u8         reserved_at_40[0x20];
4820 
4821 	u8         enable[0x1];
4822 	u8         tag_enable[0x1];
4823 	u8         reserved_at_62[0x1e];
4824 };
4825 
4826 struct mlx5_ifc_query_cong_status_in_bits {
4827 	u8         opcode[0x10];
4828 	u8         reserved_at_10[0x10];
4829 
4830 	u8         reserved_at_20[0x10];
4831 	u8         op_mod[0x10];
4832 
4833 	u8         reserved_at_40[0x18];
4834 	u8         priority[0x4];
4835 	u8         cong_protocol[0x4];
4836 
4837 	u8         reserved_at_60[0x20];
4838 };
4839 
4840 struct mlx5_ifc_query_cong_statistics_out_bits {
4841 	u8         status[0x8];
4842 	u8         reserved_at_8[0x18];
4843 
4844 	u8         syndrome[0x20];
4845 
4846 	u8         reserved_at_40[0x40];
4847 
4848 	u8         rp_cur_flows[0x20];
4849 
4850 	u8         sum_flows[0x20];
4851 
4852 	u8         rp_cnp_ignored_high[0x20];
4853 
4854 	u8         rp_cnp_ignored_low[0x20];
4855 
4856 	u8         rp_cnp_handled_high[0x20];
4857 
4858 	u8         rp_cnp_handled_low[0x20];
4859 
4860 	u8         reserved_at_140[0x100];
4861 
4862 	u8         time_stamp_high[0x20];
4863 
4864 	u8         time_stamp_low[0x20];
4865 
4866 	u8         accumulators_period[0x20];
4867 
4868 	u8         np_ecn_marked_roce_packets_high[0x20];
4869 
4870 	u8         np_ecn_marked_roce_packets_low[0x20];
4871 
4872 	u8         np_cnp_sent_high[0x20];
4873 
4874 	u8         np_cnp_sent_low[0x20];
4875 
4876 	u8         reserved_at_320[0x560];
4877 };
4878 
4879 struct mlx5_ifc_query_cong_statistics_in_bits {
4880 	u8         opcode[0x10];
4881 	u8         reserved_at_10[0x10];
4882 
4883 	u8         reserved_at_20[0x10];
4884 	u8         op_mod[0x10];
4885 
4886 	u8         clear[0x1];
4887 	u8         reserved_at_41[0x1f];
4888 
4889 	u8         reserved_at_60[0x20];
4890 };
4891 
4892 struct mlx5_ifc_query_cong_params_out_bits {
4893 	u8         status[0x8];
4894 	u8         reserved_at_8[0x18];
4895 
4896 	u8         syndrome[0x20];
4897 
4898 	u8         reserved_at_40[0x40];
4899 
4900 	union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4901 };
4902 
4903 struct mlx5_ifc_query_cong_params_in_bits {
4904 	u8         opcode[0x10];
4905 	u8         reserved_at_10[0x10];
4906 
4907 	u8         reserved_at_20[0x10];
4908 	u8         op_mod[0x10];
4909 
4910 	u8         reserved_at_40[0x1c];
4911 	u8         cong_protocol[0x4];
4912 
4913 	u8         reserved_at_60[0x20];
4914 };
4915 
4916 struct mlx5_ifc_query_adapter_out_bits {
4917 	u8         status[0x8];
4918 	u8         reserved_at_8[0x18];
4919 
4920 	u8         syndrome[0x20];
4921 
4922 	u8         reserved_at_40[0x40];
4923 
4924 	struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
4925 };
4926 
4927 struct mlx5_ifc_query_adapter_in_bits {
4928 	u8         opcode[0x10];
4929 	u8         reserved_at_10[0x10];
4930 
4931 	u8         reserved_at_20[0x10];
4932 	u8         op_mod[0x10];
4933 
4934 	u8         reserved_at_40[0x40];
4935 };
4936 
4937 struct mlx5_ifc_qp_2rst_out_bits {
4938 	u8         status[0x8];
4939 	u8         reserved_at_8[0x18];
4940 
4941 	u8         syndrome[0x20];
4942 
4943 	u8         reserved_at_40[0x40];
4944 };
4945 
4946 struct mlx5_ifc_qp_2rst_in_bits {
4947 	u8         opcode[0x10];
4948 	u8         reserved_at_10[0x10];
4949 
4950 	u8         reserved_at_20[0x10];
4951 	u8         op_mod[0x10];
4952 
4953 	u8         reserved_at_40[0x8];
4954 	u8         qpn[0x18];
4955 
4956 	u8         reserved_at_60[0x20];
4957 };
4958 
4959 struct mlx5_ifc_qp_2err_out_bits {
4960 	u8         status[0x8];
4961 	u8         reserved_at_8[0x18];
4962 
4963 	u8         syndrome[0x20];
4964 
4965 	u8         reserved_at_40[0x40];
4966 };
4967 
4968 struct mlx5_ifc_qp_2err_in_bits {
4969 	u8         opcode[0x10];
4970 	u8         reserved_at_10[0x10];
4971 
4972 	u8         reserved_at_20[0x10];
4973 	u8         op_mod[0x10];
4974 
4975 	u8         reserved_at_40[0x8];
4976 	u8         qpn[0x18];
4977 
4978 	u8         reserved_at_60[0x20];
4979 };
4980 
4981 struct mlx5_ifc_page_fault_resume_out_bits {
4982 	u8         status[0x8];
4983 	u8         reserved_at_8[0x18];
4984 
4985 	u8         syndrome[0x20];
4986 
4987 	u8         reserved_at_40[0x40];
4988 };
4989 
4990 struct mlx5_ifc_page_fault_resume_in_bits {
4991 	u8         opcode[0x10];
4992 	u8         reserved_at_10[0x10];
4993 
4994 	u8         reserved_at_20[0x10];
4995 	u8         op_mod[0x10];
4996 
4997 	u8         error[0x1];
4998 	u8         reserved_at_41[0x4];
4999 	u8         page_fault_type[0x3];
5000 	u8         wq_number[0x18];
5001 
5002 	u8         reserved_at_60[0x8];
5003 	u8         token[0x18];
5004 };
5005 
5006 struct mlx5_ifc_nop_out_bits {
5007 	u8         status[0x8];
5008 	u8         reserved_at_8[0x18];
5009 
5010 	u8         syndrome[0x20];
5011 
5012 	u8         reserved_at_40[0x40];
5013 };
5014 
5015 struct mlx5_ifc_nop_in_bits {
5016 	u8         opcode[0x10];
5017 	u8         reserved_at_10[0x10];
5018 
5019 	u8         reserved_at_20[0x10];
5020 	u8         op_mod[0x10];
5021 
5022 	u8         reserved_at_40[0x40];
5023 };
5024 
5025 struct mlx5_ifc_modify_vport_state_out_bits {
5026 	u8         status[0x8];
5027 	u8         reserved_at_8[0x18];
5028 
5029 	u8         syndrome[0x20];
5030 
5031 	u8         reserved_at_40[0x40];
5032 };
5033 
5034 struct mlx5_ifc_modify_vport_state_in_bits {
5035 	u8         opcode[0x10];
5036 	u8         reserved_at_10[0x10];
5037 
5038 	u8         reserved_at_20[0x10];
5039 	u8         op_mod[0x10];
5040 
5041 	u8         other_vport[0x1];
5042 	u8         reserved_at_41[0xf];
5043 	u8         vport_number[0x10];
5044 
5045 	u8         reserved_at_60[0x18];
5046 	u8         admin_state[0x4];
5047 	u8         reserved_at_7c[0x4];
5048 };
5049 
5050 struct mlx5_ifc_modify_tis_out_bits {
5051 	u8         status[0x8];
5052 	u8         reserved_at_8[0x18];
5053 
5054 	u8         syndrome[0x20];
5055 
5056 	u8         reserved_at_40[0x40];
5057 };
5058 
5059 struct mlx5_ifc_modify_tis_bitmask_bits {
5060 	u8         reserved_at_0[0x20];
5061 
5062 	u8         reserved_at_20[0x1d];
5063 	u8         lag_tx_port_affinity[0x1];
5064 	u8         strict_lag_tx_port_affinity[0x1];
5065 	u8         prio[0x1];
5066 };
5067 
5068 struct mlx5_ifc_modify_tis_in_bits {
5069 	u8         opcode[0x10];
5070 	u8         reserved_at_10[0x10];
5071 
5072 	u8         reserved_at_20[0x10];
5073 	u8         op_mod[0x10];
5074 
5075 	u8         reserved_at_40[0x8];
5076 	u8         tisn[0x18];
5077 
5078 	u8         reserved_at_60[0x20];
5079 
5080 	struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
5081 
5082 	u8         reserved_at_c0[0x40];
5083 
5084 	struct mlx5_ifc_tisc_bits ctx;
5085 };
5086 
5087 struct mlx5_ifc_modify_tir_bitmask_bits {
5088 	u8	   reserved_at_0[0x20];
5089 
5090 	u8         reserved_at_20[0x1b];
5091 	u8         self_lb_en[0x1];
5092 	u8         reserved_at_3c[0x1];
5093 	u8         hash[0x1];
5094 	u8         reserved_at_3e[0x1];
5095 	u8         lro[0x1];
5096 };
5097 
5098 struct mlx5_ifc_modify_tir_out_bits {
5099 	u8         status[0x8];
5100 	u8         reserved_at_8[0x18];
5101 
5102 	u8         syndrome[0x20];
5103 
5104 	u8         reserved_at_40[0x40];
5105 };
5106 
5107 struct mlx5_ifc_modify_tir_in_bits {
5108 	u8         opcode[0x10];
5109 	u8         reserved_at_10[0x10];
5110 
5111 	u8         reserved_at_20[0x10];
5112 	u8         op_mod[0x10];
5113 
5114 	u8         reserved_at_40[0x8];
5115 	u8         tirn[0x18];
5116 
5117 	u8         reserved_at_60[0x20];
5118 
5119 	struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
5120 
5121 	u8         reserved_at_c0[0x40];
5122 
5123 	struct mlx5_ifc_tirc_bits ctx;
5124 };
5125 
5126 struct mlx5_ifc_modify_sq_out_bits {
5127 	u8         status[0x8];
5128 	u8         reserved_at_8[0x18];
5129 
5130 	u8         syndrome[0x20];
5131 
5132 	u8         reserved_at_40[0x40];
5133 };
5134 
5135 struct mlx5_ifc_modify_sq_in_bits {
5136 	u8         opcode[0x10];
5137 	u8         reserved_at_10[0x10];
5138 
5139 	u8         reserved_at_20[0x10];
5140 	u8         op_mod[0x10];
5141 
5142 	u8         sq_state[0x4];
5143 	u8         reserved_at_44[0x4];
5144 	u8         sqn[0x18];
5145 
5146 	u8         reserved_at_60[0x20];
5147 
5148 	u8         modify_bitmask[0x40];
5149 
5150 	u8         reserved_at_c0[0x40];
5151 
5152 	struct mlx5_ifc_sqc_bits ctx;
5153 };
5154 
5155 struct mlx5_ifc_modify_scheduling_element_out_bits {
5156 	u8         status[0x8];
5157 	u8         reserved_at_8[0x18];
5158 
5159 	u8         syndrome[0x20];
5160 
5161 	u8         reserved_at_40[0x1c0];
5162 };
5163 
5164 enum {
5165 	MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
5166 	MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
5167 };
5168 
5169 struct mlx5_ifc_modify_scheduling_element_in_bits {
5170 	u8         opcode[0x10];
5171 	u8         reserved_at_10[0x10];
5172 
5173 	u8         reserved_at_20[0x10];
5174 	u8         op_mod[0x10];
5175 
5176 	u8         scheduling_hierarchy[0x8];
5177 	u8         reserved_at_48[0x18];
5178 
5179 	u8         scheduling_element_id[0x20];
5180 
5181 	u8         reserved_at_80[0x20];
5182 
5183 	u8         modify_bitmask[0x20];
5184 
5185 	u8         reserved_at_c0[0x40];
5186 
5187 	struct mlx5_ifc_scheduling_context_bits scheduling_context;
5188 
5189 	u8         reserved_at_300[0x100];
5190 };
5191 
5192 struct mlx5_ifc_modify_rqt_out_bits {
5193 	u8         status[0x8];
5194 	u8         reserved_at_8[0x18];
5195 
5196 	u8         syndrome[0x20];
5197 
5198 	u8         reserved_at_40[0x40];
5199 };
5200 
5201 struct mlx5_ifc_rqt_bitmask_bits {
5202 	u8	   reserved_at_0[0x20];
5203 
5204 	u8         reserved_at_20[0x1f];
5205 	u8         rqn_list[0x1];
5206 };
5207 
5208 struct mlx5_ifc_modify_rqt_in_bits {
5209 	u8         opcode[0x10];
5210 	u8         reserved_at_10[0x10];
5211 
5212 	u8         reserved_at_20[0x10];
5213 	u8         op_mod[0x10];
5214 
5215 	u8         reserved_at_40[0x8];
5216 	u8         rqtn[0x18];
5217 
5218 	u8         reserved_at_60[0x20];
5219 
5220 	struct mlx5_ifc_rqt_bitmask_bits bitmask;
5221 
5222 	u8         reserved_at_c0[0x40];
5223 
5224 	struct mlx5_ifc_rqtc_bits ctx;
5225 };
5226 
5227 struct mlx5_ifc_modify_rq_out_bits {
5228 	u8         status[0x8];
5229 	u8         reserved_at_8[0x18];
5230 
5231 	u8         syndrome[0x20];
5232 
5233 	u8         reserved_at_40[0x40];
5234 };
5235 
5236 enum {
5237 	MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
5238 	MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
5239 	MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
5240 };
5241 
5242 struct mlx5_ifc_modify_rq_in_bits {
5243 	u8         opcode[0x10];
5244 	u8         reserved_at_10[0x10];
5245 
5246 	u8         reserved_at_20[0x10];
5247 	u8         op_mod[0x10];
5248 
5249 	u8         rq_state[0x4];
5250 	u8         reserved_at_44[0x4];
5251 	u8         rqn[0x18];
5252 
5253 	u8         reserved_at_60[0x20];
5254 
5255 	u8         modify_bitmask[0x40];
5256 
5257 	u8         reserved_at_c0[0x40];
5258 
5259 	struct mlx5_ifc_rqc_bits ctx;
5260 };
5261 
5262 struct mlx5_ifc_modify_rmp_out_bits {
5263 	u8         status[0x8];
5264 	u8         reserved_at_8[0x18];
5265 
5266 	u8         syndrome[0x20];
5267 
5268 	u8         reserved_at_40[0x40];
5269 };
5270 
5271 struct mlx5_ifc_rmp_bitmask_bits {
5272 	u8	   reserved_at_0[0x20];
5273 
5274 	u8         reserved_at_20[0x1f];
5275 	u8         lwm[0x1];
5276 };
5277 
5278 struct mlx5_ifc_modify_rmp_in_bits {
5279 	u8         opcode[0x10];
5280 	u8         reserved_at_10[0x10];
5281 
5282 	u8         reserved_at_20[0x10];
5283 	u8         op_mod[0x10];
5284 
5285 	u8         rmp_state[0x4];
5286 	u8         reserved_at_44[0x4];
5287 	u8         rmpn[0x18];
5288 
5289 	u8         reserved_at_60[0x20];
5290 
5291 	struct mlx5_ifc_rmp_bitmask_bits bitmask;
5292 
5293 	u8         reserved_at_c0[0x40];
5294 
5295 	struct mlx5_ifc_rmpc_bits ctx;
5296 };
5297 
5298 struct mlx5_ifc_modify_nic_vport_context_out_bits {
5299 	u8         status[0x8];
5300 	u8         reserved_at_8[0x18];
5301 
5302 	u8         syndrome[0x20];
5303 
5304 	u8         reserved_at_40[0x40];
5305 };
5306 
5307 struct mlx5_ifc_modify_nic_vport_field_select_bits {
5308 	u8         reserved_at_0[0x14];
5309 	u8         disable_uc_local_lb[0x1];
5310 	u8         disable_mc_local_lb[0x1];
5311 	u8         node_guid[0x1];
5312 	u8         port_guid[0x1];
5313 	u8         min_inline[0x1];
5314 	u8         mtu[0x1];
5315 	u8         change_event[0x1];
5316 	u8         promisc[0x1];
5317 	u8         permanent_address[0x1];
5318 	u8         addresses_list[0x1];
5319 	u8         roce_en[0x1];
5320 	u8         reserved_at_1f[0x1];
5321 };
5322 
5323 struct mlx5_ifc_modify_nic_vport_context_in_bits {
5324 	u8         opcode[0x10];
5325 	u8         reserved_at_10[0x10];
5326 
5327 	u8         reserved_at_20[0x10];
5328 	u8         op_mod[0x10];
5329 
5330 	u8         other_vport[0x1];
5331 	u8         reserved_at_41[0xf];
5332 	u8         vport_number[0x10];
5333 
5334 	struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5335 
5336 	u8         reserved_at_80[0x780];
5337 
5338 	struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5339 };
5340 
5341 struct mlx5_ifc_modify_hca_vport_context_out_bits {
5342 	u8         status[0x8];
5343 	u8         reserved_at_8[0x18];
5344 
5345 	u8         syndrome[0x20];
5346 
5347 	u8         reserved_at_40[0x40];
5348 };
5349 
5350 struct mlx5_ifc_modify_hca_vport_context_in_bits {
5351 	u8         opcode[0x10];
5352 	u8         reserved_at_10[0x10];
5353 
5354 	u8         reserved_at_20[0x10];
5355 	u8         op_mod[0x10];
5356 
5357 	u8         other_vport[0x1];
5358 	u8         reserved_at_41[0xb];
5359 	u8         port_num[0x4];
5360 	u8         vport_number[0x10];
5361 
5362 	u8         reserved_at_60[0x20];
5363 
5364 	struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5365 };
5366 
5367 struct mlx5_ifc_modify_cq_out_bits {
5368 	u8         status[0x8];
5369 	u8         reserved_at_8[0x18];
5370 
5371 	u8         syndrome[0x20];
5372 
5373 	u8         reserved_at_40[0x40];
5374 };
5375 
5376 enum {
5377 	MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
5378 	MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
5379 };
5380 
5381 struct mlx5_ifc_modify_cq_in_bits {
5382 	u8         opcode[0x10];
5383 	u8         reserved_at_10[0x10];
5384 
5385 	u8         reserved_at_20[0x10];
5386 	u8         op_mod[0x10];
5387 
5388 	u8         reserved_at_40[0x8];
5389 	u8         cqn[0x18];
5390 
5391 	union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5392 
5393 	struct mlx5_ifc_cqc_bits cq_context;
5394 
5395 	u8         reserved_at_280[0x600];
5396 
5397 	u8         pas[0][0x40];
5398 };
5399 
5400 struct mlx5_ifc_modify_cong_status_out_bits {
5401 	u8         status[0x8];
5402 	u8         reserved_at_8[0x18];
5403 
5404 	u8         syndrome[0x20];
5405 
5406 	u8         reserved_at_40[0x40];
5407 };
5408 
5409 struct mlx5_ifc_modify_cong_status_in_bits {
5410 	u8         opcode[0x10];
5411 	u8         reserved_at_10[0x10];
5412 
5413 	u8         reserved_at_20[0x10];
5414 	u8         op_mod[0x10];
5415 
5416 	u8         reserved_at_40[0x18];
5417 	u8         priority[0x4];
5418 	u8         cong_protocol[0x4];
5419 
5420 	u8         enable[0x1];
5421 	u8         tag_enable[0x1];
5422 	u8         reserved_at_62[0x1e];
5423 };
5424 
5425 struct mlx5_ifc_modify_cong_params_out_bits {
5426 	u8         status[0x8];
5427 	u8         reserved_at_8[0x18];
5428 
5429 	u8         syndrome[0x20];
5430 
5431 	u8         reserved_at_40[0x40];
5432 };
5433 
5434 struct mlx5_ifc_modify_cong_params_in_bits {
5435 	u8         opcode[0x10];
5436 	u8         reserved_at_10[0x10];
5437 
5438 	u8         reserved_at_20[0x10];
5439 	u8         op_mod[0x10];
5440 
5441 	u8         reserved_at_40[0x1c];
5442 	u8         cong_protocol[0x4];
5443 
5444 	union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5445 
5446 	u8         reserved_at_80[0x80];
5447 
5448 	union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5449 };
5450 
5451 struct mlx5_ifc_manage_pages_out_bits {
5452 	u8         status[0x8];
5453 	u8         reserved_at_8[0x18];
5454 
5455 	u8         syndrome[0x20];
5456 
5457 	u8         output_num_entries[0x20];
5458 
5459 	u8         reserved_at_60[0x20];
5460 
5461 	u8         pas[0][0x40];
5462 };
5463 
5464 enum {
5465 	MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
5466 	MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
5467 	MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
5468 };
5469 
5470 struct mlx5_ifc_manage_pages_in_bits {
5471 	u8         opcode[0x10];
5472 	u8         reserved_at_10[0x10];
5473 
5474 	u8         reserved_at_20[0x10];
5475 	u8         op_mod[0x10];
5476 
5477 	u8         reserved_at_40[0x10];
5478 	u8         function_id[0x10];
5479 
5480 	u8         input_num_entries[0x20];
5481 
5482 	u8         pas[0][0x40];
5483 };
5484 
5485 struct mlx5_ifc_mad_ifc_out_bits {
5486 	u8         status[0x8];
5487 	u8         reserved_at_8[0x18];
5488 
5489 	u8         syndrome[0x20];
5490 
5491 	u8         reserved_at_40[0x40];
5492 
5493 	u8         response_mad_packet[256][0x8];
5494 };
5495 
5496 struct mlx5_ifc_mad_ifc_in_bits {
5497 	u8         opcode[0x10];
5498 	u8         reserved_at_10[0x10];
5499 
5500 	u8         reserved_at_20[0x10];
5501 	u8         op_mod[0x10];
5502 
5503 	u8         remote_lid[0x10];
5504 	u8         reserved_at_50[0x8];
5505 	u8         port[0x8];
5506 
5507 	u8         reserved_at_60[0x20];
5508 
5509 	u8         mad[256][0x8];
5510 };
5511 
5512 struct mlx5_ifc_init_hca_out_bits {
5513 	u8         status[0x8];
5514 	u8         reserved_at_8[0x18];
5515 
5516 	u8         syndrome[0x20];
5517 
5518 	u8         reserved_at_40[0x40];
5519 };
5520 
5521 struct mlx5_ifc_init_hca_in_bits {
5522 	u8         opcode[0x10];
5523 	u8         reserved_at_10[0x10];
5524 
5525 	u8         reserved_at_20[0x10];
5526 	u8         op_mod[0x10];
5527 
5528 	u8         reserved_at_40[0x40];
5529 };
5530 
5531 struct mlx5_ifc_init2rtr_qp_out_bits {
5532 	u8         status[0x8];
5533 	u8         reserved_at_8[0x18];
5534 
5535 	u8         syndrome[0x20];
5536 
5537 	u8         reserved_at_40[0x40];
5538 };
5539 
5540 struct mlx5_ifc_init2rtr_qp_in_bits {
5541 	u8         opcode[0x10];
5542 	u8         reserved_at_10[0x10];
5543 
5544 	u8         reserved_at_20[0x10];
5545 	u8         op_mod[0x10];
5546 
5547 	u8         reserved_at_40[0x8];
5548 	u8         qpn[0x18];
5549 
5550 	u8         reserved_at_60[0x20];
5551 
5552 	u8         opt_param_mask[0x20];
5553 
5554 	u8         reserved_at_a0[0x20];
5555 
5556 	struct mlx5_ifc_qpc_bits qpc;
5557 
5558 	u8         reserved_at_800[0x80];
5559 };
5560 
5561 struct mlx5_ifc_init2init_qp_out_bits {
5562 	u8         status[0x8];
5563 	u8         reserved_at_8[0x18];
5564 
5565 	u8         syndrome[0x20];
5566 
5567 	u8         reserved_at_40[0x40];
5568 };
5569 
5570 struct mlx5_ifc_init2init_qp_in_bits {
5571 	u8         opcode[0x10];
5572 	u8         reserved_at_10[0x10];
5573 
5574 	u8         reserved_at_20[0x10];
5575 	u8         op_mod[0x10];
5576 
5577 	u8         reserved_at_40[0x8];
5578 	u8         qpn[0x18];
5579 
5580 	u8         reserved_at_60[0x20];
5581 
5582 	u8         opt_param_mask[0x20];
5583 
5584 	u8         reserved_at_a0[0x20];
5585 
5586 	struct mlx5_ifc_qpc_bits qpc;
5587 
5588 	u8         reserved_at_800[0x80];
5589 };
5590 
5591 struct mlx5_ifc_get_dropped_packet_log_out_bits {
5592 	u8         status[0x8];
5593 	u8         reserved_at_8[0x18];
5594 
5595 	u8         syndrome[0x20];
5596 
5597 	u8         reserved_at_40[0x40];
5598 
5599 	u8         packet_headers_log[128][0x8];
5600 
5601 	u8         packet_syndrome[64][0x8];
5602 };
5603 
5604 struct mlx5_ifc_get_dropped_packet_log_in_bits {
5605 	u8         opcode[0x10];
5606 	u8         reserved_at_10[0x10];
5607 
5608 	u8         reserved_at_20[0x10];
5609 	u8         op_mod[0x10];
5610 
5611 	u8         reserved_at_40[0x40];
5612 };
5613 
5614 struct mlx5_ifc_gen_eqe_in_bits {
5615 	u8         opcode[0x10];
5616 	u8         reserved_at_10[0x10];
5617 
5618 	u8         reserved_at_20[0x10];
5619 	u8         op_mod[0x10];
5620 
5621 	u8         reserved_at_40[0x18];
5622 	u8         eq_number[0x8];
5623 
5624 	u8         reserved_at_60[0x20];
5625 
5626 	u8         eqe[64][0x8];
5627 };
5628 
5629 struct mlx5_ifc_gen_eq_out_bits {
5630 	u8         status[0x8];
5631 	u8         reserved_at_8[0x18];
5632 
5633 	u8         syndrome[0x20];
5634 
5635 	u8         reserved_at_40[0x40];
5636 };
5637 
5638 struct mlx5_ifc_enable_hca_out_bits {
5639 	u8         status[0x8];
5640 	u8         reserved_at_8[0x18];
5641 
5642 	u8         syndrome[0x20];
5643 
5644 	u8         reserved_at_40[0x20];
5645 };
5646 
5647 struct mlx5_ifc_enable_hca_in_bits {
5648 	u8         opcode[0x10];
5649 	u8         reserved_at_10[0x10];
5650 
5651 	u8         reserved_at_20[0x10];
5652 	u8         op_mod[0x10];
5653 
5654 	u8         reserved_at_40[0x10];
5655 	u8         function_id[0x10];
5656 
5657 	u8         reserved_at_60[0x20];
5658 };
5659 
5660 struct mlx5_ifc_drain_dct_out_bits {
5661 	u8         status[0x8];
5662 	u8         reserved_at_8[0x18];
5663 
5664 	u8         syndrome[0x20];
5665 
5666 	u8         reserved_at_40[0x40];
5667 };
5668 
5669 struct mlx5_ifc_drain_dct_in_bits {
5670 	u8         opcode[0x10];
5671 	u8         reserved_at_10[0x10];
5672 
5673 	u8         reserved_at_20[0x10];
5674 	u8         op_mod[0x10];
5675 
5676 	u8         reserved_at_40[0x8];
5677 	u8         dctn[0x18];
5678 
5679 	u8         reserved_at_60[0x20];
5680 };
5681 
5682 struct mlx5_ifc_disable_hca_out_bits {
5683 	u8         status[0x8];
5684 	u8         reserved_at_8[0x18];
5685 
5686 	u8         syndrome[0x20];
5687 
5688 	u8         reserved_at_40[0x20];
5689 };
5690 
5691 struct mlx5_ifc_disable_hca_in_bits {
5692 	u8         opcode[0x10];
5693 	u8         reserved_at_10[0x10];
5694 
5695 	u8         reserved_at_20[0x10];
5696 	u8         op_mod[0x10];
5697 
5698 	u8         reserved_at_40[0x10];
5699 	u8         function_id[0x10];
5700 
5701 	u8         reserved_at_60[0x20];
5702 };
5703 
5704 struct mlx5_ifc_detach_from_mcg_out_bits {
5705 	u8         status[0x8];
5706 	u8         reserved_at_8[0x18];
5707 
5708 	u8         syndrome[0x20];
5709 
5710 	u8         reserved_at_40[0x40];
5711 };
5712 
5713 struct mlx5_ifc_detach_from_mcg_in_bits {
5714 	u8         opcode[0x10];
5715 	u8         reserved_at_10[0x10];
5716 
5717 	u8         reserved_at_20[0x10];
5718 	u8         op_mod[0x10];
5719 
5720 	u8         reserved_at_40[0x8];
5721 	u8         qpn[0x18];
5722 
5723 	u8         reserved_at_60[0x20];
5724 
5725 	u8         multicast_gid[16][0x8];
5726 };
5727 
5728 struct mlx5_ifc_destroy_xrq_out_bits {
5729 	u8         status[0x8];
5730 	u8         reserved_at_8[0x18];
5731 
5732 	u8         syndrome[0x20];
5733 
5734 	u8         reserved_at_40[0x40];
5735 };
5736 
5737 struct mlx5_ifc_destroy_xrq_in_bits {
5738 	u8         opcode[0x10];
5739 	u8         reserved_at_10[0x10];
5740 
5741 	u8         reserved_at_20[0x10];
5742 	u8         op_mod[0x10];
5743 
5744 	u8         reserved_at_40[0x8];
5745 	u8         xrqn[0x18];
5746 
5747 	u8         reserved_at_60[0x20];
5748 };
5749 
5750 struct mlx5_ifc_destroy_xrc_srq_out_bits {
5751 	u8         status[0x8];
5752 	u8         reserved_at_8[0x18];
5753 
5754 	u8         syndrome[0x20];
5755 
5756 	u8         reserved_at_40[0x40];
5757 };
5758 
5759 struct mlx5_ifc_destroy_xrc_srq_in_bits {
5760 	u8         opcode[0x10];
5761 	u8         reserved_at_10[0x10];
5762 
5763 	u8         reserved_at_20[0x10];
5764 	u8         op_mod[0x10];
5765 
5766 	u8         reserved_at_40[0x8];
5767 	u8         xrc_srqn[0x18];
5768 
5769 	u8         reserved_at_60[0x20];
5770 };
5771 
5772 struct mlx5_ifc_destroy_tis_out_bits {
5773 	u8         status[0x8];
5774 	u8         reserved_at_8[0x18];
5775 
5776 	u8         syndrome[0x20];
5777 
5778 	u8         reserved_at_40[0x40];
5779 };
5780 
5781 struct mlx5_ifc_destroy_tis_in_bits {
5782 	u8         opcode[0x10];
5783 	u8         reserved_at_10[0x10];
5784 
5785 	u8         reserved_at_20[0x10];
5786 	u8         op_mod[0x10];
5787 
5788 	u8         reserved_at_40[0x8];
5789 	u8         tisn[0x18];
5790 
5791 	u8         reserved_at_60[0x20];
5792 };
5793 
5794 struct mlx5_ifc_destroy_tir_out_bits {
5795 	u8         status[0x8];
5796 	u8         reserved_at_8[0x18];
5797 
5798 	u8         syndrome[0x20];
5799 
5800 	u8         reserved_at_40[0x40];
5801 };
5802 
5803 struct mlx5_ifc_destroy_tir_in_bits {
5804 	u8         opcode[0x10];
5805 	u8         reserved_at_10[0x10];
5806 
5807 	u8         reserved_at_20[0x10];
5808 	u8         op_mod[0x10];
5809 
5810 	u8         reserved_at_40[0x8];
5811 	u8         tirn[0x18];
5812 
5813 	u8         reserved_at_60[0x20];
5814 };
5815 
5816 struct mlx5_ifc_destroy_srq_out_bits {
5817 	u8         status[0x8];
5818 	u8         reserved_at_8[0x18];
5819 
5820 	u8         syndrome[0x20];
5821 
5822 	u8         reserved_at_40[0x40];
5823 };
5824 
5825 struct mlx5_ifc_destroy_srq_in_bits {
5826 	u8         opcode[0x10];
5827 	u8         reserved_at_10[0x10];
5828 
5829 	u8         reserved_at_20[0x10];
5830 	u8         op_mod[0x10];
5831 
5832 	u8         reserved_at_40[0x8];
5833 	u8         srqn[0x18];
5834 
5835 	u8         reserved_at_60[0x20];
5836 };
5837 
5838 struct mlx5_ifc_destroy_sq_out_bits {
5839 	u8         status[0x8];
5840 	u8         reserved_at_8[0x18];
5841 
5842 	u8         syndrome[0x20];
5843 
5844 	u8         reserved_at_40[0x40];
5845 };
5846 
5847 struct mlx5_ifc_destroy_sq_in_bits {
5848 	u8         opcode[0x10];
5849 	u8         reserved_at_10[0x10];
5850 
5851 	u8         reserved_at_20[0x10];
5852 	u8         op_mod[0x10];
5853 
5854 	u8         reserved_at_40[0x8];
5855 	u8         sqn[0x18];
5856 
5857 	u8         reserved_at_60[0x20];
5858 };
5859 
5860 struct mlx5_ifc_destroy_scheduling_element_out_bits {
5861 	u8         status[0x8];
5862 	u8         reserved_at_8[0x18];
5863 
5864 	u8         syndrome[0x20];
5865 
5866 	u8         reserved_at_40[0x1c0];
5867 };
5868 
5869 struct mlx5_ifc_destroy_scheduling_element_in_bits {
5870 	u8         opcode[0x10];
5871 	u8         reserved_at_10[0x10];
5872 
5873 	u8         reserved_at_20[0x10];
5874 	u8         op_mod[0x10];
5875 
5876 	u8         scheduling_hierarchy[0x8];
5877 	u8         reserved_at_48[0x18];
5878 
5879 	u8         scheduling_element_id[0x20];
5880 
5881 	u8         reserved_at_80[0x180];
5882 };
5883 
5884 struct mlx5_ifc_destroy_rqt_out_bits {
5885 	u8         status[0x8];
5886 	u8         reserved_at_8[0x18];
5887 
5888 	u8         syndrome[0x20];
5889 
5890 	u8         reserved_at_40[0x40];
5891 };
5892 
5893 struct mlx5_ifc_destroy_rqt_in_bits {
5894 	u8         opcode[0x10];
5895 	u8         reserved_at_10[0x10];
5896 
5897 	u8         reserved_at_20[0x10];
5898 	u8         op_mod[0x10];
5899 
5900 	u8         reserved_at_40[0x8];
5901 	u8         rqtn[0x18];
5902 
5903 	u8         reserved_at_60[0x20];
5904 };
5905 
5906 struct mlx5_ifc_destroy_rq_out_bits {
5907 	u8         status[0x8];
5908 	u8         reserved_at_8[0x18];
5909 
5910 	u8         syndrome[0x20];
5911 
5912 	u8         reserved_at_40[0x40];
5913 };
5914 
5915 struct mlx5_ifc_destroy_rq_in_bits {
5916 	u8         opcode[0x10];
5917 	u8         reserved_at_10[0x10];
5918 
5919 	u8         reserved_at_20[0x10];
5920 	u8         op_mod[0x10];
5921 
5922 	u8         reserved_at_40[0x8];
5923 	u8         rqn[0x18];
5924 
5925 	u8         reserved_at_60[0x20];
5926 };
5927 
5928 struct mlx5_ifc_set_delay_drop_params_in_bits {
5929 	u8         opcode[0x10];
5930 	u8         reserved_at_10[0x10];
5931 
5932 	u8         reserved_at_20[0x10];
5933 	u8         op_mod[0x10];
5934 
5935 	u8         reserved_at_40[0x20];
5936 
5937 	u8         reserved_at_60[0x10];
5938 	u8         delay_drop_timeout[0x10];
5939 };
5940 
5941 struct mlx5_ifc_set_delay_drop_params_out_bits {
5942 	u8         status[0x8];
5943 	u8         reserved_at_8[0x18];
5944 
5945 	u8         syndrome[0x20];
5946 
5947 	u8         reserved_at_40[0x40];
5948 };
5949 
5950 struct mlx5_ifc_destroy_rmp_out_bits {
5951 	u8         status[0x8];
5952 	u8         reserved_at_8[0x18];
5953 
5954 	u8         syndrome[0x20];
5955 
5956 	u8         reserved_at_40[0x40];
5957 };
5958 
5959 struct mlx5_ifc_destroy_rmp_in_bits {
5960 	u8         opcode[0x10];
5961 	u8         reserved_at_10[0x10];
5962 
5963 	u8         reserved_at_20[0x10];
5964 	u8         op_mod[0x10];
5965 
5966 	u8         reserved_at_40[0x8];
5967 	u8         rmpn[0x18];
5968 
5969 	u8         reserved_at_60[0x20];
5970 };
5971 
5972 struct mlx5_ifc_destroy_qp_out_bits {
5973 	u8         status[0x8];
5974 	u8         reserved_at_8[0x18];
5975 
5976 	u8         syndrome[0x20];
5977 
5978 	u8         reserved_at_40[0x40];
5979 };
5980 
5981 struct mlx5_ifc_destroy_qp_in_bits {
5982 	u8         opcode[0x10];
5983 	u8         reserved_at_10[0x10];
5984 
5985 	u8         reserved_at_20[0x10];
5986 	u8         op_mod[0x10];
5987 
5988 	u8         reserved_at_40[0x8];
5989 	u8         qpn[0x18];
5990 
5991 	u8         reserved_at_60[0x20];
5992 };
5993 
5994 struct mlx5_ifc_destroy_psv_out_bits {
5995 	u8         status[0x8];
5996 	u8         reserved_at_8[0x18];
5997 
5998 	u8         syndrome[0x20];
5999 
6000 	u8         reserved_at_40[0x40];
6001 };
6002 
6003 struct mlx5_ifc_destroy_psv_in_bits {
6004 	u8         opcode[0x10];
6005 	u8         reserved_at_10[0x10];
6006 
6007 	u8         reserved_at_20[0x10];
6008 	u8         op_mod[0x10];
6009 
6010 	u8         reserved_at_40[0x8];
6011 	u8         psvn[0x18];
6012 
6013 	u8         reserved_at_60[0x20];
6014 };
6015 
6016 struct mlx5_ifc_destroy_mkey_out_bits {
6017 	u8         status[0x8];
6018 	u8         reserved_at_8[0x18];
6019 
6020 	u8         syndrome[0x20];
6021 
6022 	u8         reserved_at_40[0x40];
6023 };
6024 
6025 struct mlx5_ifc_destroy_mkey_in_bits {
6026 	u8         opcode[0x10];
6027 	u8         reserved_at_10[0x10];
6028 
6029 	u8         reserved_at_20[0x10];
6030 	u8         op_mod[0x10];
6031 
6032 	u8         reserved_at_40[0x8];
6033 	u8         mkey_index[0x18];
6034 
6035 	u8         reserved_at_60[0x20];
6036 };
6037 
6038 struct mlx5_ifc_destroy_flow_table_out_bits {
6039 	u8         status[0x8];
6040 	u8         reserved_at_8[0x18];
6041 
6042 	u8         syndrome[0x20];
6043 
6044 	u8         reserved_at_40[0x40];
6045 };
6046 
6047 struct mlx5_ifc_destroy_flow_table_in_bits {
6048 	u8         opcode[0x10];
6049 	u8         reserved_at_10[0x10];
6050 
6051 	u8         reserved_at_20[0x10];
6052 	u8         op_mod[0x10];
6053 
6054 	u8         other_vport[0x1];
6055 	u8         reserved_at_41[0xf];
6056 	u8         vport_number[0x10];
6057 
6058 	u8         reserved_at_60[0x20];
6059 
6060 	u8         table_type[0x8];
6061 	u8         reserved_at_88[0x18];
6062 
6063 	u8         reserved_at_a0[0x8];
6064 	u8         table_id[0x18];
6065 
6066 	u8         reserved_at_c0[0x140];
6067 };
6068 
6069 struct mlx5_ifc_destroy_flow_group_out_bits {
6070 	u8         status[0x8];
6071 	u8         reserved_at_8[0x18];
6072 
6073 	u8         syndrome[0x20];
6074 
6075 	u8         reserved_at_40[0x40];
6076 };
6077 
6078 struct mlx5_ifc_destroy_flow_group_in_bits {
6079 	u8         opcode[0x10];
6080 	u8         reserved_at_10[0x10];
6081 
6082 	u8         reserved_at_20[0x10];
6083 	u8         op_mod[0x10];
6084 
6085 	u8         other_vport[0x1];
6086 	u8         reserved_at_41[0xf];
6087 	u8         vport_number[0x10];
6088 
6089 	u8         reserved_at_60[0x20];
6090 
6091 	u8         table_type[0x8];
6092 	u8         reserved_at_88[0x18];
6093 
6094 	u8         reserved_at_a0[0x8];
6095 	u8         table_id[0x18];
6096 
6097 	u8         group_id[0x20];
6098 
6099 	u8         reserved_at_e0[0x120];
6100 };
6101 
6102 struct mlx5_ifc_destroy_eq_out_bits {
6103 	u8         status[0x8];
6104 	u8         reserved_at_8[0x18];
6105 
6106 	u8         syndrome[0x20];
6107 
6108 	u8         reserved_at_40[0x40];
6109 };
6110 
6111 struct mlx5_ifc_destroy_eq_in_bits {
6112 	u8         opcode[0x10];
6113 	u8         reserved_at_10[0x10];
6114 
6115 	u8         reserved_at_20[0x10];
6116 	u8         op_mod[0x10];
6117 
6118 	u8         reserved_at_40[0x18];
6119 	u8         eq_number[0x8];
6120 
6121 	u8         reserved_at_60[0x20];
6122 };
6123 
6124 struct mlx5_ifc_destroy_dct_out_bits {
6125 	u8         status[0x8];
6126 	u8         reserved_at_8[0x18];
6127 
6128 	u8         syndrome[0x20];
6129 
6130 	u8         reserved_at_40[0x40];
6131 };
6132 
6133 struct mlx5_ifc_destroy_dct_in_bits {
6134 	u8         opcode[0x10];
6135 	u8         reserved_at_10[0x10];
6136 
6137 	u8         reserved_at_20[0x10];
6138 	u8         op_mod[0x10];
6139 
6140 	u8         reserved_at_40[0x8];
6141 	u8         dctn[0x18];
6142 
6143 	u8         reserved_at_60[0x20];
6144 };
6145 
6146 struct mlx5_ifc_destroy_cq_out_bits {
6147 	u8         status[0x8];
6148 	u8         reserved_at_8[0x18];
6149 
6150 	u8         syndrome[0x20];
6151 
6152 	u8         reserved_at_40[0x40];
6153 };
6154 
6155 struct mlx5_ifc_destroy_cq_in_bits {
6156 	u8         opcode[0x10];
6157 	u8         reserved_at_10[0x10];
6158 
6159 	u8         reserved_at_20[0x10];
6160 	u8         op_mod[0x10];
6161 
6162 	u8         reserved_at_40[0x8];
6163 	u8         cqn[0x18];
6164 
6165 	u8         reserved_at_60[0x20];
6166 };
6167 
6168 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
6169 	u8         status[0x8];
6170 	u8         reserved_at_8[0x18];
6171 
6172 	u8         syndrome[0x20];
6173 
6174 	u8         reserved_at_40[0x40];
6175 };
6176 
6177 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
6178 	u8         opcode[0x10];
6179 	u8         reserved_at_10[0x10];
6180 
6181 	u8         reserved_at_20[0x10];
6182 	u8         op_mod[0x10];
6183 
6184 	u8         reserved_at_40[0x20];
6185 
6186 	u8         reserved_at_60[0x10];
6187 	u8         vxlan_udp_port[0x10];
6188 };
6189 
6190 struct mlx5_ifc_delete_l2_table_entry_out_bits {
6191 	u8         status[0x8];
6192 	u8         reserved_at_8[0x18];
6193 
6194 	u8         syndrome[0x20];
6195 
6196 	u8         reserved_at_40[0x40];
6197 };
6198 
6199 struct mlx5_ifc_delete_l2_table_entry_in_bits {
6200 	u8         opcode[0x10];
6201 	u8         reserved_at_10[0x10];
6202 
6203 	u8         reserved_at_20[0x10];
6204 	u8         op_mod[0x10];
6205 
6206 	u8         reserved_at_40[0x60];
6207 
6208 	u8         reserved_at_a0[0x8];
6209 	u8         table_index[0x18];
6210 
6211 	u8         reserved_at_c0[0x140];
6212 };
6213 
6214 struct mlx5_ifc_delete_fte_out_bits {
6215 	u8         status[0x8];
6216 	u8         reserved_at_8[0x18];
6217 
6218 	u8         syndrome[0x20];
6219 
6220 	u8         reserved_at_40[0x40];
6221 };
6222 
6223 struct mlx5_ifc_delete_fte_in_bits {
6224 	u8         opcode[0x10];
6225 	u8         reserved_at_10[0x10];
6226 
6227 	u8         reserved_at_20[0x10];
6228 	u8         op_mod[0x10];
6229 
6230 	u8         other_vport[0x1];
6231 	u8         reserved_at_41[0xf];
6232 	u8         vport_number[0x10];
6233 
6234 	u8         reserved_at_60[0x20];
6235 
6236 	u8         table_type[0x8];
6237 	u8         reserved_at_88[0x18];
6238 
6239 	u8         reserved_at_a0[0x8];
6240 	u8         table_id[0x18];
6241 
6242 	u8         reserved_at_c0[0x40];
6243 
6244 	u8         flow_index[0x20];
6245 
6246 	u8         reserved_at_120[0xe0];
6247 };
6248 
6249 struct mlx5_ifc_dealloc_xrcd_out_bits {
6250 	u8         status[0x8];
6251 	u8         reserved_at_8[0x18];
6252 
6253 	u8         syndrome[0x20];
6254 
6255 	u8         reserved_at_40[0x40];
6256 };
6257 
6258 struct mlx5_ifc_dealloc_xrcd_in_bits {
6259 	u8         opcode[0x10];
6260 	u8         reserved_at_10[0x10];
6261 
6262 	u8         reserved_at_20[0x10];
6263 	u8         op_mod[0x10];
6264 
6265 	u8         reserved_at_40[0x8];
6266 	u8         xrcd[0x18];
6267 
6268 	u8         reserved_at_60[0x20];
6269 };
6270 
6271 struct mlx5_ifc_dealloc_uar_out_bits {
6272 	u8         status[0x8];
6273 	u8         reserved_at_8[0x18];
6274 
6275 	u8         syndrome[0x20];
6276 
6277 	u8         reserved_at_40[0x40];
6278 };
6279 
6280 struct mlx5_ifc_dealloc_uar_in_bits {
6281 	u8         opcode[0x10];
6282 	u8         reserved_at_10[0x10];
6283 
6284 	u8         reserved_at_20[0x10];
6285 	u8         op_mod[0x10];
6286 
6287 	u8         reserved_at_40[0x8];
6288 	u8         uar[0x18];
6289 
6290 	u8         reserved_at_60[0x20];
6291 };
6292 
6293 struct mlx5_ifc_dealloc_transport_domain_out_bits {
6294 	u8         status[0x8];
6295 	u8         reserved_at_8[0x18];
6296 
6297 	u8         syndrome[0x20];
6298 
6299 	u8         reserved_at_40[0x40];
6300 };
6301 
6302 struct mlx5_ifc_dealloc_transport_domain_in_bits {
6303 	u8         opcode[0x10];
6304 	u8         reserved_at_10[0x10];
6305 
6306 	u8         reserved_at_20[0x10];
6307 	u8         op_mod[0x10];
6308 
6309 	u8         reserved_at_40[0x8];
6310 	u8         transport_domain[0x18];
6311 
6312 	u8         reserved_at_60[0x20];
6313 };
6314 
6315 struct mlx5_ifc_dealloc_q_counter_out_bits {
6316 	u8         status[0x8];
6317 	u8         reserved_at_8[0x18];
6318 
6319 	u8         syndrome[0x20];
6320 
6321 	u8         reserved_at_40[0x40];
6322 };
6323 
6324 struct mlx5_ifc_dealloc_q_counter_in_bits {
6325 	u8         opcode[0x10];
6326 	u8         reserved_at_10[0x10];
6327 
6328 	u8         reserved_at_20[0x10];
6329 	u8         op_mod[0x10];
6330 
6331 	u8         reserved_at_40[0x18];
6332 	u8         counter_set_id[0x8];
6333 
6334 	u8         reserved_at_60[0x20];
6335 };
6336 
6337 struct mlx5_ifc_dealloc_pd_out_bits {
6338 	u8         status[0x8];
6339 	u8         reserved_at_8[0x18];
6340 
6341 	u8         syndrome[0x20];
6342 
6343 	u8         reserved_at_40[0x40];
6344 };
6345 
6346 struct mlx5_ifc_dealloc_pd_in_bits {
6347 	u8         opcode[0x10];
6348 	u8         reserved_at_10[0x10];
6349 
6350 	u8         reserved_at_20[0x10];
6351 	u8         op_mod[0x10];
6352 
6353 	u8         reserved_at_40[0x8];
6354 	u8         pd[0x18];
6355 
6356 	u8         reserved_at_60[0x20];
6357 };
6358 
6359 struct mlx5_ifc_dealloc_flow_counter_out_bits {
6360 	u8         status[0x8];
6361 	u8         reserved_at_8[0x18];
6362 
6363 	u8         syndrome[0x20];
6364 
6365 	u8         reserved_at_40[0x40];
6366 };
6367 
6368 struct mlx5_ifc_dealloc_flow_counter_in_bits {
6369 	u8         opcode[0x10];
6370 	u8         reserved_at_10[0x10];
6371 
6372 	u8         reserved_at_20[0x10];
6373 	u8         op_mod[0x10];
6374 
6375 	u8         flow_counter_id[0x20];
6376 
6377 	u8         reserved_at_60[0x20];
6378 };
6379 
6380 struct mlx5_ifc_create_xrq_out_bits {
6381 	u8         status[0x8];
6382 	u8         reserved_at_8[0x18];
6383 
6384 	u8         syndrome[0x20];
6385 
6386 	u8         reserved_at_40[0x8];
6387 	u8         xrqn[0x18];
6388 
6389 	u8         reserved_at_60[0x20];
6390 };
6391 
6392 struct mlx5_ifc_create_xrq_in_bits {
6393 	u8         opcode[0x10];
6394 	u8         reserved_at_10[0x10];
6395 
6396 	u8         reserved_at_20[0x10];
6397 	u8         op_mod[0x10];
6398 
6399 	u8         reserved_at_40[0x40];
6400 
6401 	struct mlx5_ifc_xrqc_bits xrq_context;
6402 };
6403 
6404 struct mlx5_ifc_create_xrc_srq_out_bits {
6405 	u8         status[0x8];
6406 	u8         reserved_at_8[0x18];
6407 
6408 	u8         syndrome[0x20];
6409 
6410 	u8         reserved_at_40[0x8];
6411 	u8         xrc_srqn[0x18];
6412 
6413 	u8         reserved_at_60[0x20];
6414 };
6415 
6416 struct mlx5_ifc_create_xrc_srq_in_bits {
6417 	u8         opcode[0x10];
6418 	u8         reserved_at_10[0x10];
6419 
6420 	u8         reserved_at_20[0x10];
6421 	u8         op_mod[0x10];
6422 
6423 	u8         reserved_at_40[0x40];
6424 
6425 	struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6426 
6427 	u8         reserved_at_280[0x600];
6428 
6429 	u8         pas[0][0x40];
6430 };
6431 
6432 struct mlx5_ifc_create_tis_out_bits {
6433 	u8         status[0x8];
6434 	u8         reserved_at_8[0x18];
6435 
6436 	u8         syndrome[0x20];
6437 
6438 	u8         reserved_at_40[0x8];
6439 	u8         tisn[0x18];
6440 
6441 	u8         reserved_at_60[0x20];
6442 };
6443 
6444 struct mlx5_ifc_create_tis_in_bits {
6445 	u8         opcode[0x10];
6446 	u8         reserved_at_10[0x10];
6447 
6448 	u8         reserved_at_20[0x10];
6449 	u8         op_mod[0x10];
6450 
6451 	u8         reserved_at_40[0xc0];
6452 
6453 	struct mlx5_ifc_tisc_bits ctx;
6454 };
6455 
6456 struct mlx5_ifc_create_tir_out_bits {
6457 	u8         status[0x8];
6458 	u8         reserved_at_8[0x18];
6459 
6460 	u8         syndrome[0x20];
6461 
6462 	u8         reserved_at_40[0x8];
6463 	u8         tirn[0x18];
6464 
6465 	u8         reserved_at_60[0x20];
6466 };
6467 
6468 struct mlx5_ifc_create_tir_in_bits {
6469 	u8         opcode[0x10];
6470 	u8         reserved_at_10[0x10];
6471 
6472 	u8         reserved_at_20[0x10];
6473 	u8         op_mod[0x10];
6474 
6475 	u8         reserved_at_40[0xc0];
6476 
6477 	struct mlx5_ifc_tirc_bits ctx;
6478 };
6479 
6480 struct mlx5_ifc_create_srq_out_bits {
6481 	u8         status[0x8];
6482 	u8         reserved_at_8[0x18];
6483 
6484 	u8         syndrome[0x20];
6485 
6486 	u8         reserved_at_40[0x8];
6487 	u8         srqn[0x18];
6488 
6489 	u8         reserved_at_60[0x20];
6490 };
6491 
6492 struct mlx5_ifc_create_srq_in_bits {
6493 	u8         opcode[0x10];
6494 	u8         reserved_at_10[0x10];
6495 
6496 	u8         reserved_at_20[0x10];
6497 	u8         op_mod[0x10];
6498 
6499 	u8         reserved_at_40[0x40];
6500 
6501 	struct mlx5_ifc_srqc_bits srq_context_entry;
6502 
6503 	u8         reserved_at_280[0x600];
6504 
6505 	u8         pas[0][0x40];
6506 };
6507 
6508 struct mlx5_ifc_create_sq_out_bits {
6509 	u8         status[0x8];
6510 	u8         reserved_at_8[0x18];
6511 
6512 	u8         syndrome[0x20];
6513 
6514 	u8         reserved_at_40[0x8];
6515 	u8         sqn[0x18];
6516 
6517 	u8         reserved_at_60[0x20];
6518 };
6519 
6520 struct mlx5_ifc_create_sq_in_bits {
6521 	u8         opcode[0x10];
6522 	u8         reserved_at_10[0x10];
6523 
6524 	u8         reserved_at_20[0x10];
6525 	u8         op_mod[0x10];
6526 
6527 	u8         reserved_at_40[0xc0];
6528 
6529 	struct mlx5_ifc_sqc_bits ctx;
6530 };
6531 
6532 struct mlx5_ifc_create_scheduling_element_out_bits {
6533 	u8         status[0x8];
6534 	u8         reserved_at_8[0x18];
6535 
6536 	u8         syndrome[0x20];
6537 
6538 	u8         reserved_at_40[0x40];
6539 
6540 	u8         scheduling_element_id[0x20];
6541 
6542 	u8         reserved_at_a0[0x160];
6543 };
6544 
6545 struct mlx5_ifc_create_scheduling_element_in_bits {
6546 	u8         opcode[0x10];
6547 	u8         reserved_at_10[0x10];
6548 
6549 	u8         reserved_at_20[0x10];
6550 	u8         op_mod[0x10];
6551 
6552 	u8         scheduling_hierarchy[0x8];
6553 	u8         reserved_at_48[0x18];
6554 
6555 	u8         reserved_at_60[0xa0];
6556 
6557 	struct mlx5_ifc_scheduling_context_bits scheduling_context;
6558 
6559 	u8         reserved_at_300[0x100];
6560 };
6561 
6562 struct mlx5_ifc_create_rqt_out_bits {
6563 	u8         status[0x8];
6564 	u8         reserved_at_8[0x18];
6565 
6566 	u8         syndrome[0x20];
6567 
6568 	u8         reserved_at_40[0x8];
6569 	u8         rqtn[0x18];
6570 
6571 	u8         reserved_at_60[0x20];
6572 };
6573 
6574 struct mlx5_ifc_create_rqt_in_bits {
6575 	u8         opcode[0x10];
6576 	u8         reserved_at_10[0x10];
6577 
6578 	u8         reserved_at_20[0x10];
6579 	u8         op_mod[0x10];
6580 
6581 	u8         reserved_at_40[0xc0];
6582 
6583 	struct mlx5_ifc_rqtc_bits rqt_context;
6584 };
6585 
6586 struct mlx5_ifc_create_rq_out_bits {
6587 	u8         status[0x8];
6588 	u8         reserved_at_8[0x18];
6589 
6590 	u8         syndrome[0x20];
6591 
6592 	u8         reserved_at_40[0x8];
6593 	u8         rqn[0x18];
6594 
6595 	u8         reserved_at_60[0x20];
6596 };
6597 
6598 struct mlx5_ifc_create_rq_in_bits {
6599 	u8         opcode[0x10];
6600 	u8         reserved_at_10[0x10];
6601 
6602 	u8         reserved_at_20[0x10];
6603 	u8         op_mod[0x10];
6604 
6605 	u8         reserved_at_40[0xc0];
6606 
6607 	struct mlx5_ifc_rqc_bits ctx;
6608 };
6609 
6610 struct mlx5_ifc_create_rmp_out_bits {
6611 	u8         status[0x8];
6612 	u8         reserved_at_8[0x18];
6613 
6614 	u8         syndrome[0x20];
6615 
6616 	u8         reserved_at_40[0x8];
6617 	u8         rmpn[0x18];
6618 
6619 	u8         reserved_at_60[0x20];
6620 };
6621 
6622 struct mlx5_ifc_create_rmp_in_bits {
6623 	u8         opcode[0x10];
6624 	u8         reserved_at_10[0x10];
6625 
6626 	u8         reserved_at_20[0x10];
6627 	u8         op_mod[0x10];
6628 
6629 	u8         reserved_at_40[0xc0];
6630 
6631 	struct mlx5_ifc_rmpc_bits ctx;
6632 };
6633 
6634 struct mlx5_ifc_create_qp_out_bits {
6635 	u8         status[0x8];
6636 	u8         reserved_at_8[0x18];
6637 
6638 	u8         syndrome[0x20];
6639 
6640 	u8         reserved_at_40[0x8];
6641 	u8         qpn[0x18];
6642 
6643 	u8         reserved_at_60[0x20];
6644 };
6645 
6646 struct mlx5_ifc_create_qp_in_bits {
6647 	u8         opcode[0x10];
6648 	u8         reserved_at_10[0x10];
6649 
6650 	u8         reserved_at_20[0x10];
6651 	u8         op_mod[0x10];
6652 
6653 	u8         reserved_at_40[0x40];
6654 
6655 	u8         opt_param_mask[0x20];
6656 
6657 	u8         reserved_at_a0[0x20];
6658 
6659 	struct mlx5_ifc_qpc_bits qpc;
6660 
6661 	u8         reserved_at_800[0x80];
6662 
6663 	u8         pas[0][0x40];
6664 };
6665 
6666 struct mlx5_ifc_create_psv_out_bits {
6667 	u8         status[0x8];
6668 	u8         reserved_at_8[0x18];
6669 
6670 	u8         syndrome[0x20];
6671 
6672 	u8         reserved_at_40[0x40];
6673 
6674 	u8         reserved_at_80[0x8];
6675 	u8         psv0_index[0x18];
6676 
6677 	u8         reserved_at_a0[0x8];
6678 	u8         psv1_index[0x18];
6679 
6680 	u8         reserved_at_c0[0x8];
6681 	u8         psv2_index[0x18];
6682 
6683 	u8         reserved_at_e0[0x8];
6684 	u8         psv3_index[0x18];
6685 };
6686 
6687 struct mlx5_ifc_create_psv_in_bits {
6688 	u8         opcode[0x10];
6689 	u8         reserved_at_10[0x10];
6690 
6691 	u8         reserved_at_20[0x10];
6692 	u8         op_mod[0x10];
6693 
6694 	u8         num_psv[0x4];
6695 	u8         reserved_at_44[0x4];
6696 	u8         pd[0x18];
6697 
6698 	u8         reserved_at_60[0x20];
6699 };
6700 
6701 struct mlx5_ifc_create_mkey_out_bits {
6702 	u8         status[0x8];
6703 	u8         reserved_at_8[0x18];
6704 
6705 	u8         syndrome[0x20];
6706 
6707 	u8         reserved_at_40[0x8];
6708 	u8         mkey_index[0x18];
6709 
6710 	u8         reserved_at_60[0x20];
6711 };
6712 
6713 struct mlx5_ifc_create_mkey_in_bits {
6714 	u8         opcode[0x10];
6715 	u8         reserved_at_10[0x10];
6716 
6717 	u8         reserved_at_20[0x10];
6718 	u8         op_mod[0x10];
6719 
6720 	u8         reserved_at_40[0x20];
6721 
6722 	u8         pg_access[0x1];
6723 	u8         reserved_at_61[0x1f];
6724 
6725 	struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6726 
6727 	u8         reserved_at_280[0x80];
6728 
6729 	u8         translations_octword_actual_size[0x20];
6730 
6731 	u8         reserved_at_320[0x560];
6732 
6733 	u8         klm_pas_mtt[0][0x20];
6734 };
6735 
6736 struct mlx5_ifc_create_flow_table_out_bits {
6737 	u8         status[0x8];
6738 	u8         reserved_at_8[0x18];
6739 
6740 	u8         syndrome[0x20];
6741 
6742 	u8         reserved_at_40[0x8];
6743 	u8         table_id[0x18];
6744 
6745 	u8         reserved_at_60[0x20];
6746 };
6747 
6748 struct mlx5_ifc_flow_table_context_bits {
6749 	u8         encap_en[0x1];
6750 	u8         decap_en[0x1];
6751 	u8         reserved_at_2[0x2];
6752 	u8         table_miss_action[0x4];
6753 	u8         level[0x8];
6754 	u8         reserved_at_10[0x8];
6755 	u8         log_size[0x8];
6756 
6757 	u8         reserved_at_20[0x8];
6758 	u8         table_miss_id[0x18];
6759 
6760 	u8         reserved_at_40[0x8];
6761 	u8         lag_master_next_table_id[0x18];
6762 
6763 	u8         reserved_at_60[0xe0];
6764 };
6765 
6766 struct mlx5_ifc_create_flow_table_in_bits {
6767 	u8         opcode[0x10];
6768 	u8         reserved_at_10[0x10];
6769 
6770 	u8         reserved_at_20[0x10];
6771 	u8         op_mod[0x10];
6772 
6773 	u8         other_vport[0x1];
6774 	u8         reserved_at_41[0xf];
6775 	u8         vport_number[0x10];
6776 
6777 	u8         reserved_at_60[0x20];
6778 
6779 	u8         table_type[0x8];
6780 	u8         reserved_at_88[0x18];
6781 
6782 	u8         reserved_at_a0[0x20];
6783 
6784 	struct mlx5_ifc_flow_table_context_bits flow_table_context;
6785 };
6786 
6787 struct mlx5_ifc_create_flow_group_out_bits {
6788 	u8         status[0x8];
6789 	u8         reserved_at_8[0x18];
6790 
6791 	u8         syndrome[0x20];
6792 
6793 	u8         reserved_at_40[0x8];
6794 	u8         group_id[0x18];
6795 
6796 	u8         reserved_at_60[0x20];
6797 };
6798 
6799 enum {
6800 	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
6801 	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
6802 	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
6803 };
6804 
6805 struct mlx5_ifc_create_flow_group_in_bits {
6806 	u8         opcode[0x10];
6807 	u8         reserved_at_10[0x10];
6808 
6809 	u8         reserved_at_20[0x10];
6810 	u8         op_mod[0x10];
6811 
6812 	u8         other_vport[0x1];
6813 	u8         reserved_at_41[0xf];
6814 	u8         vport_number[0x10];
6815 
6816 	u8         reserved_at_60[0x20];
6817 
6818 	u8         table_type[0x8];
6819 	u8         reserved_at_88[0x18];
6820 
6821 	u8         reserved_at_a0[0x8];
6822 	u8         table_id[0x18];
6823 
6824 	u8         reserved_at_c0[0x20];
6825 
6826 	u8         start_flow_index[0x20];
6827 
6828 	u8         reserved_at_100[0x20];
6829 
6830 	u8         end_flow_index[0x20];
6831 
6832 	u8         reserved_at_140[0xa0];
6833 
6834 	u8         reserved_at_1e0[0x18];
6835 	u8         match_criteria_enable[0x8];
6836 
6837 	struct mlx5_ifc_fte_match_param_bits match_criteria;
6838 
6839 	u8         reserved_at_1200[0xe00];
6840 };
6841 
6842 struct mlx5_ifc_create_eq_out_bits {
6843 	u8         status[0x8];
6844 	u8         reserved_at_8[0x18];
6845 
6846 	u8         syndrome[0x20];
6847 
6848 	u8         reserved_at_40[0x18];
6849 	u8         eq_number[0x8];
6850 
6851 	u8         reserved_at_60[0x20];
6852 };
6853 
6854 struct mlx5_ifc_create_eq_in_bits {
6855 	u8         opcode[0x10];
6856 	u8         reserved_at_10[0x10];
6857 
6858 	u8         reserved_at_20[0x10];
6859 	u8         op_mod[0x10];
6860 
6861 	u8         reserved_at_40[0x40];
6862 
6863 	struct mlx5_ifc_eqc_bits eq_context_entry;
6864 
6865 	u8         reserved_at_280[0x40];
6866 
6867 	u8         event_bitmask[0x40];
6868 
6869 	u8         reserved_at_300[0x580];
6870 
6871 	u8         pas[0][0x40];
6872 };
6873 
6874 struct mlx5_ifc_create_dct_out_bits {
6875 	u8         status[0x8];
6876 	u8         reserved_at_8[0x18];
6877 
6878 	u8         syndrome[0x20];
6879 
6880 	u8         reserved_at_40[0x8];
6881 	u8         dctn[0x18];
6882 
6883 	u8         reserved_at_60[0x20];
6884 };
6885 
6886 struct mlx5_ifc_create_dct_in_bits {
6887 	u8         opcode[0x10];
6888 	u8         reserved_at_10[0x10];
6889 
6890 	u8         reserved_at_20[0x10];
6891 	u8         op_mod[0x10];
6892 
6893 	u8         reserved_at_40[0x40];
6894 
6895 	struct mlx5_ifc_dctc_bits dct_context_entry;
6896 
6897 	u8         reserved_at_280[0x180];
6898 };
6899 
6900 struct mlx5_ifc_create_cq_out_bits {
6901 	u8         status[0x8];
6902 	u8         reserved_at_8[0x18];
6903 
6904 	u8         syndrome[0x20];
6905 
6906 	u8         reserved_at_40[0x8];
6907 	u8         cqn[0x18];
6908 
6909 	u8         reserved_at_60[0x20];
6910 };
6911 
6912 struct mlx5_ifc_create_cq_in_bits {
6913 	u8         opcode[0x10];
6914 	u8         reserved_at_10[0x10];
6915 
6916 	u8         reserved_at_20[0x10];
6917 	u8         op_mod[0x10];
6918 
6919 	u8         reserved_at_40[0x40];
6920 
6921 	struct mlx5_ifc_cqc_bits cq_context;
6922 
6923 	u8         reserved_at_280[0x600];
6924 
6925 	u8         pas[0][0x40];
6926 };
6927 
6928 struct mlx5_ifc_config_int_moderation_out_bits {
6929 	u8         status[0x8];
6930 	u8         reserved_at_8[0x18];
6931 
6932 	u8         syndrome[0x20];
6933 
6934 	u8         reserved_at_40[0x4];
6935 	u8         min_delay[0xc];
6936 	u8         int_vector[0x10];
6937 
6938 	u8         reserved_at_60[0x20];
6939 };
6940 
6941 enum {
6942 	MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
6943 	MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
6944 };
6945 
6946 struct mlx5_ifc_config_int_moderation_in_bits {
6947 	u8         opcode[0x10];
6948 	u8         reserved_at_10[0x10];
6949 
6950 	u8         reserved_at_20[0x10];
6951 	u8         op_mod[0x10];
6952 
6953 	u8         reserved_at_40[0x4];
6954 	u8         min_delay[0xc];
6955 	u8         int_vector[0x10];
6956 
6957 	u8         reserved_at_60[0x20];
6958 };
6959 
6960 struct mlx5_ifc_attach_to_mcg_out_bits {
6961 	u8         status[0x8];
6962 	u8         reserved_at_8[0x18];
6963 
6964 	u8         syndrome[0x20];
6965 
6966 	u8         reserved_at_40[0x40];
6967 };
6968 
6969 struct mlx5_ifc_attach_to_mcg_in_bits {
6970 	u8         opcode[0x10];
6971 	u8         reserved_at_10[0x10];
6972 
6973 	u8         reserved_at_20[0x10];
6974 	u8         op_mod[0x10];
6975 
6976 	u8         reserved_at_40[0x8];
6977 	u8         qpn[0x18];
6978 
6979 	u8         reserved_at_60[0x20];
6980 
6981 	u8         multicast_gid[16][0x8];
6982 };
6983 
6984 struct mlx5_ifc_arm_xrq_out_bits {
6985 	u8         status[0x8];
6986 	u8         reserved_at_8[0x18];
6987 
6988 	u8         syndrome[0x20];
6989 
6990 	u8         reserved_at_40[0x40];
6991 };
6992 
6993 struct mlx5_ifc_arm_xrq_in_bits {
6994 	u8         opcode[0x10];
6995 	u8         reserved_at_10[0x10];
6996 
6997 	u8         reserved_at_20[0x10];
6998 	u8         op_mod[0x10];
6999 
7000 	u8         reserved_at_40[0x8];
7001 	u8         xrqn[0x18];
7002 
7003 	u8         reserved_at_60[0x10];
7004 	u8         lwm[0x10];
7005 };
7006 
7007 struct mlx5_ifc_arm_xrc_srq_out_bits {
7008 	u8         status[0x8];
7009 	u8         reserved_at_8[0x18];
7010 
7011 	u8         syndrome[0x20];
7012 
7013 	u8         reserved_at_40[0x40];
7014 };
7015 
7016 enum {
7017 	MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
7018 };
7019 
7020 struct mlx5_ifc_arm_xrc_srq_in_bits {
7021 	u8         opcode[0x10];
7022 	u8         reserved_at_10[0x10];
7023 
7024 	u8         reserved_at_20[0x10];
7025 	u8         op_mod[0x10];
7026 
7027 	u8         reserved_at_40[0x8];
7028 	u8         xrc_srqn[0x18];
7029 
7030 	u8         reserved_at_60[0x10];
7031 	u8         lwm[0x10];
7032 };
7033 
7034 struct mlx5_ifc_arm_rq_out_bits {
7035 	u8         status[0x8];
7036 	u8         reserved_at_8[0x18];
7037 
7038 	u8         syndrome[0x20];
7039 
7040 	u8         reserved_at_40[0x40];
7041 };
7042 
7043 enum {
7044 	MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
7045 	MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
7046 };
7047 
7048 struct mlx5_ifc_arm_rq_in_bits {
7049 	u8         opcode[0x10];
7050 	u8         reserved_at_10[0x10];
7051 
7052 	u8         reserved_at_20[0x10];
7053 	u8         op_mod[0x10];
7054 
7055 	u8         reserved_at_40[0x8];
7056 	u8         srq_number[0x18];
7057 
7058 	u8         reserved_at_60[0x10];
7059 	u8         lwm[0x10];
7060 };
7061 
7062 struct mlx5_ifc_arm_dct_out_bits {
7063 	u8         status[0x8];
7064 	u8         reserved_at_8[0x18];
7065 
7066 	u8         syndrome[0x20];
7067 
7068 	u8         reserved_at_40[0x40];
7069 };
7070 
7071 struct mlx5_ifc_arm_dct_in_bits {
7072 	u8         opcode[0x10];
7073 	u8         reserved_at_10[0x10];
7074 
7075 	u8         reserved_at_20[0x10];
7076 	u8         op_mod[0x10];
7077 
7078 	u8         reserved_at_40[0x8];
7079 	u8         dct_number[0x18];
7080 
7081 	u8         reserved_at_60[0x20];
7082 };
7083 
7084 struct mlx5_ifc_alloc_xrcd_out_bits {
7085 	u8         status[0x8];
7086 	u8         reserved_at_8[0x18];
7087 
7088 	u8         syndrome[0x20];
7089 
7090 	u8         reserved_at_40[0x8];
7091 	u8         xrcd[0x18];
7092 
7093 	u8         reserved_at_60[0x20];
7094 };
7095 
7096 struct mlx5_ifc_alloc_xrcd_in_bits {
7097 	u8         opcode[0x10];
7098 	u8         reserved_at_10[0x10];
7099 
7100 	u8         reserved_at_20[0x10];
7101 	u8         op_mod[0x10];
7102 
7103 	u8         reserved_at_40[0x40];
7104 };
7105 
7106 struct mlx5_ifc_alloc_uar_out_bits {
7107 	u8         status[0x8];
7108 	u8         reserved_at_8[0x18];
7109 
7110 	u8         syndrome[0x20];
7111 
7112 	u8         reserved_at_40[0x8];
7113 	u8         uar[0x18];
7114 
7115 	u8         reserved_at_60[0x20];
7116 };
7117 
7118 struct mlx5_ifc_alloc_uar_in_bits {
7119 	u8         opcode[0x10];
7120 	u8         reserved_at_10[0x10];
7121 
7122 	u8         reserved_at_20[0x10];
7123 	u8         op_mod[0x10];
7124 
7125 	u8         reserved_at_40[0x40];
7126 };
7127 
7128 struct mlx5_ifc_alloc_transport_domain_out_bits {
7129 	u8         status[0x8];
7130 	u8         reserved_at_8[0x18];
7131 
7132 	u8         syndrome[0x20];
7133 
7134 	u8         reserved_at_40[0x8];
7135 	u8         transport_domain[0x18];
7136 
7137 	u8         reserved_at_60[0x20];
7138 };
7139 
7140 struct mlx5_ifc_alloc_transport_domain_in_bits {
7141 	u8         opcode[0x10];
7142 	u8         reserved_at_10[0x10];
7143 
7144 	u8         reserved_at_20[0x10];
7145 	u8         op_mod[0x10];
7146 
7147 	u8         reserved_at_40[0x40];
7148 };
7149 
7150 struct mlx5_ifc_alloc_q_counter_out_bits {
7151 	u8         status[0x8];
7152 	u8         reserved_at_8[0x18];
7153 
7154 	u8         syndrome[0x20];
7155 
7156 	u8         reserved_at_40[0x18];
7157 	u8         counter_set_id[0x8];
7158 
7159 	u8         reserved_at_60[0x20];
7160 };
7161 
7162 struct mlx5_ifc_alloc_q_counter_in_bits {
7163 	u8         opcode[0x10];
7164 	u8         reserved_at_10[0x10];
7165 
7166 	u8         reserved_at_20[0x10];
7167 	u8         op_mod[0x10];
7168 
7169 	u8         reserved_at_40[0x40];
7170 };
7171 
7172 struct mlx5_ifc_alloc_pd_out_bits {
7173 	u8         status[0x8];
7174 	u8         reserved_at_8[0x18];
7175 
7176 	u8         syndrome[0x20];
7177 
7178 	u8         reserved_at_40[0x8];
7179 	u8         pd[0x18];
7180 
7181 	u8         reserved_at_60[0x20];
7182 };
7183 
7184 struct mlx5_ifc_alloc_pd_in_bits {
7185 	u8         opcode[0x10];
7186 	u8         reserved_at_10[0x10];
7187 
7188 	u8         reserved_at_20[0x10];
7189 	u8         op_mod[0x10];
7190 
7191 	u8         reserved_at_40[0x40];
7192 };
7193 
7194 struct mlx5_ifc_alloc_flow_counter_out_bits {
7195 	u8         status[0x8];
7196 	u8         reserved_at_8[0x18];
7197 
7198 	u8         syndrome[0x20];
7199 
7200 	u8         flow_counter_id[0x20];
7201 
7202 	u8         reserved_at_60[0x20];
7203 };
7204 
7205 struct mlx5_ifc_alloc_flow_counter_in_bits {
7206 	u8         opcode[0x10];
7207 	u8         reserved_at_10[0x10];
7208 
7209 	u8         reserved_at_20[0x10];
7210 	u8         op_mod[0x10];
7211 
7212 	u8         reserved_at_40[0x40];
7213 };
7214 
7215 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
7216 	u8         status[0x8];
7217 	u8         reserved_at_8[0x18];
7218 
7219 	u8         syndrome[0x20];
7220 
7221 	u8         reserved_at_40[0x40];
7222 };
7223 
7224 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
7225 	u8         opcode[0x10];
7226 	u8         reserved_at_10[0x10];
7227 
7228 	u8         reserved_at_20[0x10];
7229 	u8         op_mod[0x10];
7230 
7231 	u8         reserved_at_40[0x20];
7232 
7233 	u8         reserved_at_60[0x10];
7234 	u8         vxlan_udp_port[0x10];
7235 };
7236 
7237 struct mlx5_ifc_set_pp_rate_limit_out_bits {
7238 	u8         status[0x8];
7239 	u8         reserved_at_8[0x18];
7240 
7241 	u8         syndrome[0x20];
7242 
7243 	u8         reserved_at_40[0x40];
7244 };
7245 
7246 struct mlx5_ifc_set_pp_rate_limit_in_bits {
7247 	u8         opcode[0x10];
7248 	u8         reserved_at_10[0x10];
7249 
7250 	u8         reserved_at_20[0x10];
7251 	u8         op_mod[0x10];
7252 
7253 	u8         reserved_at_40[0x10];
7254 	u8         rate_limit_index[0x10];
7255 
7256 	u8         reserved_at_60[0x20];
7257 
7258 	u8         rate_limit[0x20];
7259 
7260 	u8         reserved_at_a0[0x160];
7261 };
7262 
7263 struct mlx5_ifc_access_register_out_bits {
7264 	u8         status[0x8];
7265 	u8         reserved_at_8[0x18];
7266 
7267 	u8         syndrome[0x20];
7268 
7269 	u8         reserved_at_40[0x40];
7270 
7271 	u8         register_data[0][0x20];
7272 };
7273 
7274 enum {
7275 	MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
7276 	MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
7277 };
7278 
7279 struct mlx5_ifc_access_register_in_bits {
7280 	u8         opcode[0x10];
7281 	u8         reserved_at_10[0x10];
7282 
7283 	u8         reserved_at_20[0x10];
7284 	u8         op_mod[0x10];
7285 
7286 	u8         reserved_at_40[0x10];
7287 	u8         register_id[0x10];
7288 
7289 	u8         argument[0x20];
7290 
7291 	u8         register_data[0][0x20];
7292 };
7293 
7294 struct mlx5_ifc_sltp_reg_bits {
7295 	u8         status[0x4];
7296 	u8         version[0x4];
7297 	u8         local_port[0x8];
7298 	u8         pnat[0x2];
7299 	u8         reserved_at_12[0x2];
7300 	u8         lane[0x4];
7301 	u8         reserved_at_18[0x8];
7302 
7303 	u8         reserved_at_20[0x20];
7304 
7305 	u8         reserved_at_40[0x7];
7306 	u8         polarity[0x1];
7307 	u8         ob_tap0[0x8];
7308 	u8         ob_tap1[0x8];
7309 	u8         ob_tap2[0x8];
7310 
7311 	u8         reserved_at_60[0xc];
7312 	u8         ob_preemp_mode[0x4];
7313 	u8         ob_reg[0x8];
7314 	u8         ob_bias[0x8];
7315 
7316 	u8         reserved_at_80[0x20];
7317 };
7318 
7319 struct mlx5_ifc_slrg_reg_bits {
7320 	u8         status[0x4];
7321 	u8         version[0x4];
7322 	u8         local_port[0x8];
7323 	u8         pnat[0x2];
7324 	u8         reserved_at_12[0x2];
7325 	u8         lane[0x4];
7326 	u8         reserved_at_18[0x8];
7327 
7328 	u8         time_to_link_up[0x10];
7329 	u8         reserved_at_30[0xc];
7330 	u8         grade_lane_speed[0x4];
7331 
7332 	u8         grade_version[0x8];
7333 	u8         grade[0x18];
7334 
7335 	u8         reserved_at_60[0x4];
7336 	u8         height_grade_type[0x4];
7337 	u8         height_grade[0x18];
7338 
7339 	u8         height_dz[0x10];
7340 	u8         height_dv[0x10];
7341 
7342 	u8         reserved_at_a0[0x10];
7343 	u8         height_sigma[0x10];
7344 
7345 	u8         reserved_at_c0[0x20];
7346 
7347 	u8         reserved_at_e0[0x4];
7348 	u8         phase_grade_type[0x4];
7349 	u8         phase_grade[0x18];
7350 
7351 	u8         reserved_at_100[0x8];
7352 	u8         phase_eo_pos[0x8];
7353 	u8         reserved_at_110[0x8];
7354 	u8         phase_eo_neg[0x8];
7355 
7356 	u8         ffe_set_tested[0x10];
7357 	u8         test_errors_per_lane[0x10];
7358 };
7359 
7360 struct mlx5_ifc_pvlc_reg_bits {
7361 	u8         reserved_at_0[0x8];
7362 	u8         local_port[0x8];
7363 	u8         reserved_at_10[0x10];
7364 
7365 	u8         reserved_at_20[0x1c];
7366 	u8         vl_hw_cap[0x4];
7367 
7368 	u8         reserved_at_40[0x1c];
7369 	u8         vl_admin[0x4];
7370 
7371 	u8         reserved_at_60[0x1c];
7372 	u8         vl_operational[0x4];
7373 };
7374 
7375 struct mlx5_ifc_pude_reg_bits {
7376 	u8         swid[0x8];
7377 	u8         local_port[0x8];
7378 	u8         reserved_at_10[0x4];
7379 	u8         admin_status[0x4];
7380 	u8         reserved_at_18[0x4];
7381 	u8         oper_status[0x4];
7382 
7383 	u8         reserved_at_20[0x60];
7384 };
7385 
7386 struct mlx5_ifc_ptys_reg_bits {
7387 	u8         reserved_at_0[0x1];
7388 	u8         an_disable_admin[0x1];
7389 	u8         an_disable_cap[0x1];
7390 	u8         reserved_at_3[0x5];
7391 	u8         local_port[0x8];
7392 	u8         reserved_at_10[0xd];
7393 	u8         proto_mask[0x3];
7394 
7395 	u8         an_status[0x4];
7396 	u8         reserved_at_24[0x3c];
7397 
7398 	u8         eth_proto_capability[0x20];
7399 
7400 	u8         ib_link_width_capability[0x10];
7401 	u8         ib_proto_capability[0x10];
7402 
7403 	u8         reserved_at_a0[0x20];
7404 
7405 	u8         eth_proto_admin[0x20];
7406 
7407 	u8         ib_link_width_admin[0x10];
7408 	u8         ib_proto_admin[0x10];
7409 
7410 	u8         reserved_at_100[0x20];
7411 
7412 	u8         eth_proto_oper[0x20];
7413 
7414 	u8         ib_link_width_oper[0x10];
7415 	u8         ib_proto_oper[0x10];
7416 
7417 	u8         reserved_at_160[0x1c];
7418 	u8         connector_type[0x4];
7419 
7420 	u8         eth_proto_lp_advertise[0x20];
7421 
7422 	u8         reserved_at_1a0[0x60];
7423 };
7424 
7425 struct mlx5_ifc_mlcr_reg_bits {
7426 	u8         reserved_at_0[0x8];
7427 	u8         local_port[0x8];
7428 	u8         reserved_at_10[0x20];
7429 
7430 	u8         beacon_duration[0x10];
7431 	u8         reserved_at_40[0x10];
7432 
7433 	u8         beacon_remain[0x10];
7434 };
7435 
7436 struct mlx5_ifc_ptas_reg_bits {
7437 	u8         reserved_at_0[0x20];
7438 
7439 	u8         algorithm_options[0x10];
7440 	u8         reserved_at_30[0x4];
7441 	u8         repetitions_mode[0x4];
7442 	u8         num_of_repetitions[0x8];
7443 
7444 	u8         grade_version[0x8];
7445 	u8         height_grade_type[0x4];
7446 	u8         phase_grade_type[0x4];
7447 	u8         height_grade_weight[0x8];
7448 	u8         phase_grade_weight[0x8];
7449 
7450 	u8         gisim_measure_bits[0x10];
7451 	u8         adaptive_tap_measure_bits[0x10];
7452 
7453 	u8         ber_bath_high_error_threshold[0x10];
7454 	u8         ber_bath_mid_error_threshold[0x10];
7455 
7456 	u8         ber_bath_low_error_threshold[0x10];
7457 	u8         one_ratio_high_threshold[0x10];
7458 
7459 	u8         one_ratio_high_mid_threshold[0x10];
7460 	u8         one_ratio_low_mid_threshold[0x10];
7461 
7462 	u8         one_ratio_low_threshold[0x10];
7463 	u8         ndeo_error_threshold[0x10];
7464 
7465 	u8         mixer_offset_step_size[0x10];
7466 	u8         reserved_at_110[0x8];
7467 	u8         mix90_phase_for_voltage_bath[0x8];
7468 
7469 	u8         mixer_offset_start[0x10];
7470 	u8         mixer_offset_end[0x10];
7471 
7472 	u8         reserved_at_140[0x15];
7473 	u8         ber_test_time[0xb];
7474 };
7475 
7476 struct mlx5_ifc_pspa_reg_bits {
7477 	u8         swid[0x8];
7478 	u8         local_port[0x8];
7479 	u8         sub_port[0x8];
7480 	u8         reserved_at_18[0x8];
7481 
7482 	u8         reserved_at_20[0x20];
7483 };
7484 
7485 struct mlx5_ifc_pqdr_reg_bits {
7486 	u8         reserved_at_0[0x8];
7487 	u8         local_port[0x8];
7488 	u8         reserved_at_10[0x5];
7489 	u8         prio[0x3];
7490 	u8         reserved_at_18[0x6];
7491 	u8         mode[0x2];
7492 
7493 	u8         reserved_at_20[0x20];
7494 
7495 	u8         reserved_at_40[0x10];
7496 	u8         min_threshold[0x10];
7497 
7498 	u8         reserved_at_60[0x10];
7499 	u8         max_threshold[0x10];
7500 
7501 	u8         reserved_at_80[0x10];
7502 	u8         mark_probability_denominator[0x10];
7503 
7504 	u8         reserved_at_a0[0x60];
7505 };
7506 
7507 struct mlx5_ifc_ppsc_reg_bits {
7508 	u8         reserved_at_0[0x8];
7509 	u8         local_port[0x8];
7510 	u8         reserved_at_10[0x10];
7511 
7512 	u8         reserved_at_20[0x60];
7513 
7514 	u8         reserved_at_80[0x1c];
7515 	u8         wrps_admin[0x4];
7516 
7517 	u8         reserved_at_a0[0x1c];
7518 	u8         wrps_status[0x4];
7519 
7520 	u8         reserved_at_c0[0x8];
7521 	u8         up_threshold[0x8];
7522 	u8         reserved_at_d0[0x8];
7523 	u8         down_threshold[0x8];
7524 
7525 	u8         reserved_at_e0[0x20];
7526 
7527 	u8         reserved_at_100[0x1c];
7528 	u8         srps_admin[0x4];
7529 
7530 	u8         reserved_at_120[0x1c];
7531 	u8         srps_status[0x4];
7532 
7533 	u8         reserved_at_140[0x40];
7534 };
7535 
7536 struct mlx5_ifc_pplr_reg_bits {
7537 	u8         reserved_at_0[0x8];
7538 	u8         local_port[0x8];
7539 	u8         reserved_at_10[0x10];
7540 
7541 	u8         reserved_at_20[0x8];
7542 	u8         lb_cap[0x8];
7543 	u8         reserved_at_30[0x8];
7544 	u8         lb_en[0x8];
7545 };
7546 
7547 struct mlx5_ifc_pplm_reg_bits {
7548 	u8         reserved_at_0[0x8];
7549 	u8         local_port[0x8];
7550 	u8         reserved_at_10[0x10];
7551 
7552 	u8         reserved_at_20[0x20];
7553 
7554 	u8         port_profile_mode[0x8];
7555 	u8         static_port_profile[0x8];
7556 	u8         active_port_profile[0x8];
7557 	u8         reserved_at_58[0x8];
7558 
7559 	u8         retransmission_active[0x8];
7560 	u8         fec_mode_active[0x18];
7561 
7562 	u8         reserved_at_80[0x20];
7563 };
7564 
7565 struct mlx5_ifc_ppcnt_reg_bits {
7566 	u8         swid[0x8];
7567 	u8         local_port[0x8];
7568 	u8         pnat[0x2];
7569 	u8         reserved_at_12[0x8];
7570 	u8         grp[0x6];
7571 
7572 	u8         clr[0x1];
7573 	u8         reserved_at_21[0x1c];
7574 	u8         prio_tc[0x3];
7575 
7576 	union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
7577 };
7578 
7579 struct mlx5_ifc_mpcnt_reg_bits {
7580 	u8         reserved_at_0[0x8];
7581 	u8         pcie_index[0x8];
7582 	u8         reserved_at_10[0xa];
7583 	u8         grp[0x6];
7584 
7585 	u8         clr[0x1];
7586 	u8         reserved_at_21[0x1f];
7587 
7588 	union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
7589 };
7590 
7591 struct mlx5_ifc_ppad_reg_bits {
7592 	u8         reserved_at_0[0x3];
7593 	u8         single_mac[0x1];
7594 	u8         reserved_at_4[0x4];
7595 	u8         local_port[0x8];
7596 	u8         mac_47_32[0x10];
7597 
7598 	u8         mac_31_0[0x20];
7599 
7600 	u8         reserved_at_40[0x40];
7601 };
7602 
7603 struct mlx5_ifc_pmtu_reg_bits {
7604 	u8         reserved_at_0[0x8];
7605 	u8         local_port[0x8];
7606 	u8         reserved_at_10[0x10];
7607 
7608 	u8         max_mtu[0x10];
7609 	u8         reserved_at_30[0x10];
7610 
7611 	u8         admin_mtu[0x10];
7612 	u8         reserved_at_50[0x10];
7613 
7614 	u8         oper_mtu[0x10];
7615 	u8         reserved_at_70[0x10];
7616 };
7617 
7618 struct mlx5_ifc_pmpr_reg_bits {
7619 	u8         reserved_at_0[0x8];
7620 	u8         module[0x8];
7621 	u8         reserved_at_10[0x10];
7622 
7623 	u8         reserved_at_20[0x18];
7624 	u8         attenuation_5g[0x8];
7625 
7626 	u8         reserved_at_40[0x18];
7627 	u8         attenuation_7g[0x8];
7628 
7629 	u8         reserved_at_60[0x18];
7630 	u8         attenuation_12g[0x8];
7631 };
7632 
7633 struct mlx5_ifc_pmpe_reg_bits {
7634 	u8         reserved_at_0[0x8];
7635 	u8         module[0x8];
7636 	u8         reserved_at_10[0xc];
7637 	u8         module_status[0x4];
7638 
7639 	u8         reserved_at_20[0x60];
7640 };
7641 
7642 struct mlx5_ifc_pmpc_reg_bits {
7643 	u8         module_state_updated[32][0x8];
7644 };
7645 
7646 struct mlx5_ifc_pmlpn_reg_bits {
7647 	u8         reserved_at_0[0x4];
7648 	u8         mlpn_status[0x4];
7649 	u8         local_port[0x8];
7650 	u8         reserved_at_10[0x10];
7651 
7652 	u8         e[0x1];
7653 	u8         reserved_at_21[0x1f];
7654 };
7655 
7656 struct mlx5_ifc_pmlp_reg_bits {
7657 	u8         rxtx[0x1];
7658 	u8         reserved_at_1[0x7];
7659 	u8         local_port[0x8];
7660 	u8         reserved_at_10[0x8];
7661 	u8         width[0x8];
7662 
7663 	u8         lane0_module_mapping[0x20];
7664 
7665 	u8         lane1_module_mapping[0x20];
7666 
7667 	u8         lane2_module_mapping[0x20];
7668 
7669 	u8         lane3_module_mapping[0x20];
7670 
7671 	u8         reserved_at_a0[0x160];
7672 };
7673 
7674 struct mlx5_ifc_pmaos_reg_bits {
7675 	u8         reserved_at_0[0x8];
7676 	u8         module[0x8];
7677 	u8         reserved_at_10[0x4];
7678 	u8         admin_status[0x4];
7679 	u8         reserved_at_18[0x4];
7680 	u8         oper_status[0x4];
7681 
7682 	u8         ase[0x1];
7683 	u8         ee[0x1];
7684 	u8         reserved_at_22[0x1c];
7685 	u8         e[0x2];
7686 
7687 	u8         reserved_at_40[0x40];
7688 };
7689 
7690 struct mlx5_ifc_plpc_reg_bits {
7691 	u8         reserved_at_0[0x4];
7692 	u8         profile_id[0xc];
7693 	u8         reserved_at_10[0x4];
7694 	u8         proto_mask[0x4];
7695 	u8         reserved_at_18[0x8];
7696 
7697 	u8         reserved_at_20[0x10];
7698 	u8         lane_speed[0x10];
7699 
7700 	u8         reserved_at_40[0x17];
7701 	u8         lpbf[0x1];
7702 	u8         fec_mode_policy[0x8];
7703 
7704 	u8         retransmission_capability[0x8];
7705 	u8         fec_mode_capability[0x18];
7706 
7707 	u8         retransmission_support_admin[0x8];
7708 	u8         fec_mode_support_admin[0x18];
7709 
7710 	u8         retransmission_request_admin[0x8];
7711 	u8         fec_mode_request_admin[0x18];
7712 
7713 	u8         reserved_at_c0[0x80];
7714 };
7715 
7716 struct mlx5_ifc_plib_reg_bits {
7717 	u8         reserved_at_0[0x8];
7718 	u8         local_port[0x8];
7719 	u8         reserved_at_10[0x8];
7720 	u8         ib_port[0x8];
7721 
7722 	u8         reserved_at_20[0x60];
7723 };
7724 
7725 struct mlx5_ifc_plbf_reg_bits {
7726 	u8         reserved_at_0[0x8];
7727 	u8         local_port[0x8];
7728 	u8         reserved_at_10[0xd];
7729 	u8         lbf_mode[0x3];
7730 
7731 	u8         reserved_at_20[0x20];
7732 };
7733 
7734 struct mlx5_ifc_pipg_reg_bits {
7735 	u8         reserved_at_0[0x8];
7736 	u8         local_port[0x8];
7737 	u8         reserved_at_10[0x10];
7738 
7739 	u8         dic[0x1];
7740 	u8         reserved_at_21[0x19];
7741 	u8         ipg[0x4];
7742 	u8         reserved_at_3e[0x2];
7743 };
7744 
7745 struct mlx5_ifc_pifr_reg_bits {
7746 	u8         reserved_at_0[0x8];
7747 	u8         local_port[0x8];
7748 	u8         reserved_at_10[0x10];
7749 
7750 	u8         reserved_at_20[0xe0];
7751 
7752 	u8         port_filter[8][0x20];
7753 
7754 	u8         port_filter_update_en[8][0x20];
7755 };
7756 
7757 struct mlx5_ifc_pfcc_reg_bits {
7758 	u8         reserved_at_0[0x8];
7759 	u8         local_port[0x8];
7760 	u8         reserved_at_10[0x10];
7761 
7762 	u8         ppan[0x4];
7763 	u8         reserved_at_24[0x4];
7764 	u8         prio_mask_tx[0x8];
7765 	u8         reserved_at_30[0x8];
7766 	u8         prio_mask_rx[0x8];
7767 
7768 	u8         pptx[0x1];
7769 	u8         aptx[0x1];
7770 	u8         reserved_at_42[0x6];
7771 	u8         pfctx[0x8];
7772 	u8         reserved_at_50[0x10];
7773 
7774 	u8         pprx[0x1];
7775 	u8         aprx[0x1];
7776 	u8         reserved_at_62[0x6];
7777 	u8         pfcrx[0x8];
7778 	u8         reserved_at_70[0x10];
7779 
7780 	u8         reserved_at_80[0x80];
7781 };
7782 
7783 struct mlx5_ifc_pelc_reg_bits {
7784 	u8         op[0x4];
7785 	u8         reserved_at_4[0x4];
7786 	u8         local_port[0x8];
7787 	u8         reserved_at_10[0x10];
7788 
7789 	u8         op_admin[0x8];
7790 	u8         op_capability[0x8];
7791 	u8         op_request[0x8];
7792 	u8         op_active[0x8];
7793 
7794 	u8         admin[0x40];
7795 
7796 	u8         capability[0x40];
7797 
7798 	u8         request[0x40];
7799 
7800 	u8         active[0x40];
7801 
7802 	u8         reserved_at_140[0x80];
7803 };
7804 
7805 struct mlx5_ifc_peir_reg_bits {
7806 	u8         reserved_at_0[0x8];
7807 	u8         local_port[0x8];
7808 	u8         reserved_at_10[0x10];
7809 
7810 	u8         reserved_at_20[0xc];
7811 	u8         error_count[0x4];
7812 	u8         reserved_at_30[0x10];
7813 
7814 	u8         reserved_at_40[0xc];
7815 	u8         lane[0x4];
7816 	u8         reserved_at_50[0x8];
7817 	u8         error_type[0x8];
7818 };
7819 
7820 struct mlx5_ifc_pcam_enhanced_features_bits {
7821 	u8         reserved_at_0[0x7b];
7822 
7823 	u8         rx_buffer_fullness_counters[0x1];
7824 	u8         ptys_connector_type[0x1];
7825 	u8         reserved_at_7d[0x1];
7826 	u8         ppcnt_discard_group[0x1];
7827 	u8         ppcnt_statistical_group[0x1];
7828 };
7829 
7830 struct mlx5_ifc_pcam_reg_bits {
7831 	u8         reserved_at_0[0x8];
7832 	u8         feature_group[0x8];
7833 	u8         reserved_at_10[0x8];
7834 	u8         access_reg_group[0x8];
7835 
7836 	u8         reserved_at_20[0x20];
7837 
7838 	union {
7839 		u8         reserved_at_0[0x80];
7840 	} port_access_reg_cap_mask;
7841 
7842 	u8         reserved_at_c0[0x80];
7843 
7844 	union {
7845 		struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
7846 		u8         reserved_at_0[0x80];
7847 	} feature_cap_mask;
7848 
7849 	u8         reserved_at_1c0[0xc0];
7850 };
7851 
7852 struct mlx5_ifc_mcam_enhanced_features_bits {
7853 	u8         reserved_at_0[0x7b];
7854 	u8         pcie_outbound_stalled[0x1];
7855 	u8         tx_overflow_buffer_pkt[0x1];
7856 	u8         mtpps_enh_out_per_adj[0x1];
7857 	u8         mtpps_fs[0x1];
7858 	u8         pcie_performance_group[0x1];
7859 };
7860 
7861 struct mlx5_ifc_mcam_access_reg_bits {
7862 	u8         reserved_at_0[0x1c];
7863 	u8         mcda[0x1];
7864 	u8         mcc[0x1];
7865 	u8         mcqi[0x1];
7866 	u8         reserved_at_1f[0x1];
7867 
7868 	u8         regs_95_to_64[0x20];
7869 	u8         regs_63_to_32[0x20];
7870 	u8         regs_31_to_0[0x20];
7871 };
7872 
7873 struct mlx5_ifc_mcam_reg_bits {
7874 	u8         reserved_at_0[0x8];
7875 	u8         feature_group[0x8];
7876 	u8         reserved_at_10[0x8];
7877 	u8         access_reg_group[0x8];
7878 
7879 	u8         reserved_at_20[0x20];
7880 
7881 	union {
7882 		struct mlx5_ifc_mcam_access_reg_bits access_regs;
7883 		u8         reserved_at_0[0x80];
7884 	} mng_access_reg_cap_mask;
7885 
7886 	u8         reserved_at_c0[0x80];
7887 
7888 	union {
7889 		struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
7890 		u8         reserved_at_0[0x80];
7891 	} mng_feature_cap_mask;
7892 
7893 	u8         reserved_at_1c0[0x80];
7894 };
7895 
7896 struct mlx5_ifc_pcap_reg_bits {
7897 	u8         reserved_at_0[0x8];
7898 	u8         local_port[0x8];
7899 	u8         reserved_at_10[0x10];
7900 
7901 	u8         port_capability_mask[4][0x20];
7902 };
7903 
7904 struct mlx5_ifc_paos_reg_bits {
7905 	u8         swid[0x8];
7906 	u8         local_port[0x8];
7907 	u8         reserved_at_10[0x4];
7908 	u8         admin_status[0x4];
7909 	u8         reserved_at_18[0x4];
7910 	u8         oper_status[0x4];
7911 
7912 	u8         ase[0x1];
7913 	u8         ee[0x1];
7914 	u8         reserved_at_22[0x1c];
7915 	u8         e[0x2];
7916 
7917 	u8         reserved_at_40[0x40];
7918 };
7919 
7920 struct mlx5_ifc_pamp_reg_bits {
7921 	u8         reserved_at_0[0x8];
7922 	u8         opamp_group[0x8];
7923 	u8         reserved_at_10[0xc];
7924 	u8         opamp_group_type[0x4];
7925 
7926 	u8         start_index[0x10];
7927 	u8         reserved_at_30[0x4];
7928 	u8         num_of_indices[0xc];
7929 
7930 	u8         index_data[18][0x10];
7931 };
7932 
7933 struct mlx5_ifc_pcmr_reg_bits {
7934 	u8         reserved_at_0[0x8];
7935 	u8         local_port[0x8];
7936 	u8         reserved_at_10[0x2e];
7937 	u8         fcs_cap[0x1];
7938 	u8         reserved_at_3f[0x1f];
7939 	u8         fcs_chk[0x1];
7940 	u8         reserved_at_5f[0x1];
7941 };
7942 
7943 struct mlx5_ifc_lane_2_module_mapping_bits {
7944 	u8         reserved_at_0[0x6];
7945 	u8         rx_lane[0x2];
7946 	u8         reserved_at_8[0x6];
7947 	u8         tx_lane[0x2];
7948 	u8         reserved_at_10[0x8];
7949 	u8         module[0x8];
7950 };
7951 
7952 struct mlx5_ifc_bufferx_reg_bits {
7953 	u8         reserved_at_0[0x6];
7954 	u8         lossy[0x1];
7955 	u8         epsb[0x1];
7956 	u8         reserved_at_8[0xc];
7957 	u8         size[0xc];
7958 
7959 	u8         xoff_threshold[0x10];
7960 	u8         xon_threshold[0x10];
7961 };
7962 
7963 struct mlx5_ifc_set_node_in_bits {
7964 	u8         node_description[64][0x8];
7965 };
7966 
7967 struct mlx5_ifc_register_power_settings_bits {
7968 	u8         reserved_at_0[0x18];
7969 	u8         power_settings_level[0x8];
7970 
7971 	u8         reserved_at_20[0x60];
7972 };
7973 
7974 struct mlx5_ifc_register_host_endianness_bits {
7975 	u8         he[0x1];
7976 	u8         reserved_at_1[0x1f];
7977 
7978 	u8         reserved_at_20[0x60];
7979 };
7980 
7981 struct mlx5_ifc_umr_pointer_desc_argument_bits {
7982 	u8         reserved_at_0[0x20];
7983 
7984 	u8         mkey[0x20];
7985 
7986 	u8         addressh_63_32[0x20];
7987 
7988 	u8         addressl_31_0[0x20];
7989 };
7990 
7991 struct mlx5_ifc_ud_adrs_vector_bits {
7992 	u8         dc_key[0x40];
7993 
7994 	u8         ext[0x1];
7995 	u8         reserved_at_41[0x7];
7996 	u8         destination_qp_dct[0x18];
7997 
7998 	u8         static_rate[0x4];
7999 	u8         sl_eth_prio[0x4];
8000 	u8         fl[0x1];
8001 	u8         mlid[0x7];
8002 	u8         rlid_udp_sport[0x10];
8003 
8004 	u8         reserved_at_80[0x20];
8005 
8006 	u8         rmac_47_16[0x20];
8007 
8008 	u8         rmac_15_0[0x10];
8009 	u8         tclass[0x8];
8010 	u8         hop_limit[0x8];
8011 
8012 	u8         reserved_at_e0[0x1];
8013 	u8         grh[0x1];
8014 	u8         reserved_at_e2[0x2];
8015 	u8         src_addr_index[0x8];
8016 	u8         flow_label[0x14];
8017 
8018 	u8         rgid_rip[16][0x8];
8019 };
8020 
8021 struct mlx5_ifc_pages_req_event_bits {
8022 	u8         reserved_at_0[0x10];
8023 	u8         function_id[0x10];
8024 
8025 	u8         num_pages[0x20];
8026 
8027 	u8         reserved_at_40[0xa0];
8028 };
8029 
8030 struct mlx5_ifc_eqe_bits {
8031 	u8         reserved_at_0[0x8];
8032 	u8         event_type[0x8];
8033 	u8         reserved_at_10[0x8];
8034 	u8         event_sub_type[0x8];
8035 
8036 	u8         reserved_at_20[0xe0];
8037 
8038 	union mlx5_ifc_event_auto_bits event_data;
8039 
8040 	u8         reserved_at_1e0[0x10];
8041 	u8         signature[0x8];
8042 	u8         reserved_at_1f8[0x7];
8043 	u8         owner[0x1];
8044 };
8045 
8046 enum {
8047 	MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
8048 };
8049 
8050 struct mlx5_ifc_cmd_queue_entry_bits {
8051 	u8         type[0x8];
8052 	u8         reserved_at_8[0x18];
8053 
8054 	u8         input_length[0x20];
8055 
8056 	u8         input_mailbox_pointer_63_32[0x20];
8057 
8058 	u8         input_mailbox_pointer_31_9[0x17];
8059 	u8         reserved_at_77[0x9];
8060 
8061 	u8         command_input_inline_data[16][0x8];
8062 
8063 	u8         command_output_inline_data[16][0x8];
8064 
8065 	u8         output_mailbox_pointer_63_32[0x20];
8066 
8067 	u8         output_mailbox_pointer_31_9[0x17];
8068 	u8         reserved_at_1b7[0x9];
8069 
8070 	u8         output_length[0x20];
8071 
8072 	u8         token[0x8];
8073 	u8         signature[0x8];
8074 	u8         reserved_at_1f0[0x8];
8075 	u8         status[0x7];
8076 	u8         ownership[0x1];
8077 };
8078 
8079 struct mlx5_ifc_cmd_out_bits {
8080 	u8         status[0x8];
8081 	u8         reserved_at_8[0x18];
8082 
8083 	u8         syndrome[0x20];
8084 
8085 	u8         command_output[0x20];
8086 };
8087 
8088 struct mlx5_ifc_cmd_in_bits {
8089 	u8         opcode[0x10];
8090 	u8         reserved_at_10[0x10];
8091 
8092 	u8         reserved_at_20[0x10];
8093 	u8         op_mod[0x10];
8094 
8095 	u8         command[0][0x20];
8096 };
8097 
8098 struct mlx5_ifc_cmd_if_box_bits {
8099 	u8         mailbox_data[512][0x8];
8100 
8101 	u8         reserved_at_1000[0x180];
8102 
8103 	u8         next_pointer_63_32[0x20];
8104 
8105 	u8         next_pointer_31_10[0x16];
8106 	u8         reserved_at_11b6[0xa];
8107 
8108 	u8         block_number[0x20];
8109 
8110 	u8         reserved_at_11e0[0x8];
8111 	u8         token[0x8];
8112 	u8         ctrl_signature[0x8];
8113 	u8         signature[0x8];
8114 };
8115 
8116 struct mlx5_ifc_mtt_bits {
8117 	u8         ptag_63_32[0x20];
8118 
8119 	u8         ptag_31_8[0x18];
8120 	u8         reserved_at_38[0x6];
8121 	u8         wr_en[0x1];
8122 	u8         rd_en[0x1];
8123 };
8124 
8125 struct mlx5_ifc_query_wol_rol_out_bits {
8126 	u8         status[0x8];
8127 	u8         reserved_at_8[0x18];
8128 
8129 	u8         syndrome[0x20];
8130 
8131 	u8         reserved_at_40[0x10];
8132 	u8         rol_mode[0x8];
8133 	u8         wol_mode[0x8];
8134 
8135 	u8         reserved_at_60[0x20];
8136 };
8137 
8138 struct mlx5_ifc_query_wol_rol_in_bits {
8139 	u8         opcode[0x10];
8140 	u8         reserved_at_10[0x10];
8141 
8142 	u8         reserved_at_20[0x10];
8143 	u8         op_mod[0x10];
8144 
8145 	u8         reserved_at_40[0x40];
8146 };
8147 
8148 struct mlx5_ifc_set_wol_rol_out_bits {
8149 	u8         status[0x8];
8150 	u8         reserved_at_8[0x18];
8151 
8152 	u8         syndrome[0x20];
8153 
8154 	u8         reserved_at_40[0x40];
8155 };
8156 
8157 struct mlx5_ifc_set_wol_rol_in_bits {
8158 	u8         opcode[0x10];
8159 	u8         reserved_at_10[0x10];
8160 
8161 	u8         reserved_at_20[0x10];
8162 	u8         op_mod[0x10];
8163 
8164 	u8         rol_mode_valid[0x1];
8165 	u8         wol_mode_valid[0x1];
8166 	u8         reserved_at_42[0xe];
8167 	u8         rol_mode[0x8];
8168 	u8         wol_mode[0x8];
8169 
8170 	u8         reserved_at_60[0x20];
8171 };
8172 
8173 enum {
8174 	MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
8175 	MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
8176 	MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
8177 };
8178 
8179 enum {
8180 	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
8181 	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
8182 	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
8183 };
8184 
8185 enum {
8186 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
8187 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
8188 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
8189 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
8190 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
8191 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
8192 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
8193 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
8194 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
8195 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
8196 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
8197 };
8198 
8199 struct mlx5_ifc_initial_seg_bits {
8200 	u8         fw_rev_minor[0x10];
8201 	u8         fw_rev_major[0x10];
8202 
8203 	u8         cmd_interface_rev[0x10];
8204 	u8         fw_rev_subminor[0x10];
8205 
8206 	u8         reserved_at_40[0x40];
8207 
8208 	u8         cmdq_phy_addr_63_32[0x20];
8209 
8210 	u8         cmdq_phy_addr_31_12[0x14];
8211 	u8         reserved_at_b4[0x2];
8212 	u8         nic_interface[0x2];
8213 	u8         log_cmdq_size[0x4];
8214 	u8         log_cmdq_stride[0x4];
8215 
8216 	u8         command_doorbell_vector[0x20];
8217 
8218 	u8         reserved_at_e0[0xf00];
8219 
8220 	u8         initializing[0x1];
8221 	u8         reserved_at_fe1[0x4];
8222 	u8         nic_interface_supported[0x3];
8223 	u8         reserved_at_fe8[0x18];
8224 
8225 	struct mlx5_ifc_health_buffer_bits health_buffer;
8226 
8227 	u8         no_dram_nic_offset[0x20];
8228 
8229 	u8         reserved_at_1220[0x6e40];
8230 
8231 	u8         reserved_at_8060[0x1f];
8232 	u8         clear_int[0x1];
8233 
8234 	u8         health_syndrome[0x8];
8235 	u8         health_counter[0x18];
8236 
8237 	u8         reserved_at_80a0[0x17fc0];
8238 };
8239 
8240 struct mlx5_ifc_mtpps_reg_bits {
8241 	u8         reserved_at_0[0xc];
8242 	u8         cap_number_of_pps_pins[0x4];
8243 	u8         reserved_at_10[0x4];
8244 	u8         cap_max_num_of_pps_in_pins[0x4];
8245 	u8         reserved_at_18[0x4];
8246 	u8         cap_max_num_of_pps_out_pins[0x4];
8247 
8248 	u8         reserved_at_20[0x24];
8249 	u8         cap_pin_3_mode[0x4];
8250 	u8         reserved_at_48[0x4];
8251 	u8         cap_pin_2_mode[0x4];
8252 	u8         reserved_at_50[0x4];
8253 	u8         cap_pin_1_mode[0x4];
8254 	u8         reserved_at_58[0x4];
8255 	u8         cap_pin_0_mode[0x4];
8256 
8257 	u8         reserved_at_60[0x4];
8258 	u8         cap_pin_7_mode[0x4];
8259 	u8         reserved_at_68[0x4];
8260 	u8         cap_pin_6_mode[0x4];
8261 	u8         reserved_at_70[0x4];
8262 	u8         cap_pin_5_mode[0x4];
8263 	u8         reserved_at_78[0x4];
8264 	u8         cap_pin_4_mode[0x4];
8265 
8266 	u8         field_select[0x20];
8267 	u8         reserved_at_a0[0x60];
8268 
8269 	u8         enable[0x1];
8270 	u8         reserved_at_101[0xb];
8271 	u8         pattern[0x4];
8272 	u8         reserved_at_110[0x4];
8273 	u8         pin_mode[0x4];
8274 	u8         pin[0x8];
8275 
8276 	u8         reserved_at_120[0x20];
8277 
8278 	u8         time_stamp[0x40];
8279 
8280 	u8         out_pulse_duration[0x10];
8281 	u8         out_periodic_adjustment[0x10];
8282 	u8         enhanced_out_periodic_adjustment[0x20];
8283 
8284 	u8         reserved_at_1c0[0x20];
8285 };
8286 
8287 struct mlx5_ifc_mtppse_reg_bits {
8288 	u8         reserved_at_0[0x18];
8289 	u8         pin[0x8];
8290 	u8         event_arm[0x1];
8291 	u8         reserved_at_21[0x1b];
8292 	u8         event_generation_mode[0x4];
8293 	u8         reserved_at_40[0x40];
8294 };
8295 
8296 struct mlx5_ifc_mcqi_cap_bits {
8297 	u8         supported_info_bitmask[0x20];
8298 
8299 	u8         component_size[0x20];
8300 
8301 	u8         max_component_size[0x20];
8302 
8303 	u8         log_mcda_word_size[0x4];
8304 	u8         reserved_at_64[0xc];
8305 	u8         mcda_max_write_size[0x10];
8306 
8307 	u8         rd_en[0x1];
8308 	u8         reserved_at_81[0x1];
8309 	u8         match_chip_id[0x1];
8310 	u8         match_psid[0x1];
8311 	u8         check_user_timestamp[0x1];
8312 	u8         match_base_guid_mac[0x1];
8313 	u8         reserved_at_86[0x1a];
8314 };
8315 
8316 struct mlx5_ifc_mcqi_reg_bits {
8317 	u8         read_pending_component[0x1];
8318 	u8         reserved_at_1[0xf];
8319 	u8         component_index[0x10];
8320 
8321 	u8         reserved_at_20[0x20];
8322 
8323 	u8         reserved_at_40[0x1b];
8324 	u8         info_type[0x5];
8325 
8326 	u8         info_size[0x20];
8327 
8328 	u8         offset[0x20];
8329 
8330 	u8         reserved_at_a0[0x10];
8331 	u8         data_size[0x10];
8332 
8333 	u8         data[0][0x20];
8334 };
8335 
8336 struct mlx5_ifc_mcc_reg_bits {
8337 	u8         reserved_at_0[0x4];
8338 	u8         time_elapsed_since_last_cmd[0xc];
8339 	u8         reserved_at_10[0x8];
8340 	u8         instruction[0x8];
8341 
8342 	u8         reserved_at_20[0x10];
8343 	u8         component_index[0x10];
8344 
8345 	u8         reserved_at_40[0x8];
8346 	u8         update_handle[0x18];
8347 
8348 	u8         handle_owner_type[0x4];
8349 	u8         handle_owner_host_id[0x4];
8350 	u8         reserved_at_68[0x1];
8351 	u8         control_progress[0x7];
8352 	u8         error_code[0x8];
8353 	u8         reserved_at_78[0x4];
8354 	u8         control_state[0x4];
8355 
8356 	u8         component_size[0x20];
8357 
8358 	u8         reserved_at_a0[0x60];
8359 };
8360 
8361 struct mlx5_ifc_mcda_reg_bits {
8362 	u8         reserved_at_0[0x8];
8363 	u8         update_handle[0x18];
8364 
8365 	u8         offset[0x20];
8366 
8367 	u8         reserved_at_40[0x10];
8368 	u8         size[0x10];
8369 
8370 	u8         reserved_at_60[0x20];
8371 
8372 	u8         data[0][0x20];
8373 };
8374 
8375 union mlx5_ifc_ports_control_registers_document_bits {
8376 	struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
8377 	struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
8378 	struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
8379 	struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
8380 	struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
8381 	struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
8382 	struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
8383 	struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
8384 	struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
8385 	struct mlx5_ifc_pamp_reg_bits pamp_reg;
8386 	struct mlx5_ifc_paos_reg_bits paos_reg;
8387 	struct mlx5_ifc_pcap_reg_bits pcap_reg;
8388 	struct mlx5_ifc_peir_reg_bits peir_reg;
8389 	struct mlx5_ifc_pelc_reg_bits pelc_reg;
8390 	struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
8391 	struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
8392 	struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
8393 	struct mlx5_ifc_pifr_reg_bits pifr_reg;
8394 	struct mlx5_ifc_pipg_reg_bits pipg_reg;
8395 	struct mlx5_ifc_plbf_reg_bits plbf_reg;
8396 	struct mlx5_ifc_plib_reg_bits plib_reg;
8397 	struct mlx5_ifc_plpc_reg_bits plpc_reg;
8398 	struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
8399 	struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
8400 	struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
8401 	struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
8402 	struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
8403 	struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
8404 	struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
8405 	struct mlx5_ifc_ppad_reg_bits ppad_reg;
8406 	struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
8407 	struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
8408 	struct mlx5_ifc_pplm_reg_bits pplm_reg;
8409 	struct mlx5_ifc_pplr_reg_bits pplr_reg;
8410 	struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
8411 	struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
8412 	struct mlx5_ifc_pspa_reg_bits pspa_reg;
8413 	struct mlx5_ifc_ptas_reg_bits ptas_reg;
8414 	struct mlx5_ifc_ptys_reg_bits ptys_reg;
8415 	struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
8416 	struct mlx5_ifc_pude_reg_bits pude_reg;
8417 	struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
8418 	struct mlx5_ifc_slrg_reg_bits slrg_reg;
8419 	struct mlx5_ifc_sltp_reg_bits sltp_reg;
8420 	struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
8421 	struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
8422 	struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
8423 	struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
8424 	struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
8425 	struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
8426 	struct mlx5_ifc_mcc_reg_bits mcc_reg;
8427 	struct mlx5_ifc_mcda_reg_bits mcda_reg;
8428 	u8         reserved_at_0[0x60e0];
8429 };
8430 
8431 union mlx5_ifc_debug_enhancements_document_bits {
8432 	struct mlx5_ifc_health_buffer_bits health_buffer;
8433 	u8         reserved_at_0[0x200];
8434 };
8435 
8436 union mlx5_ifc_uplink_pci_interface_document_bits {
8437 	struct mlx5_ifc_initial_seg_bits initial_seg;
8438 	u8         reserved_at_0[0x20060];
8439 };
8440 
8441 struct mlx5_ifc_set_flow_table_root_out_bits {
8442 	u8         status[0x8];
8443 	u8         reserved_at_8[0x18];
8444 
8445 	u8         syndrome[0x20];
8446 
8447 	u8         reserved_at_40[0x40];
8448 };
8449 
8450 struct mlx5_ifc_set_flow_table_root_in_bits {
8451 	u8         opcode[0x10];
8452 	u8         reserved_at_10[0x10];
8453 
8454 	u8         reserved_at_20[0x10];
8455 	u8         op_mod[0x10];
8456 
8457 	u8         other_vport[0x1];
8458 	u8         reserved_at_41[0xf];
8459 	u8         vport_number[0x10];
8460 
8461 	u8         reserved_at_60[0x20];
8462 
8463 	u8         table_type[0x8];
8464 	u8         reserved_at_88[0x18];
8465 
8466 	u8         reserved_at_a0[0x8];
8467 	u8         table_id[0x18];
8468 
8469 	u8         reserved_at_c0[0x8];
8470 	u8         underlay_qpn[0x18];
8471 	u8         reserved_at_e0[0x120];
8472 };
8473 
8474 enum {
8475 	MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID     = (1UL << 0),
8476 	MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
8477 };
8478 
8479 struct mlx5_ifc_modify_flow_table_out_bits {
8480 	u8         status[0x8];
8481 	u8         reserved_at_8[0x18];
8482 
8483 	u8         syndrome[0x20];
8484 
8485 	u8         reserved_at_40[0x40];
8486 };
8487 
8488 struct mlx5_ifc_modify_flow_table_in_bits {
8489 	u8         opcode[0x10];
8490 	u8         reserved_at_10[0x10];
8491 
8492 	u8         reserved_at_20[0x10];
8493 	u8         op_mod[0x10];
8494 
8495 	u8         other_vport[0x1];
8496 	u8         reserved_at_41[0xf];
8497 	u8         vport_number[0x10];
8498 
8499 	u8         reserved_at_60[0x10];
8500 	u8         modify_field_select[0x10];
8501 
8502 	u8         table_type[0x8];
8503 	u8         reserved_at_88[0x18];
8504 
8505 	u8         reserved_at_a0[0x8];
8506 	u8         table_id[0x18];
8507 
8508 	struct mlx5_ifc_flow_table_context_bits flow_table_context;
8509 };
8510 
8511 struct mlx5_ifc_ets_tcn_config_reg_bits {
8512 	u8         g[0x1];
8513 	u8         b[0x1];
8514 	u8         r[0x1];
8515 	u8         reserved_at_3[0x9];
8516 	u8         group[0x4];
8517 	u8         reserved_at_10[0x9];
8518 	u8         bw_allocation[0x7];
8519 
8520 	u8         reserved_at_20[0xc];
8521 	u8         max_bw_units[0x4];
8522 	u8         reserved_at_30[0x8];
8523 	u8         max_bw_value[0x8];
8524 };
8525 
8526 struct mlx5_ifc_ets_global_config_reg_bits {
8527 	u8         reserved_at_0[0x2];
8528 	u8         r[0x1];
8529 	u8         reserved_at_3[0x1d];
8530 
8531 	u8         reserved_at_20[0xc];
8532 	u8         max_bw_units[0x4];
8533 	u8         reserved_at_30[0x8];
8534 	u8         max_bw_value[0x8];
8535 };
8536 
8537 struct mlx5_ifc_qetc_reg_bits {
8538 	u8                                         reserved_at_0[0x8];
8539 	u8                                         port_number[0x8];
8540 	u8                                         reserved_at_10[0x30];
8541 
8542 	struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
8543 	struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
8544 };
8545 
8546 struct mlx5_ifc_qtct_reg_bits {
8547 	u8         reserved_at_0[0x8];
8548 	u8         port_number[0x8];
8549 	u8         reserved_at_10[0xd];
8550 	u8         prio[0x3];
8551 
8552 	u8         reserved_at_20[0x1d];
8553 	u8         tclass[0x3];
8554 };
8555 
8556 struct mlx5_ifc_mcia_reg_bits {
8557 	u8         l[0x1];
8558 	u8         reserved_at_1[0x7];
8559 	u8         module[0x8];
8560 	u8         reserved_at_10[0x8];
8561 	u8         status[0x8];
8562 
8563 	u8         i2c_device_address[0x8];
8564 	u8         page_number[0x8];
8565 	u8         device_address[0x10];
8566 
8567 	u8         reserved_at_40[0x10];
8568 	u8         size[0x10];
8569 
8570 	u8         reserved_at_60[0x20];
8571 
8572 	u8         dword_0[0x20];
8573 	u8         dword_1[0x20];
8574 	u8         dword_2[0x20];
8575 	u8         dword_3[0x20];
8576 	u8         dword_4[0x20];
8577 	u8         dword_5[0x20];
8578 	u8         dword_6[0x20];
8579 	u8         dword_7[0x20];
8580 	u8         dword_8[0x20];
8581 	u8         dword_9[0x20];
8582 	u8         dword_10[0x20];
8583 	u8         dword_11[0x20];
8584 };
8585 
8586 struct mlx5_ifc_dcbx_param_bits {
8587 	u8         dcbx_cee_cap[0x1];
8588 	u8         dcbx_ieee_cap[0x1];
8589 	u8         dcbx_standby_cap[0x1];
8590 	u8         reserved_at_0[0x5];
8591 	u8         port_number[0x8];
8592 	u8         reserved_at_10[0xa];
8593 	u8         max_application_table_size[6];
8594 	u8         reserved_at_20[0x15];
8595 	u8         version_oper[0x3];
8596 	u8         reserved_at_38[5];
8597 	u8         version_admin[0x3];
8598 	u8         willing_admin[0x1];
8599 	u8         reserved_at_41[0x3];
8600 	u8         pfc_cap_oper[0x4];
8601 	u8         reserved_at_48[0x4];
8602 	u8         pfc_cap_admin[0x4];
8603 	u8         reserved_at_50[0x4];
8604 	u8         num_of_tc_oper[0x4];
8605 	u8         reserved_at_58[0x4];
8606 	u8         num_of_tc_admin[0x4];
8607 	u8         remote_willing[0x1];
8608 	u8         reserved_at_61[3];
8609 	u8         remote_pfc_cap[4];
8610 	u8         reserved_at_68[0x14];
8611 	u8         remote_num_of_tc[0x4];
8612 	u8         reserved_at_80[0x18];
8613 	u8         error[0x8];
8614 	u8         reserved_at_a0[0x160];
8615 };
8616 
8617 struct mlx5_ifc_lagc_bits {
8618 	u8         reserved_at_0[0x1d];
8619 	u8         lag_state[0x3];
8620 
8621 	u8         reserved_at_20[0x14];
8622 	u8         tx_remap_affinity_2[0x4];
8623 	u8         reserved_at_38[0x4];
8624 	u8         tx_remap_affinity_1[0x4];
8625 };
8626 
8627 struct mlx5_ifc_create_lag_out_bits {
8628 	u8         status[0x8];
8629 	u8         reserved_at_8[0x18];
8630 
8631 	u8         syndrome[0x20];
8632 
8633 	u8         reserved_at_40[0x40];
8634 };
8635 
8636 struct mlx5_ifc_create_lag_in_bits {
8637 	u8         opcode[0x10];
8638 	u8         reserved_at_10[0x10];
8639 
8640 	u8         reserved_at_20[0x10];
8641 	u8         op_mod[0x10];
8642 
8643 	struct mlx5_ifc_lagc_bits ctx;
8644 };
8645 
8646 struct mlx5_ifc_modify_lag_out_bits {
8647 	u8         status[0x8];
8648 	u8         reserved_at_8[0x18];
8649 
8650 	u8         syndrome[0x20];
8651 
8652 	u8         reserved_at_40[0x40];
8653 };
8654 
8655 struct mlx5_ifc_modify_lag_in_bits {
8656 	u8         opcode[0x10];
8657 	u8         reserved_at_10[0x10];
8658 
8659 	u8         reserved_at_20[0x10];
8660 	u8         op_mod[0x10];
8661 
8662 	u8         reserved_at_40[0x20];
8663 	u8         field_select[0x20];
8664 
8665 	struct mlx5_ifc_lagc_bits ctx;
8666 };
8667 
8668 struct mlx5_ifc_query_lag_out_bits {
8669 	u8         status[0x8];
8670 	u8         reserved_at_8[0x18];
8671 
8672 	u8         syndrome[0x20];
8673 
8674 	struct mlx5_ifc_lagc_bits ctx;
8675 };
8676 
8677 struct mlx5_ifc_query_lag_in_bits {
8678 	u8         opcode[0x10];
8679 	u8         reserved_at_10[0x10];
8680 
8681 	u8         reserved_at_20[0x10];
8682 	u8         op_mod[0x10];
8683 
8684 	u8         reserved_at_40[0x40];
8685 };
8686 
8687 struct mlx5_ifc_destroy_lag_out_bits {
8688 	u8         status[0x8];
8689 	u8         reserved_at_8[0x18];
8690 
8691 	u8         syndrome[0x20];
8692 
8693 	u8         reserved_at_40[0x40];
8694 };
8695 
8696 struct mlx5_ifc_destroy_lag_in_bits {
8697 	u8         opcode[0x10];
8698 	u8         reserved_at_10[0x10];
8699 
8700 	u8         reserved_at_20[0x10];
8701 	u8         op_mod[0x10];
8702 
8703 	u8         reserved_at_40[0x40];
8704 };
8705 
8706 struct mlx5_ifc_create_vport_lag_out_bits {
8707 	u8         status[0x8];
8708 	u8         reserved_at_8[0x18];
8709 
8710 	u8         syndrome[0x20];
8711 
8712 	u8         reserved_at_40[0x40];
8713 };
8714 
8715 struct mlx5_ifc_create_vport_lag_in_bits {
8716 	u8         opcode[0x10];
8717 	u8         reserved_at_10[0x10];
8718 
8719 	u8         reserved_at_20[0x10];
8720 	u8         op_mod[0x10];
8721 
8722 	u8         reserved_at_40[0x40];
8723 };
8724 
8725 struct mlx5_ifc_destroy_vport_lag_out_bits {
8726 	u8         status[0x8];
8727 	u8         reserved_at_8[0x18];
8728 
8729 	u8         syndrome[0x20];
8730 
8731 	u8         reserved_at_40[0x40];
8732 };
8733 
8734 struct mlx5_ifc_destroy_vport_lag_in_bits {
8735 	u8         opcode[0x10];
8736 	u8         reserved_at_10[0x10];
8737 
8738 	u8         reserved_at_20[0x10];
8739 	u8         op_mod[0x10];
8740 
8741 	u8         reserved_at_40[0x40];
8742 };
8743 
8744 #endif /* MLX5_IFC_H */
8745