| /sound/pci/ |
| D | intel8x0m.c | 170 unsigned long reg_offset; /* offset to bmaddr */ member
399 unsigned long port = ichdev->reg_offset; in snd_intel8x0m_setup_periods()
449 unsigned long port = ichdev->reg_offset; in snd_intel8x0m_update()
541 unsigned long port = ichdev->reg_offset; in snd_intel8x0m_pcm_trigger()
588 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb) << chip->pcm_pos_shift; in snd_intel8x0m_pcm_pointer()
983 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00); in snd_intel8x0m_chip_init()
986 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS); in snd_intel8x0m_chip_init()
989 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset, chip->ichd[i].bdbar_addr); in snd_intel8x0m_chip_init()
1001 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00); in snd_intel8x0m_free()
1004 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS); in snd_intel8x0m_free()
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| D | intel8x0.c | 353 unsigned long reg_offset; /* offset to bmaddr */ member
681 unsigned long port = ichdev->reg_offset; in snd_intel8x0_setup_periods()
752 unsigned long port = ichdev->reg_offset; in snd_intel8x0_update()
848 unsigned long port = ichdev->reg_offset; in snd_intel8x0_pcm_trigger()
885 unsigned long port = ichdev->reg_offset; in snd_intel8x0_ali_trigger()
1074 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV); in snd_intel8x0_pcm_pointer()
1075 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb); in snd_intel8x0_pcm_pointer()
1081 if (civ != igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV)) in snd_intel8x0_pcm_pointer()
1092 if (ptr1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb)) in snd_intel8x0_pcm_pointer()
2588 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00); in snd_intel8x0_chip_init()
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| D | via82xx.c | 325 unsigned int reg_offset; member
986 ((viadev->reg_offset & 0x10) == 0 ? VIA_REG_TYPE_INT_LSAMPLE : 0) | in via686_setup_format()
1051 if (chip->spdif_on && viadev->reg_offset == 0x30) in snd_via8233_playback_prepare()
1062 outb(chip->playback_volume[viadev->reg_offset / 0x10][0], in snd_via8233_playback_prepare()
1064 outb(chip->playback_volume[viadev->reg_offset / 0x10][1], in snd_via8233_playback_prepare()
1192 if (chip->spdif_on && viadev->reg_offset == 0x30) { in snd_via82xx_pcm_open()
1196 } else if (chip->dxs_fixed && viadev->reg_offset < 0x40) { in snd_via82xx_pcm_open()
1200 } else if (chip->dxs_src && viadev->reg_offset < 0x40) { in snd_via82xx_pcm_open()
1263 stream = viadev->reg_offset / 0x10; in snd_via8233_playback_open()
1357 stream = viadev->reg_offset / 0x10; in snd_via8233_playback_close()
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| D | via82xx_modem.c | 220 unsigned int reg_offset; member
833 static void init_viadev(struct via82xx_modem *chip, int idx, unsigned int reg_offset, in init_viadev() argument
836 chip->devs[idx].reg_offset = reg_offset; in init_viadev()
838 chip->devs[idx].port = chip->port + reg_offset; in init_viadev()
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| /sound/soc/codecs/ |
| D | wm8995.c | 1802 int reg_offset, ret; in wm8995_set_fll() local
1817 reg_offset = 0; in wm8995_set_fll()
1821 reg_offset = 0x20; in wm8995_set_fll()
1867 snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_1 + reg_offset, in wm8995_set_fll()
1872 snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_2 + reg_offset, in wm8995_set_fll()
1876 snd_soc_write(codec, WM8995_FLL1_CONTROL_3 + reg_offset, fll.k); in wm8995_set_fll()
1878 snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_4 + reg_offset, in wm8995_set_fll()
1882 snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_5 + reg_offset, in wm8995_set_fll()
1889 snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_1 + reg_offset, in wm8995_set_fll()
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| D | wm8994.c | 2137 int reg_offset, ret; in _wm8994_set_fll() local
2145 reg_offset = 0; in _wm8994_set_fll()
2150 reg_offset = 0x20; in _wm8994_set_fll()
2158 reg = snd_soc_read(codec, WM8994_FLL1_CONTROL_1 + reg_offset); in _wm8994_set_fll()
2214 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset, in _wm8994_set_fll()
2220 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset, in _wm8994_set_fll()
2227 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset, in _wm8994_set_fll()
2231 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_3 + reg_offset, in _wm8994_set_fll()
2234 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset, in _wm8994_set_fll()
2239 snd_soc_update_bits(codec, WM8958_FLL1_EFS_1 + reg_offset, in _wm8994_set_fll()
[all …]
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| D | rt5677.c | 5078 .reg_offset = 0,
5082 .reg_offset = 0,
5086 .reg_offset = 0,
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| /sound/soc/sh/rcar/ |
| D | gen.c | 42 unsigned int reg_offset; member
50 .reg_offset = offset, \
186 regf.reg = conf[i].reg_offset; in _rsnd_gen_regmap_init()
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| /sound/soc/rockchip/ |
| D | rockchip_i2s.c | 29 u32 reg_offset; member
369 regmap_write(i2s->grf, i2s->pins->reg_offset, val); in rockchip_i2s_hw_params()
564 .reg_offset = 0xe220,
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