| /sound/soc/intel/skylake/ |
| D | skl-sst-cldma.h | 22 #define BDL_ALIGN(x) (x >> DMA_ADDRESS_128_BITS_ALIGNMENT) argument
59 #define CL_SD_CTL_SRST(x) \ argument
60 ((x << CL_SD_CTL_SRST_SHIFT) & CL_SD_CTL_SRST_MASK)
65 #define CL_SD_CTL_RUN(x) \ argument
66 ((x << CL_SD_CTL_RUN_SHIFT) & CL_SD_CTL_RUN_MASK)
71 #define CL_SD_CTL_IOCE(x) \ argument
72 ((x << CL_SD_CTL_IOCE_SHIFT) & CL_SD_CTL_IOCE_MASK)
77 #define CL_SD_CTL_FEIE(x) \ argument
78 ((x << CL_SD_CTL_FEIE_SHIFT) & CL_SD_CTL_FEIE_MASK)
83 #define CL_SD_CTL_DEIE(x) \ argument
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| D | skl-sst-ipc.c | 30 #define IPC_GLB_TYPE(x) ((x) << IPC_GLB_TYPE_SHIFT) argument
35 #define IPC_GLB_REPLY_STATUS(x) ((x) << IPC_GLB_REPLY_STATUS_SHIFT) argument
39 #define IPC_GLB_REPLY_TYPE(x) (((x) >> IPC_GLB_REPLY_TYPE_SHIFT) \ argument
48 #define IPC_MSG_TARGET(x) (((x) & IPC_MSG_TARGET_MASK) \ argument
53 #define IPC_MSG_DIR(x) (((x) & IPC_MSG_DIR_MASK) \ argument
58 #define IPC_GLB_NOTIFY_TYPE(x) (((x) >> IPC_GLB_NOTIFY_TYPE_SHIFT) \ argument
63 #define IPC_GLB_NOTIFY_MSG_TYPE(x) (((x) >> IPC_GLB_NOTIFY_MSG_TYPE_SHIFT) \ argument
68 #define IPC_GLB_NOTIFY_RSP_TYPE(x) (((x) >> IPC_GLB_NOTIFY_RSP_SHIFT) \ argument
76 #define IPC_PPL_MEM_SIZE(x) (((x) & IPC_PPL_MEM_SIZE_MASK) \ argument
81 #define IPC_PPL_TYPE(x) (((x) & IPC_PPL_TYPE_MASK) \ argument
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| /sound/usb/ |
| D | mixer_us16x08.h | 18 #define SND_US16X08_KCBIAS(x) (((x)->private_value >> 24) & 0xff) argument
19 #define SND_US16X08_KCSTEP(x) (((x)->private_value >> 16) & 0xff) argument
20 #define SND_US16X08_KCMIN(x) (((x)->private_value >> 8) & 0xff) argument
21 #define SND_US16X08_KCMAX(x) (((x)->private_value >> 0) & 0xff) argument
34 #define MUA0(x, y) ((x)[(y) * 10 + 4]) argument
35 #define MUA1(x, y) ((x)[(y) * 10 + 5]) argument
36 #define MUA2(x, y) ((x)[(y) * 10 + 6]) argument
37 #define MUB0(x, y) ((x)[(y) * 10 + 7]) argument
38 #define MUB1(x, y) ((x)[(y) * 10 + 8]) argument
39 #define MUB2(x, y) ((x)[(y) * 10 + 9]) argument
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| /sound/soc/fsl/ |
| D | imx-ssi.h | 106 #define SSI_SRCCR_WL(x) ((((x) - 2) >> 1) << 13) argument
107 #define SSI_SRCCR_DC(x) (((x) & 0x1f) << 8) argument
108 #define SSI_SRCCR_PM(x) (((x) & 0xff) << 0) argument
116 #define SSI_STCCR_WL(x) ((((x) - 2) >> 1) << 13) argument
117 #define SSI_STCCR_DC(x) (((x) & 0x1f) << 8) argument
118 #define SSI_STCCR_PM(x) (((x) & 0xff) << 0) argument
124 #define SSI_SFCSR_RFCNT1(x) (((x) & 0xf) << 28) argument
126 #define SSI_SFCSR_TFCNT1(x) (((x) & 0xf) << 24) argument
128 #define SSI_SFCSR_RFWM1(x) (((x) & 0xf) << 20) argument
129 #define SSI_SFCSR_TFWM1(x) (((x) & 0xf) << 16) argument
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| D | fsl_ssi.h | 133 #define CCSR_SSI_SxCCR_WL(x) \ argument
134 (((((x) / 2) - 1) << CCSR_SSI_SxCCR_WL_SHIFT) & CCSR_SSI_SxCCR_WL_MASK)
137 #define CCSR_SSI_SxCCR_DC(x) \ argument
138 ((((x) - 1) << CCSR_SSI_SxCCR_DC_SHIFT) & CCSR_SSI_SxCCR_DC_MASK)
141 #define CCSR_SSI_SxCCR_PM(x) \ argument
142 ((((x) - 1) << CCSR_SSI_SxCCR_PM_SHIFT) & CCSR_SSI_SxCCR_PM_MASK)
151 #define CCSR_SSI_SFCSR_RFCNT1(x) \ argument
152 (((x) & CCSR_SSI_SFCSR_RFCNT1_MASK) >> CCSR_SSI_SFCSR_RFCNT1_SHIFT)
155 #define CCSR_SSI_SFCSR_TFCNT1(x) \ argument
156 (((x) & CCSR_SSI_SFCSR_TFCNT1_MASK) >> CCSR_SSI_SFCSR_TFCNT1_SHIFT)
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| D | fsl_sai.h | 88 #define FSL_SAI_CR3_WDFL(x) (x) argument
92 #define FSL_SAI_CR4_FRSZ(x) (((x) - 1) << 16) argument
94 #define FSL_SAI_CR4_SYWD(x) (((x) - 1) << 8) argument
102 #define FSL_SAI_CR5_WNW(x) (((x) - 1) << 24) argument
104 #define FSL_SAI_CR5_W0W(x) (((x) - 1) << 16) argument
106 #define FSL_SAI_CR5_FBT(x) ((x) << 8) argument
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| /sound/pci/au88x0/ |
| D | au8830.h | 105 #define ADB_DMA(x) (x) argument
106 #define ADB_SRCOUT(x) (x + OFFSET_SRCOUT) argument
107 #define ADB_SRCIN(x) (x + OFFSET_SRCIN) argument
108 #define ADB_MIXOUT(x) (x + OFFSET_MIXOUT) argument
109 #define ADB_MIXIN(x) (x + OFFSET_MIXIN) argument
110 #define ADB_CODECIN(x) (x + OFFSET_CODECIN) argument
111 #define ADB_CODECOUT(x) (x + OFFSET_CODECOUT) argument
112 #define ADB_SPORTIN(x) (x + OFFSET_SPORTIN) argument
113 #define ADB_SPORTOUT(x) (x + OFFSET_SPORTOUT) argument
114 #define ADB_SPDIFIN(x) (x + OFFSET_SPDIFIN) argument
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| D | au8810.h | 84 #define ADB_DMA(x) (x) argument
85 #define ADB_SRCOUT(x) (x + OFFSET_SRCOUT) argument
86 #define ADB_SRCIN(x) (x + OFFSET_SRCIN) argument
87 #define ADB_MIXOUT(x) (x + OFFSET_MIXOUT) argument
88 #define ADB_MIXIN(x) (x + OFFSET_MIXIN) argument
89 #define ADB_CODECIN(x) (x + OFFSET_CODECIN) argument
90 #define ADB_CODECOUT(x) (x + OFFSET_CODECOUT) argument
91 #define ADB_SPORTIN(x) (x + OFFSET_SPORTIN) argument
92 #define ADB_SPORTOUT(x) (x + OFFSET_SPORTOUT) argument
93 #define ADB_SPDIFOUT(x) (x + OFFSET_SPDIFOUT) argument
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| D | au8820.h | 76 #define ADB_DMA(x) (x + OFFSET_ADBDMA) argument
77 #define ADB_SRCOUT(x) (x + OFFSET_SRCOUT) argument
78 #define ADB_SRCIN(x) (x + OFFSET_SRCIN) argument
79 #define ADB_MIXOUT(x) (x + OFFSET_MIXOUT) argument
80 #define ADB_MIXIN(x) (x + OFFSET_MIXIN) argument
81 #define ADB_CODECIN(x) (x + OFFSET_CODECIN) argument
82 #define ADB_CODECOUT(x) (x + OFFSET_CODECOUT) argument
83 #define ADB_SPORTOUT(x) (x + OFFSET_SPORTOUT) argument
84 #define ADB_SPORTIN(x) (x + OFFSET_SPORTIN) /* */ argument
85 #define ADB_A3DOUT(x) (x + OFFSET_A3DOUT) /* 8 A3D blocks */ argument
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| D | au88x0_wt.h | 18 #define WT_BAR(x) (((x)&0xffe0)<<0x8) argument
19 #define WT_BANK(x) (x>>5) argument
34 #define WT_PARM(x,y) (((WT_BAR(x))+ 0x80 +(((x)&0x1f)<<2)+(y))<<2) /* 0x0200 */ argument
35 #define WT_DELAY(x,y) (((WT_BAR(x))+ 0x100 +(((x)&0x1f)<<2)+(y))<<2) /* 0x0400 */ argument
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| D | au88x0.h | 38 #define hwread(x,y) readl((x)+(y)) argument
39 #define hwwrite(x,y,z) writel((z),(x)+(y)) argument
49 #define SRC_RATIO(x,y) ((((x<<15)/y) + 1)/2) argument
86 #define VORTEX_IS_QUAD(x) ((x)->isquad) argument
88 #define IS_BAD_CHIP(x) (\ argument
89 (x->rev == 0xfe && x->device == PCI_DEVICE_ID_AUREAL_VORTEX_2) || \
90 (x->rev == 0xfe && x->device == PCI_DEVICE_ID_AUREAL_ADVANTAGE))
101 #define MIX_CAPT(x) (vortex->mixcapt[x]) argument
102 #define MIX_PLAYB(x) (vortex->mixplayb[x]) argument
103 #define MIX_SPDIF(x) (vortex->mixspdif[x]) argument
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| /sound/soc/codecs/ |
| D | tlv320dac33.h | 117 #define DAC33_ADJSTEP(x) (x << 0) argument
118 #define DAC33_ADJTHRSHLD(x) (x << 4) argument
121 #define DAC33_REFDIV(x) (x << 4) argument
150 #define DAC33_DATA_DELAY(x) (x << 2) argument
163 #define DAC33_THRREG(x) (((x) & 0x1FFF) << 3) argument
181 #define DAC33_UTM(x) (x << 0) argument
182 #define DAC33_UFM(x) (x << 2) argument
183 #define DAC33_OFM(x) (x << 4) argument
186 #define DAC33_NSM(x) (x << 0) argument
187 #define DAC33_PSM(x) (x << 2) argument
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| D | cs42l51.h | 46 #define CS42L51_MIC_POWER_CTL_SPEED(x) (((x)&3)<<5) argument
60 #define CS42L51_INTF_CTL_DAC_FORMAT(x) (((x)&7)<<3) argument
76 #define CS42L51_MIC_CTL_MICBIAS_LVL(x) (((x)&3)<<2) argument
91 #define CS42L51_ADC_INPUT_AINB_MUX(x) (((x)&3)<<6) argument
92 #define CS42L51_ADC_INPUT_AINA_MUX(x) (((x)&3)<<4) argument
99 #define CS42L51_DAC_OUT_CTL_HP_GAIN(x) (((x)&7)<<5) argument
107 #define CS42L51_DAC_CTL_DATA_SEL(x) (((x)&3)<<6) argument
111 #define CS42L51_DAC_CTL_DACSZ(x) (((x)&3)<<0) argument
117 #define CS42L51_ALC_PGX_PGX_VOL(x) (((x)&0x1f)<<0) argument
127 #define CS42L51_MIX_VOLUME(x) (((x)&0x7f)<<0) argument
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| D | ad73311.h | 47 #define REGA_DEVC(x) ((x & 0x7) << 4) argument
53 #define REGB_DIRATE(x) (x & 0x3) argument
54 #define REGB_SCDIV(x) ((x & 0x3) << 2) argument
55 #define REGB_MCDIV(x) ((x & 0x7) << 4) argument
70 #define REGD_IGS(x) (x & 0x7) argument
72 #define REGD_OGS(x) ((x & 0x7) << 4) argument
78 #define REGE_DA(x) (x & 0x1f) argument
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| D | sirf-audio-codec.h | 80 #define TX_FIFO_SC(x) (((x) & AUDIO_PORT_TX_FIFO_LEVEL_CHECK_MASK) \ argument
82 #define TX_FIFO_LC(x) (((x) & AUDIO_PORT_TX_FIFO_LEVEL_CHECK_MASK) \ argument
84 #define TX_FIFO_HC(x) (((x) & AUDIO_PORT_TX_FIFO_LEVEL_CHECK_MASK) \ argument
92 #define RX_FIFO_SC(x) (((x) & AUDIO_PORT_RX_FIFO_LEVEL_CHECK_MASK) \ argument
94 #define RX_FIFO_LC(x) (((x) & AUDIO_PORT_RX_FIFO_LEVEL_CHECK_MASK) \ argument
96 #define RX_FIFO_HC(x) (((x) & AUDIO_PORT_RX_FIFO_LEVEL_CHECK_MASK) \ argument
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| D | ad1836.h | 25 #define AD1836_MUTE_LEFT(x) (((x) * 2) - 2) argument
26 #define AD1836_MUTE_RIGHT(x) (((x) * 2) - 1) argument
28 #define AD1836_DAC_L_VOL(x) ((x) * 2) argument
29 #define AD1836_DAC_R_VOL(x) (1 + ((x) * 2)) argument
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| /sound/soc/au1x/ |
| D | psc.h | 30 #define PSC_CTRL(x) ((x)->mmio + PSC_CTRL_OFFSET) argument
31 #define PSC_SEL(x) ((x)->mmio + PSC_SEL_OFFSET) argument
32 #define I2S_STAT(x) ((x)->mmio + PSC_I2SSTAT_OFFSET) argument
33 #define I2S_CFG(x) ((x)->mmio + PSC_I2SCFG_OFFSET) argument
34 #define I2S_PCR(x) ((x)->mmio + PSC_I2SPCR_OFFSET) argument
35 #define AC97_CFG(x) ((x)->mmio + PSC_AC97CFG_OFFSET) argument
36 #define AC97_CDC(x) ((x)->mmio + PSC_AC97CDC_OFFSET) argument
37 #define AC97_EVNT(x) ((x)->mmio + PSC_AC97EVNT_OFFSET) argument
38 #define AC97_PCR(x) ((x)->mmio + PSC_AC97PCR_OFFSET) argument
39 #define AC97_RST(x) ((x)->mmio + PSC_AC97RST_OFFSET) argument
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| /sound/soc/stm/ |
| D | stm32_sai.h | 41 #define SAI_GCR_SYNCIN_SET(x) ((x) << SAI_GCR_SYNCIN_SHIFT) argument
45 #define SAI_GCR_SYNCOUT_SET(x) ((x) << SAI_GCR_SYNCOUT_SHIFT) argument
55 #define SAI_XCR1_PRTCFG_SET(x) ((x) << SAI_XCR1_PRTCFG_SHIFT) argument
59 #define SAI_XCR1_DS_SET(x) ((x) << SAI_XCR1_DS_SHIFT) argument
68 #define SAI_XCR1_SYNCEN_SET(x) ((x) << SAI_XCR1_SYNCEN_SHIFT) argument
82 #define SAI_XCR1_MCKDIV_WIDTH(x) (((x) == SAI_STM32F4) ? 4 : 6) argument
83 #define SAI_XCR1_MCKDIV_MASK(x) GENMASK((SAI_XCR1_MCKDIV_SHIFT + (x) - 1),\ argument
85 #define SAI_XCR1_MCKDIV_SET(x) ((x) << SAI_XCR1_MCKDIV_SHIFT) argument
86 #define SAI_XCR1_MCKDIV_MAX(x) ((1 << SAI_XCR1_MCKDIV_WIDTH(x)) - 1) argument
94 #define SAI_XCR2_FTH_SET(x) ((x) << SAI_XCR2_FTH_SHIFT) argument
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| /sound/pci/ice1712/ |
| D | hoontech.h | 44 #define ICE1712_STDSP24_0_BOX(r, x) r[0] = ((r[0] & ~3) | ((x)&3)) argument
45 #define ICE1712_STDSP24_0_DAREAR(r, x) r[0] = ((r[0] & ~4) | (((x)&1)<<2)) argument
46 #define ICE1712_STDSP24_1_CHN1(r, x) r[1] = ((r[1] & ~1) | ((x)&1)) argument
47 #define ICE1712_STDSP24_1_CHN2(r, x) r[1] = ((r[1] & ~2) | (((x)&1)<<1)) argument
48 #define ICE1712_STDSP24_1_CHN3(r, x) r[1] = ((r[1] & ~4) | (((x)&1)<<2)) argument
49 #define ICE1712_STDSP24_2_CHN4(r, x) r[2] = ((r[2] & ~1) | ((x)&1)) argument
50 #define ICE1712_STDSP24_2_MIDIIN(r, x) r[2] = ((r[2] & ~2) | (((x)&1)<<1)) argument
51 #define ICE1712_STDSP24_2_MIDI1(r, x) r[2] = ((r[2] & ~4) | (((x)&1)<<2)) argument
52 #define ICE1712_STDSP24_3_MIDI2(r, x) r[3] = ((r[3] & ~1) | ((x)&1)) argument
53 #define ICE1712_STDSP24_3_MUTE(r, x) r[3] = ((r[3] & ~2) | (((x)&1)<<1)) argument
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| /sound/soc/dwc/ |
| D | local.h | 35 #define LRBR_LTHR(x) (0x40 * x + 0x020) argument
36 #define RRBR_RTHR(x) (0x40 * x + 0x024) argument
37 #define RER(x) (0x40 * x + 0x028) argument
38 #define TER(x) (0x40 * x + 0x02C) argument
39 #define RCR(x) (0x40 * x + 0x030) argument
40 #define TCR(x) (0x40 * x + 0x034) argument
41 #define ISR(x) (0x40 * x + 0x038) argument
42 #define IMR(x) (0x40 * x + 0x03C) argument
43 #define ROR(x) (0x40 * x + 0x040) argument
44 #define TOR(x) (0x40 * x + 0x044) argument
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| /sound/soc/pxa/ |
| D | mmp-sspa.h | 52 #define SSPA_CTL_XFRLEN2(x) ((x) << 24) /* Transmit Frame Length in Phase 2 */ argument
54 #define SSPA_CTL_XWDLEN2(x) ((x) << 21) /* Transmit Word Length in Phase 2 */ argument
55 #define SSPA_CTL_XDATDLY(x) ((x) << 19) /* Tansmit Data Delay */ argument
57 #define SSPA_CTL_XSSZ2(x) ((x) << 16) /* Transmit Sample Audio Size */ argument
59 #define SSPA_CTL_XFRLEN1(x) ((x) << 8) /* Transmit Frame Length in Phase 1 */ argument
61 #define SSPA_CTL_XWDLEN1(x) ((x) << 5) /* Transmit Word Length in Phase 1 */ argument
63 #define SSPA_CTL_XSSZ1(x) ((x) << 0) /* XSSZ1 */ argument
80 #define SSPA_SP_FWID(x) ((x) << 20) /* Frame-Sync Width */ argument
81 #define SSPA_TXSP_FPER(x) ((x) << 4) /* Frame-Sync Active */ argument
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| /sound/soc/rockchip/ |
| D | rockchip_i2s.h | 24 #define I2S_TXCR_CSR(x) (x << I2S_TXCR_CSR_SHIFT) argument
39 #define I2S_TXCR_PBM_MODE(x) (x << I2S_TXCR_PBM_SHIFT) argument
46 #define I2S_TXCR_VDW(x) ((x - 1) << I2S_TXCR_VDW_SHIFT) argument
54 #define I2S_RXCR_CSR(x) (x << I2S_RXCR_CSR_SHIFT) argument
69 #define I2S_RXCR_PBM_MODE(x) (x << I2S_RXCR_PBM_SHIFT) argument
76 #define I2S_RXCR_VDW(x) ((x - 1) << I2S_RXCR_VDW_SHIFT) argument
84 #define I2S_CKR_TRCM(x) (x << I2S_CKR_TRCM_SHIFT) argument
104 #define I2S_CKR_MDIV(x) ((x - 1) << I2S_CKR_MDIV_SHIFT) argument
107 #define I2S_CKR_RSD(x) ((x - 1) << I2S_CKR_RSD_SHIFT) argument
110 #define I2S_CKR_TSD(x) ((x - 1) << I2S_CKR_TSD_SHIFT) argument
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| /sound/core/seq/ |
| D | seq_queue.h | 128 #define u64_div(x,y,q) do {u32 __tmp; udiv_qrnnd(q, __tmp, (x)>>32, x, y);} while (0) argument
129 #define u64_mod(x,y,r) do {u32 __tmp; udiv_qrnnd(__tmp, q, (x)>>32, x, y);} while (0) argument
130 #define u64_divmod(x,y,q,r) udiv_qrnnd(q, r, (x)>>32, x, y) argument
133 #define u64_div(x,y,q) ((q) = (u32)((u64)(x) / (u64)(y))) argument
134 #define u64_mod(x,y,r) ((r) = (u32)((u64)(x) % (u64)(y))) argument
135 #define u64_divmod(x,y,q,r) (u64_div(x,y,q), u64_mod(x,y,r)) argument
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| /sound/soc/sirf/ |
| D | sirf-usp.h | 176 #define USP_ASYNC_TIMEOUT(x) (((x)&USP_ASYNC_TIMEOUT_MASK) \ argument
202 #define TX_FIFO_SC(x) (((x) & USP_TX_FIFO_LEVEL_CHECK_MASK) \ argument
204 #define TX_FIFO_LC(x) (((x) & USP_TX_FIFO_LEVEL_CHECK_MASK) \ argument
206 #define TX_FIFO_HC(x) (((x) & USP_TX_FIFO_LEVEL_CHECK_MASK) \ argument
246 #define RX_FIFO_SC(x) (((x) & USP_RX_FIFO_LEVEL_CHECK_MASK) \ argument
248 #define RX_FIFO_LC(x) (((x) & USP_RX_FIFO_LEVEL_CHECK_MASK) \ argument
250 #define RX_FIFO_HC(x) (((x) & USP_RX_FIFO_LEVEL_CHECK_MASK) \ argument
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| /sound/soc/samsung/ |
| D | regs-i2s-v2.h | 104 #define S3C64XX_IISFIC_TX2COUNT(x) (((x) >> 24) & 0xf) argument
105 #define S3C64XX_IISFIC_TX1COUNT(x) (((x) >> 16) & 0xf) argument
109 #define S3C2412_IISFIC_TXCOUNT(x) (((x) >> 8) & 0xf) argument
110 #define S3C2412_IISFIC_RXCOUNT(x) (((x) >> 0) & 0xf) argument
113 #define S5PC1XX_IISFICS_TXCOUNT(x) (((x) >> 8) & 0x7f) argument
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