Searched refs:MIPS_CPU_VEIC (Results 1 – 3 of 3) sorted by relevance
383 #define MIPS_CPU_VEIC MBIT_ULL(20) /* CPU supports MIPSR2 external interrupt controller mode */ macro
413 # define cpu_has_veic (cpu_data[0].options & MIPS_CPU_VEIC)
715 c->options |= MIPS_CPU_VEIC; in decode_config3()