Searched refs:timer_base (Results 1 – 4 of 4) sorted by relevance
| /arch/arm/plat-orion/ |
| D | time.c | 51 static void __iomem *timer_base; variable
67 return ~readl(timer_base + TIMER0_VAL_OFF); in orion_read_sched_clock()
96 writel(delta, timer_base + TIMER1_VAL_OFF); in orion_clkevt_next_event()
101 u = readl(timer_base + TIMER_CTRL_OFF); in orion_clkevt_next_event()
103 writel(u, timer_base + TIMER_CTRL_OFF); in orion_clkevt_next_event()
118 u = readl(timer_base + TIMER_CTRL_OFF); in orion_clkevt_shutdown()
119 writel(u & ~TIMER1_EN, timer_base + TIMER_CTRL_OFF); in orion_clkevt_shutdown()
141 writel(ticks_per_jiffy - 1, timer_base + TIMER1_RELOAD_OFF); in orion_clkevt_set_periodic()
142 writel(ticks_per_jiffy - 1, timer_base + TIMER1_VAL_OFF); in orion_clkevt_set_periodic()
149 u = readl(timer_base + TIMER_CTRL_OFF); in orion_clkevt_set_periodic()
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| /arch/arm/mach-imx/ |
| D | epit.c | 61 static void __iomem *timer_base; variable
67 val = imx_readl(timer_base + EPITCR); in epit_irq_disable()
69 imx_writel(val, timer_base + EPITCR); in epit_irq_disable()
76 val = imx_readl(timer_base + EPITCR); in epit_irq_enable()
78 imx_writel(val, timer_base + EPITCR); in epit_irq_enable()
83 imx_writel(EPITSR_OCIF, timer_base + EPITSR); in epit_irq_acknowledge()
90 return clocksource_mmio_init(timer_base + EPITCNR, "epit", c, 200, 32, in epit_clocksource_init()
101 tcmp = imx_readl(timer_base + EPITCNR); in epit_set_next_event()
103 imx_writel(tcmp - evt, timer_base + EPITCMPR); in epit_set_next_event()
211 timer_base = base; in epit_timer_init()
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| /arch/cris/arch-v32/kernel/ |
| D | time.c | 174 static void __iomem *timer_base; variable
183 REG_WR(timer, timer_base, rw_tmr0_ctrl, ctrl); in crisv32_clkevt_switch_state()
195 REG_WR(timer, timer_base, rw_tmr0_div, evt); in crisv32_clkevt_next_event()
196 REG_WR(timer, timer_base, rw_tmr0_ctrl, ctrl); in crisv32_clkevt_next_event()
199 REG_WR(timer, timer_base, rw_tmr0_ctrl, ctrl); in crisv32_clkevt_next_event()
214 intr = REG_RD(timer, timer_base, r_masked_intr); in crisv32_timer_interrupt()
218 REG_WR(timer, timer_base, rw_tmr0_ctrl, ctrl); in crisv32_timer_interrupt()
219 REG_WR(timer, timer_base, rw_ack_intr, ack); in crisv32_timer_interrupt()
251 return REG_RD(timer, timer_base, r_time); in crisv32_timer_sched_clock()
262 REG_WR(timer, timer_base, rw_tmr0_ctrl, ctrl); in crisv32_timer_init()
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| /arch/arm/plat-orion/include/plat/ |
| D | time.h | 14 void orion_time_set_base(void __iomem *timer_base);
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