1/* 2 * Copyright 2012 Stefan Roese 3 * Stefan Roese <sr@denx.de> 4 * 5 * This file is dual-licensed: you can use it either under the terms 6 * of the GPL or the X11 license, at your option. Note that this dual 7 * licensing only applies to this file, and not this project as a 8 * whole. 9 * 10 * a) This library is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of the 13 * License, or (at your option) any later version. 14 * 15 * This library is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * Or, alternatively, 21 * 22 * b) Permission is hereby granted, free of charge, to any person 23 * obtaining a copy of this software and associated documentation 24 * files (the "Software"), to deal in the Software without 25 * restriction, including without limitation the rights to use, 26 * copy, modify, merge, publish, distribute, sublicense, and/or 27 * sell copies of the Software, and to permit persons to whom the 28 * Software is furnished to do so, subject to the following 29 * conditions: 30 * 31 * The above copyright notice and this permission notice shall be 32 * included in all copies or substantial portions of the Software. 33 * 34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 41 * OTHER DEALINGS IN THE SOFTWARE. 42 */ 43 44#include "skeleton.dtsi" 45 46#include <dt-bindings/thermal/thermal.h> 47 48#include <dt-bindings/clock/sun4i-a10-pll2.h> 49#include <dt-bindings/dma/sun4i-a10.h> 50 51/ { 52 interrupt-parent = <&intc>; 53 54 aliases { 55 ethernet0 = &emac; 56 }; 57 58 chosen { 59 #address-cells = <1>; 60 #size-cells = <1>; 61 ranges; 62 63 framebuffer@0 { 64 compatible = "allwinner,simple-framebuffer", 65 "simple-framebuffer"; 66 allwinner,pipeline = "de_be0-lcd0-hdmi"; 67 clocks = <&ahb_gates 36>, <&ahb_gates 43>, 68 <&ahb_gates 44>, <&de_be0_clk>, 69 <&tcon0_ch1_clk>, <&dram_gates 26>; 70 status = "disabled"; 71 }; 72 73 framebuffer@1 { 74 compatible = "allwinner,simple-framebuffer", 75 "simple-framebuffer"; 76 allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi"; 77 clocks = <&ahb_gates 36>, <&ahb_gates 43>, 78 <&ahb_gates 44>, <&ahb_gates 46>, 79 <&de_be0_clk>, <&de_fe0_clk>, <&tcon0_ch1_clk>, 80 <&dram_gates 25>, <&dram_gates 26>; 81 status = "disabled"; 82 }; 83 84 framebuffer@2 { 85 compatible = "allwinner,simple-framebuffer", 86 "simple-framebuffer"; 87 allwinner,pipeline = "de_fe0-de_be0-lcd0"; 88 clocks = <&ahb_gates 36>, <&ahb_gates 44>, <&ahb_gates 46>, 89 <&de_be0_clk>, <&de_fe0_clk>, <&tcon0_ch0_clk>, 90 <&dram_gates 25>, <&dram_gates 26>; 91 status = "disabled"; 92 }; 93 94 framebuffer@3 { 95 compatible = "allwinner,simple-framebuffer", 96 "simple-framebuffer"; 97 allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0"; 98 clocks = <&ahb_gates 34>, <&ahb_gates 36>, 99 <&ahb_gates 44>, <&ahb_gates 46>, 100 <&de_be0_clk>, <&de_fe0_clk>, 101 <&tcon0_ch1_clk>, <&dram_gates 5>, 102 <&dram_gates 25>, <&dram_gates 26>; 103 status = "disabled"; 104 }; 105 }; 106 107 cpus { 108 #address-cells = <1>; 109 #size-cells = <0>; 110 cpu0: cpu@0 { 111 device_type = "cpu"; 112 compatible = "arm,cortex-a8"; 113 reg = <0x0>; 114 clocks = <&cpu>; 115 clock-latency = <244144>; /* 8 32k periods */ 116 operating-points = < 117 /* kHz uV */ 118 1008000 1400000 119 912000 1350000 120 864000 1300000 121 624000 1250000 122 >; 123 #cooling-cells = <2>; 124 cooling-min-level = <0>; 125 cooling-max-level = <3>; 126 }; 127 }; 128 129 thermal-zones { 130 cpu_thermal { 131 /* milliseconds */ 132 polling-delay-passive = <250>; 133 polling-delay = <1000>; 134 thermal-sensors = <&rtp>; 135 136 cooling-maps { 137 map0 { 138 trip = <&cpu_alert0>; 139 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 140 }; 141 }; 142 143 trips { 144 cpu_alert0: cpu_alert0 { 145 /* milliCelsius */ 146 temperature = <850000>; 147 hysteresis = <2000>; 148 type = "passive"; 149 }; 150 151 cpu_crit: cpu_crit { 152 /* milliCelsius */ 153 temperature = <100000>; 154 hysteresis = <2000>; 155 type = "critical"; 156 }; 157 }; 158 }; 159 }; 160 161 memory { 162 reg = <0x40000000 0x80000000>; 163 }; 164 165 clocks { 166 #address-cells = <1>; 167 #size-cells = <1>; 168 ranges; 169 170 /* 171 * This is a dummy clock, to be used as placeholder on 172 * other mux clocks when a specific parent clock is not 173 * yet implemented. It should be dropped when the driver 174 * is complete. 175 */ 176 dummy: dummy { 177 #clock-cells = <0>; 178 compatible = "fixed-clock"; 179 clock-frequency = <0>; 180 }; 181 182 osc24M: clk@01c20050 { 183 #clock-cells = <0>; 184 compatible = "allwinner,sun4i-a10-osc-clk"; 185 reg = <0x01c20050 0x4>; 186 clock-frequency = <24000000>; 187 clock-output-names = "osc24M"; 188 }; 189 190 osc3M: osc3M_clk { 191 compatible = "fixed-factor-clock"; 192 #clock-cells = <0>; 193 clock-div = <8>; 194 clock-mult = <1>; 195 clocks = <&osc24M>; 196 clock-output-names = "osc3M"; 197 }; 198 199 osc32k: clk@0 { 200 #clock-cells = <0>; 201 compatible = "fixed-clock"; 202 clock-frequency = <32768>; 203 clock-output-names = "osc32k"; 204 }; 205 206 pll1: clk@01c20000 { 207 #clock-cells = <0>; 208 compatible = "allwinner,sun4i-a10-pll1-clk"; 209 reg = <0x01c20000 0x4>; 210 clocks = <&osc24M>; 211 clock-output-names = "pll1"; 212 }; 213 214 pll2: clk@01c20008 { 215 #clock-cells = <1>; 216 compatible = "allwinner,sun4i-a10-pll2-clk"; 217 reg = <0x01c20008 0x8>; 218 clocks = <&osc24M>; 219 clock-output-names = "pll2-1x", "pll2-2x", 220 "pll2-4x", "pll2-8x"; 221 }; 222 223 pll3: clk@01c20010 { 224 #clock-cells = <0>; 225 compatible = "allwinner,sun4i-a10-pll3-clk"; 226 reg = <0x01c20010 0x4>; 227 clocks = <&osc3M>; 228 clock-output-names = "pll3"; 229 }; 230 231 pll3x2: pll3x2_clk { 232 compatible = "fixed-factor-clock"; 233 #clock-cells = <0>; 234 clock-div = <1>; 235 clock-mult = <2>; 236 clocks = <&pll3>; 237 clock-output-names = "pll3-2x"; 238 }; 239 240 pll4: clk@01c20018 { 241 #clock-cells = <0>; 242 compatible = "allwinner,sun4i-a10-pll1-clk"; 243 reg = <0x01c20018 0x4>; 244 clocks = <&osc24M>; 245 clock-output-names = "pll4"; 246 }; 247 248 pll5: clk@01c20020 { 249 #clock-cells = <1>; 250 compatible = "allwinner,sun4i-a10-pll5-clk"; 251 reg = <0x01c20020 0x4>; 252 clocks = <&osc24M>; 253 clock-output-names = "pll5_ddr", "pll5_other"; 254 }; 255 256 pll6: clk@01c20028 { 257 #clock-cells = <1>; 258 compatible = "allwinner,sun4i-a10-pll6-clk"; 259 reg = <0x01c20028 0x4>; 260 clocks = <&osc24M>; 261 clock-output-names = "pll6_sata", "pll6_other", "pll6"; 262 }; 263 264 pll7: clk@01c20030 { 265 #clock-cells = <0>; 266 compatible = "allwinner,sun4i-a10-pll3-clk"; 267 reg = <0x01c20030 0x4>; 268 clocks = <&osc3M>; 269 clock-output-names = "pll7"; 270 }; 271 272 pll7x2: pll7x2_clk { 273 compatible = "fixed-factor-clock"; 274 #clock-cells = <0>; 275 clock-div = <1>; 276 clock-mult = <2>; 277 clocks = <&pll7>; 278 clock-output-names = "pll7-2x"; 279 }; 280 281 /* dummy is 200M */ 282 cpu: cpu@01c20054 { 283 #clock-cells = <0>; 284 compatible = "allwinner,sun4i-a10-cpu-clk"; 285 reg = <0x01c20054 0x4>; 286 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; 287 clock-output-names = "cpu"; 288 }; 289 290 axi: axi@01c20054 { 291 #clock-cells = <0>; 292 compatible = "allwinner,sun4i-a10-axi-clk"; 293 reg = <0x01c20054 0x4>; 294 clocks = <&cpu>; 295 clock-output-names = "axi"; 296 }; 297 298 axi_gates: clk@01c2005c { 299 #clock-cells = <1>; 300 compatible = "allwinner,sun4i-a10-axi-gates-clk"; 301 reg = <0x01c2005c 0x4>; 302 clocks = <&axi>; 303 clock-indices = <0>; 304 clock-output-names = "axi_dram"; 305 }; 306 307 ahb: ahb@01c20054 { 308 #clock-cells = <0>; 309 compatible = "allwinner,sun4i-a10-ahb-clk"; 310 reg = <0x01c20054 0x4>; 311 clocks = <&axi>; 312 clock-output-names = "ahb"; 313 }; 314 315 ahb_gates: clk@01c20060 { 316 #clock-cells = <1>; 317 compatible = "allwinner,sun4i-a10-ahb-gates-clk"; 318 reg = <0x01c20060 0x8>; 319 clocks = <&ahb>; 320 clock-indices = <0>, <1>, 321 <2>, <3>, 322 <4>, <5>, <6>, 323 <7>, <8>, <9>, 324 <10>, <11>, <12>, 325 <13>, <14>, <16>, 326 <17>, <18>, <20>, 327 <21>, <22>, <23>, 328 <24>, <25>, <26>, 329 <32>, <33>, <34>, 330 <35>, <36>, <37>, 331 <40>, <41>, <43>, 332 <44>, <45>, 333 <46>, <47>, 334 <50>, <52>; 335 clock-output-names = "ahb_usb0", "ahb_ehci0", 336 "ahb_ohci0", "ahb_ehci1", 337 "ahb_ohci1", "ahb_ss", "ahb_dma", 338 "ahb_bist", "ahb_mmc0", "ahb_mmc1", 339 "ahb_mmc2", "ahb_mmc3", "ahb_ms", 340 "ahb_nand", "ahb_sdram", "ahb_ace", 341 "ahb_emac", "ahb_ts", "ahb_spi0", 342 "ahb_spi1", "ahb_spi2", "ahb_spi3", 343 "ahb_pata", "ahb_sata", "ahb_gps", 344 "ahb_ve", "ahb_tvd", "ahb_tve0", 345 "ahb_tve1", "ahb_lcd0", "ahb_lcd1", 346 "ahb_csi0", "ahb_csi1", "ahb_hdmi", 347 "ahb_de_be0", "ahb_de_be1", 348 "ahb_de_fe0", "ahb_de_fe1", 349 "ahb_mp", "ahb_mali400"; 350 }; 351 352 apb0: apb0@01c20054 { 353 #clock-cells = <0>; 354 compatible = "allwinner,sun4i-a10-apb0-clk"; 355 reg = <0x01c20054 0x4>; 356 clocks = <&ahb>; 357 clock-output-names = "apb0"; 358 }; 359 360 apb0_gates: clk@01c20068 { 361 #clock-cells = <1>; 362 compatible = "allwinner,sun4i-a10-apb0-gates-clk"; 363 reg = <0x01c20068 0x4>; 364 clocks = <&apb0>; 365 clock-indices = <0>, <1>, 366 <2>, <3>, 367 <5>, <6>, 368 <7>, <10>; 369 clock-output-names = "apb0_codec", "apb0_spdif", 370 "apb0_ac97", "apb0_iis", 371 "apb0_pio", "apb0_ir0", 372 "apb0_ir1", "apb0_keypad"; 373 }; 374 375 apb1: clk@01c20058 { 376 #clock-cells = <0>; 377 compatible = "allwinner,sun4i-a10-apb1-clk"; 378 reg = <0x01c20058 0x4>; 379 clocks = <&osc24M>, <&pll6 1>, <&osc32k>; 380 clock-output-names = "apb1"; 381 }; 382 383 apb1_gates: clk@01c2006c { 384 #clock-cells = <1>; 385 compatible = "allwinner,sun4i-a10-apb1-gates-clk"; 386 reg = <0x01c2006c 0x4>; 387 clocks = <&apb1>; 388 clock-indices = <0>, <1>, 389 <2>, <4>, 390 <5>, <6>, 391 <7>, <16>, 392 <17>, <18>, 393 <19>, <20>, 394 <21>, <22>, 395 <23>; 396 clock-output-names = "apb1_i2c0", "apb1_i2c1", 397 "apb1_i2c2", "apb1_can", 398 "apb1_scr", "apb1_ps20", 399 "apb1_ps21", "apb1_uart0", 400 "apb1_uart1", "apb1_uart2", 401 "apb1_uart3", "apb1_uart4", 402 "apb1_uart5", "apb1_uart6", 403 "apb1_uart7"; 404 }; 405 406 nand_clk: clk@01c20080 { 407 #clock-cells = <0>; 408 compatible = "allwinner,sun4i-a10-mod0-clk"; 409 reg = <0x01c20080 0x4>; 410 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 411 clock-output-names = "nand"; 412 }; 413 414 ms_clk: clk@01c20084 { 415 #clock-cells = <0>; 416 compatible = "allwinner,sun4i-a10-mod0-clk"; 417 reg = <0x01c20084 0x4>; 418 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 419 clock-output-names = "ms"; 420 }; 421 422 mmc0_clk: clk@01c20088 { 423 #clock-cells = <1>; 424 compatible = "allwinner,sun4i-a10-mmc-clk"; 425 reg = <0x01c20088 0x4>; 426 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 427 clock-output-names = "mmc0", 428 "mmc0_output", 429 "mmc0_sample"; 430 }; 431 432 mmc1_clk: clk@01c2008c { 433 #clock-cells = <1>; 434 compatible = "allwinner,sun4i-a10-mmc-clk"; 435 reg = <0x01c2008c 0x4>; 436 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 437 clock-output-names = "mmc1", 438 "mmc1_output", 439 "mmc1_sample"; 440 }; 441 442 mmc2_clk: clk@01c20090 { 443 #clock-cells = <1>; 444 compatible = "allwinner,sun4i-a10-mmc-clk"; 445 reg = <0x01c20090 0x4>; 446 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 447 clock-output-names = "mmc2", 448 "mmc2_output", 449 "mmc2_sample"; 450 }; 451 452 mmc3_clk: clk@01c20094 { 453 #clock-cells = <1>; 454 compatible = "allwinner,sun4i-a10-mmc-clk"; 455 reg = <0x01c20094 0x4>; 456 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 457 clock-output-names = "mmc3", 458 "mmc3_output", 459 "mmc3_sample"; 460 }; 461 462 ts_clk: clk@01c20098 { 463 #clock-cells = <0>; 464 compatible = "allwinner,sun4i-a10-mod0-clk"; 465 reg = <0x01c20098 0x4>; 466 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 467 clock-output-names = "ts"; 468 }; 469 470 ss_clk: clk@01c2009c { 471 #clock-cells = <0>; 472 compatible = "allwinner,sun4i-a10-mod0-clk"; 473 reg = <0x01c2009c 0x4>; 474 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 475 clock-output-names = "ss"; 476 }; 477 478 spi0_clk: clk@01c200a0 { 479 #clock-cells = <0>; 480 compatible = "allwinner,sun4i-a10-mod0-clk"; 481 reg = <0x01c200a0 0x4>; 482 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 483 clock-output-names = "spi0"; 484 }; 485 486 spi1_clk: clk@01c200a4 { 487 #clock-cells = <0>; 488 compatible = "allwinner,sun4i-a10-mod0-clk"; 489 reg = <0x01c200a4 0x4>; 490 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 491 clock-output-names = "spi1"; 492 }; 493 494 spi2_clk: clk@01c200a8 { 495 #clock-cells = <0>; 496 compatible = "allwinner,sun4i-a10-mod0-clk"; 497 reg = <0x01c200a8 0x4>; 498 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 499 clock-output-names = "spi2"; 500 }; 501 502 pata_clk: clk@01c200ac { 503 #clock-cells = <0>; 504 compatible = "allwinner,sun4i-a10-mod0-clk"; 505 reg = <0x01c200ac 0x4>; 506 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 507 clock-output-names = "pata"; 508 }; 509 510 ir0_clk: clk@01c200b0 { 511 #clock-cells = <0>; 512 compatible = "allwinner,sun4i-a10-mod0-clk"; 513 reg = <0x01c200b0 0x4>; 514 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 515 clock-output-names = "ir0"; 516 }; 517 518 ir1_clk: clk@01c200b4 { 519 #clock-cells = <0>; 520 compatible = "allwinner,sun4i-a10-mod0-clk"; 521 reg = <0x01c200b4 0x4>; 522 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 523 clock-output-names = "ir1"; 524 }; 525 526 spdif_clk: clk@01c200c0 { 527 #clock-cells = <0>; 528 compatible = "allwinner,sun4i-a10-mod1-clk"; 529 reg = <0x01c200c0 0x4>; 530 clocks = <&pll2 SUN4I_A10_PLL2_8X>, 531 <&pll2 SUN4I_A10_PLL2_4X>, 532 <&pll2 SUN4I_A10_PLL2_2X>, 533 <&pll2 SUN4I_A10_PLL2_1X>; 534 clock-output-names = "spdif"; 535 }; 536 537 usb_clk: clk@01c200cc { 538 #clock-cells = <1>; 539 #reset-cells = <1>; 540 compatible = "allwinner,sun4i-a10-usb-clk"; 541 reg = <0x01c200cc 0x4>; 542 clocks = <&pll6 1>; 543 clock-output-names = "usb_ohci0", "usb_ohci1", 544 "usb_phy"; 545 }; 546 547 spi3_clk: clk@01c200d4 { 548 #clock-cells = <0>; 549 compatible = "allwinner,sun4i-a10-mod0-clk"; 550 reg = <0x01c200d4 0x4>; 551 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 552 clock-output-names = "spi3"; 553 }; 554 555 dram_gates: clk@01c20100 { 556 #clock-cells = <1>; 557 compatible = "allwinner,sun4i-a10-dram-gates-clk"; 558 reg = <0x01c20100 0x4>; 559 clocks = <&pll5 0>; 560 clock-indices = <0>, 561 <1>, <2>, 562 <3>, 563 <4>, 564 <5>, <6>, 565 <15>, 566 <24>, <25>, 567 <26>, <27>, 568 <28>, <29>; 569 clock-output-names = "dram_ve", 570 "dram_csi0", "dram_csi1", 571 "dram_ts", 572 "dram_tvd", 573 "dram_tve0", "dram_tve1", 574 "dram_output", 575 "dram_de_fe1", "dram_de_fe0", 576 "dram_de_be0", "dram_de_be1", 577 "dram_de_mp", "dram_ace"; 578 }; 579 580 de_be0_clk: clk@01c20104 { 581 #clock-cells = <0>; 582 #reset-cells = <0>; 583 compatible = "allwinner,sun4i-a10-display-clk"; 584 reg = <0x01c20104 0x4>; 585 clocks = <&pll3>, <&pll7>, <&pll5 1>; 586 clock-output-names = "de-be0"; 587 }; 588 589 de_be1_clk: clk@01c20108 { 590 #clock-cells = <0>; 591 #reset-cells = <0>; 592 compatible = "allwinner,sun4i-a10-display-clk"; 593 reg = <0x01c20108 0x4>; 594 clocks = <&pll3>, <&pll7>, <&pll5 1>; 595 clock-output-names = "de-be1"; 596 }; 597 598 de_fe0_clk: clk@01c2010c { 599 #clock-cells = <0>; 600 #reset-cells = <0>; 601 compatible = "allwinner,sun4i-a10-display-clk"; 602 reg = <0x01c2010c 0x4>; 603 clocks = <&pll3>, <&pll7>, <&pll5 1>; 604 clock-output-names = "de-fe0"; 605 }; 606 607 de_fe1_clk: clk@01c20110 { 608 #clock-cells = <0>; 609 #reset-cells = <0>; 610 compatible = "allwinner,sun4i-a10-display-clk"; 611 reg = <0x01c20110 0x4>; 612 clocks = <&pll3>, <&pll7>, <&pll5 1>; 613 clock-output-names = "de-fe1"; 614 }; 615 616 617 tcon0_ch0_clk: clk@01c20118 { 618 #clock-cells = <0>; 619 #reset-cells = <1>; 620 compatible = "allwinner,sun4i-a10-tcon-ch0-clk"; 621 reg = <0x01c20118 0x4>; 622 clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; 623 clock-output-names = "tcon0-ch0-sclk"; 624 625 }; 626 627 tcon1_ch0_clk: clk@01c2011c { 628 #clock-cells = <0>; 629 #reset-cells = <1>; 630 compatible = "allwinner,sun4i-a10-tcon-ch1-clk"; 631 reg = <0x01c2011c 0x4>; 632 clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; 633 clock-output-names = "tcon1-ch0-sclk"; 634 635 }; 636 637 tcon0_ch1_clk: clk@01c2012c { 638 #clock-cells = <0>; 639 compatible = "allwinner,sun4i-a10-tcon-ch0-clk"; 640 reg = <0x01c2012c 0x4>; 641 clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; 642 clock-output-names = "tcon0-ch1-sclk"; 643 644 }; 645 646 tcon1_ch1_clk: clk@01c20130 { 647 #clock-cells = <0>; 648 compatible = "allwinner,sun4i-a10-tcon-ch1-clk"; 649 reg = <0x01c20130 0x4>; 650 clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; 651 clock-output-names = "tcon1-ch1-sclk"; 652 653 }; 654 655 ve_clk: clk@01c2013c { 656 #clock-cells = <0>; 657 #reset-cells = <0>; 658 compatible = "allwinner,sun4i-a10-ve-clk"; 659 reg = <0x01c2013c 0x4>; 660 clocks = <&pll4>; 661 clock-output-names = "ve"; 662 }; 663 664 codec_clk: clk@01c20140 { 665 #clock-cells = <0>; 666 compatible = "allwinner,sun4i-a10-codec-clk"; 667 reg = <0x01c20140 0x4>; 668 clocks = <&pll2 SUN4I_A10_PLL2_1X>; 669 clock-output-names = "codec"; 670 }; 671 }; 672 673 soc@01c00000 { 674 compatible = "simple-bus"; 675 #address-cells = <1>; 676 #size-cells = <1>; 677 ranges; 678 679 sram-controller@01c00000 { 680 compatible = "allwinner,sun4i-a10-sram-controller"; 681 reg = <0x01c00000 0x30>; 682 #address-cells = <1>; 683 #size-cells = <1>; 684 ranges; 685 686 sram_a: sram@00000000 { 687 compatible = "mmio-sram"; 688 reg = <0x00000000 0xc000>; 689 #address-cells = <1>; 690 #size-cells = <1>; 691 ranges = <0 0x00000000 0xc000>; 692 693 emac_sram: sram-section@8000 { 694 compatible = "allwinner,sun4i-a10-sram-a3-a4"; 695 reg = <0x8000 0x4000>; 696 status = "disabled"; 697 }; 698 }; 699 700 sram_d: sram@00010000 { 701 compatible = "mmio-sram"; 702 reg = <0x00010000 0x1000>; 703 #address-cells = <1>; 704 #size-cells = <1>; 705 ranges = <0 0x00010000 0x1000>; 706 707 otg_sram: sram-section@0000 { 708 compatible = "allwinner,sun4i-a10-sram-d"; 709 reg = <0x0000 0x1000>; 710 status = "disabled"; 711 }; 712 }; 713 }; 714 715 dma: dma-controller@01c02000 { 716 compatible = "allwinner,sun4i-a10-dma"; 717 reg = <0x01c02000 0x1000>; 718 interrupts = <27>; 719 clocks = <&ahb_gates 6>; 720 #dma-cells = <2>; 721 }; 722 723 nfc: nand@01c03000 { 724 compatible = "allwinner,sun4i-a10-nand"; 725 reg = <0x01c03000 0x1000>; 726 interrupts = <37>; 727 clocks = <&ahb_gates 13>, <&nand_clk>; 728 clock-names = "ahb", "mod"; 729 dmas = <&dma SUN4I_DMA_DEDICATED 3>; 730 dma-names = "rxtx"; 731 status = "disabled"; 732 #address-cells = <1>; 733 #size-cells = <0>; 734 }; 735 736 spi0: spi@01c05000 { 737 compatible = "allwinner,sun4i-a10-spi"; 738 reg = <0x01c05000 0x1000>; 739 interrupts = <10>; 740 clocks = <&ahb_gates 20>, <&spi0_clk>; 741 clock-names = "ahb", "mod"; 742 dmas = <&dma SUN4I_DMA_DEDICATED 27>, 743 <&dma SUN4I_DMA_DEDICATED 26>; 744 dma-names = "rx", "tx"; 745 status = "disabled"; 746 #address-cells = <1>; 747 #size-cells = <0>; 748 }; 749 750 spi1: spi@01c06000 { 751 compatible = "allwinner,sun4i-a10-spi"; 752 reg = <0x01c06000 0x1000>; 753 interrupts = <11>; 754 clocks = <&ahb_gates 21>, <&spi1_clk>; 755 clock-names = "ahb", "mod"; 756 dmas = <&dma SUN4I_DMA_DEDICATED 9>, 757 <&dma SUN4I_DMA_DEDICATED 8>; 758 dma-names = "rx", "tx"; 759 status = "disabled"; 760 #address-cells = <1>; 761 #size-cells = <0>; 762 }; 763 764 emac: ethernet@01c0b000 { 765 compatible = "allwinner,sun4i-a10-emac"; 766 reg = <0x01c0b000 0x1000>; 767 interrupts = <55>; 768 clocks = <&ahb_gates 17>; 769 allwinner,sram = <&emac_sram 1>; 770 status = "disabled"; 771 }; 772 773 mdio: mdio@01c0b080 { 774 compatible = "allwinner,sun4i-a10-mdio"; 775 reg = <0x01c0b080 0x14>; 776 status = "disabled"; 777 #address-cells = <1>; 778 #size-cells = <0>; 779 }; 780 781 mmc0: mmc@01c0f000 { 782 compatible = "allwinner,sun4i-a10-mmc"; 783 reg = <0x01c0f000 0x1000>; 784 clocks = <&ahb_gates 8>, 785 <&mmc0_clk 0>, 786 <&mmc0_clk 1>, 787 <&mmc0_clk 2>; 788 clock-names = "ahb", 789 "mmc", 790 "output", 791 "sample"; 792 interrupts = <32>; 793 status = "disabled"; 794 #address-cells = <1>; 795 #size-cells = <0>; 796 }; 797 798 mmc1: mmc@01c10000 { 799 compatible = "allwinner,sun4i-a10-mmc"; 800 reg = <0x01c10000 0x1000>; 801 clocks = <&ahb_gates 9>, 802 <&mmc1_clk 0>, 803 <&mmc1_clk 1>, 804 <&mmc1_clk 2>; 805 clock-names = "ahb", 806 "mmc", 807 "output", 808 "sample"; 809 interrupts = <33>; 810 status = "disabled"; 811 #address-cells = <1>; 812 #size-cells = <0>; 813 }; 814 815 mmc2: mmc@01c11000 { 816 compatible = "allwinner,sun4i-a10-mmc"; 817 reg = <0x01c11000 0x1000>; 818 clocks = <&ahb_gates 10>, 819 <&mmc2_clk 0>, 820 <&mmc2_clk 1>, 821 <&mmc2_clk 2>; 822 clock-names = "ahb", 823 "mmc", 824 "output", 825 "sample"; 826 interrupts = <34>; 827 status = "disabled"; 828 #address-cells = <1>; 829 #size-cells = <0>; 830 }; 831 832 mmc3: mmc@01c12000 { 833 compatible = "allwinner,sun4i-a10-mmc"; 834 reg = <0x01c12000 0x1000>; 835 clocks = <&ahb_gates 11>, 836 <&mmc3_clk 0>, 837 <&mmc3_clk 1>, 838 <&mmc3_clk 2>; 839 clock-names = "ahb", 840 "mmc", 841 "output", 842 "sample"; 843 interrupts = <35>; 844 status = "disabled"; 845 #address-cells = <1>; 846 #size-cells = <0>; 847 }; 848 849 usb_otg: usb@01c13000 { 850 compatible = "allwinner,sun4i-a10-musb"; 851 reg = <0x01c13000 0x0400>; 852 clocks = <&ahb_gates 0>; 853 interrupts = <38>; 854 interrupt-names = "mc"; 855 phys = <&usbphy 0>; 856 phy-names = "usb"; 857 extcon = <&usbphy 0>; 858 allwinner,sram = <&otg_sram 1>; 859 status = "disabled"; 860 }; 861 862 usbphy: phy@01c13400 { 863 #phy-cells = <1>; 864 compatible = "allwinner,sun4i-a10-usb-phy"; 865 reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>; 866 reg-names = "phy_ctrl", "pmu1", "pmu2"; 867 clocks = <&usb_clk 8>; 868 clock-names = "usb_phy"; 869 resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>; 870 reset-names = "usb0_reset", "usb1_reset", "usb2_reset"; 871 status = "disabled"; 872 }; 873 874 ehci0: usb@01c14000 { 875 compatible = "allwinner,sun4i-a10-ehci", "generic-ehci"; 876 reg = <0x01c14000 0x100>; 877 interrupts = <39>; 878 clocks = <&ahb_gates 1>; 879 phys = <&usbphy 1>; 880 phy-names = "usb"; 881 status = "disabled"; 882 }; 883 884 ohci0: usb@01c14400 { 885 compatible = "allwinner,sun4i-a10-ohci", "generic-ohci"; 886 reg = <0x01c14400 0x100>; 887 interrupts = <64>; 888 clocks = <&usb_clk 6>, <&ahb_gates 2>; 889 phys = <&usbphy 1>; 890 phy-names = "usb"; 891 status = "disabled"; 892 }; 893 894 crypto: crypto-engine@01c15000 { 895 compatible = "allwinner,sun4i-a10-crypto"; 896 reg = <0x01c15000 0x1000>; 897 interrupts = <86>; 898 clocks = <&ahb_gates 5>, <&ss_clk>; 899 clock-names = "ahb", "mod"; 900 }; 901 902 spi2: spi@01c17000 { 903 compatible = "allwinner,sun4i-a10-spi"; 904 reg = <0x01c17000 0x1000>; 905 interrupts = <12>; 906 clocks = <&ahb_gates 22>, <&spi2_clk>; 907 clock-names = "ahb", "mod"; 908 dmas = <&dma SUN4I_DMA_DEDICATED 29>, 909 <&dma SUN4I_DMA_DEDICATED 28>; 910 dma-names = "rx", "tx"; 911 status = "disabled"; 912 #address-cells = <1>; 913 #size-cells = <0>; 914 }; 915 916 ahci: sata@01c18000 { 917 compatible = "allwinner,sun4i-a10-ahci"; 918 reg = <0x01c18000 0x1000>; 919 interrupts = <56>; 920 clocks = <&pll6 0>, <&ahb_gates 25>; 921 status = "disabled"; 922 }; 923 924 ehci1: usb@01c1c000 { 925 compatible = "allwinner,sun4i-a10-ehci", "generic-ehci"; 926 reg = <0x01c1c000 0x100>; 927 interrupts = <40>; 928 clocks = <&ahb_gates 3>; 929 phys = <&usbphy 2>; 930 phy-names = "usb"; 931 status = "disabled"; 932 }; 933 934 ohci1: usb@01c1c400 { 935 compatible = "allwinner,sun4i-a10-ohci", "generic-ohci"; 936 reg = <0x01c1c400 0x100>; 937 interrupts = <65>; 938 clocks = <&usb_clk 7>, <&ahb_gates 4>; 939 phys = <&usbphy 2>; 940 phy-names = "usb"; 941 status = "disabled"; 942 }; 943 944 spi3: spi@01c1f000 { 945 compatible = "allwinner,sun4i-a10-spi"; 946 reg = <0x01c1f000 0x1000>; 947 interrupts = <50>; 948 clocks = <&ahb_gates 23>, <&spi3_clk>; 949 clock-names = "ahb", "mod"; 950 dmas = <&dma SUN4I_DMA_DEDICATED 31>, 951 <&dma SUN4I_DMA_DEDICATED 30>; 952 dma-names = "rx", "tx"; 953 status = "disabled"; 954 #address-cells = <1>; 955 #size-cells = <0>; 956 }; 957 958 intc: interrupt-controller@01c20400 { 959 compatible = "allwinner,sun4i-a10-ic"; 960 reg = <0x01c20400 0x400>; 961 interrupt-controller; 962 #interrupt-cells = <1>; 963 }; 964 965 pio: pinctrl@01c20800 { 966 compatible = "allwinner,sun4i-a10-pinctrl"; 967 reg = <0x01c20800 0x400>; 968 interrupts = <28>; 969 clocks = <&apb0_gates 5>, <&osc24M>, <&osc32k>; 970 clock-names = "apb", "hosc", "losc"; 971 gpio-controller; 972 interrupt-controller; 973 #interrupt-cells = <3>; 974 #gpio-cells = <3>; 975 976 can0_pins_a: can0@0 { 977 pins = "PH20", "PH21"; 978 function = "can"; 979 }; 980 981 emac_pins_a: emac0@0 { 982 pins = "PA0", "PA1", "PA2", 983 "PA3", "PA4", "PA5", "PA6", 984 "PA7", "PA8", "PA9", "PA10", 985 "PA11", "PA12", "PA13", "PA14", 986 "PA15", "PA16"; 987 function = "emac"; 988 }; 989 990 i2c0_pins_a: i2c0@0 { 991 pins = "PB0", "PB1"; 992 function = "i2c0"; 993 }; 994 995 i2c1_pins_a: i2c1@0 { 996 pins = "PB18", "PB19"; 997 function = "i2c1"; 998 }; 999 1000 i2c2_pins_a: i2c2@0 { 1001 pins = "PB20", "PB21"; 1002 function = "i2c2"; 1003 }; 1004 1005 ir0_rx_pins_a: ir0@0 { 1006 pins = "PB4"; 1007 function = "ir0"; 1008 }; 1009 1010 ir0_tx_pins_a: ir0@1 { 1011 pins = "PB3"; 1012 function = "ir0"; 1013 }; 1014 1015 ir1_rx_pins_a: ir1@0 { 1016 pins = "PB23"; 1017 function = "ir1"; 1018 }; 1019 1020 ir1_tx_pins_a: ir1@1 { 1021 pins = "PB22"; 1022 function = "ir1"; 1023 }; 1024 1025 mmc0_pins_a: mmc0@0 { 1026 pins = "PF0", "PF1", "PF2", 1027 "PF3", "PF4", "PF5"; 1028 function = "mmc0"; 1029 drive-strength = <30>; 1030 bias-pull-up; 1031 }; 1032 1033 ps20_pins_a: ps20@0 { 1034 pins = "PI20", "PI21"; 1035 function = "ps2"; 1036 }; 1037 1038 ps21_pins_a: ps21@0 { 1039 pins = "PH12", "PH13"; 1040 function = "ps2"; 1041 }; 1042 1043 pwm0_pins_a: pwm0@0 { 1044 pins = "PB2"; 1045 function = "pwm"; 1046 }; 1047 1048 pwm1_pins_a: pwm1@0 { 1049 pins = "PI3"; 1050 function = "pwm"; 1051 }; 1052 1053 spdif_tx_pins_a: spdif@0 { 1054 pins = "PB13"; 1055 function = "spdif"; 1056 bias-pull-up; 1057 }; 1058 1059 spi0_pins_a: spi0@0 { 1060 pins = "PI11", "PI12", "PI13"; 1061 function = "spi0"; 1062 }; 1063 1064 spi0_cs0_pins_a: spi0_cs0@0 { 1065 pins = "PI10"; 1066 function = "spi0"; 1067 }; 1068 1069 spi1_pins_a: spi1@0 { 1070 pins = "PI17", "PI18", "PI19"; 1071 function = "spi1"; 1072 }; 1073 1074 spi1_cs0_pins_a: spi1_cs0@0 { 1075 pins = "PI16"; 1076 function = "spi1"; 1077 }; 1078 1079 spi2_pins_a: spi2@0 { 1080 pins = "PC20", "PC21", "PC22"; 1081 function = "spi2"; 1082 }; 1083 1084 spi2_pins_b: spi2@1 { 1085 pins = "PB15", "PB16", "PB17"; 1086 function = "spi2"; 1087 }; 1088 1089 spi2_cs0_pins_a: spi2_cs0@0 { 1090 pins = "PC19"; 1091 function = "spi2"; 1092 }; 1093 1094 spi2_cs0_pins_b: spi2_cs0@1 { 1095 pins = "PB14"; 1096 function = "spi2"; 1097 }; 1098 1099 uart0_pins_a: uart0@0 { 1100 pins = "PB22", "PB23"; 1101 function = "uart0"; 1102 }; 1103 1104 uart0_pins_b: uart0@1 { 1105 pins = "PF2", "PF4"; 1106 function = "uart0"; 1107 }; 1108 1109 uart1_pins_a: uart1@0 { 1110 pins = "PA10", "PA11"; 1111 function = "uart1"; 1112 }; 1113 }; 1114 1115 timer@01c20c00 { 1116 compatible = "allwinner,sun4i-a10-timer"; 1117 reg = <0x01c20c00 0x90>; 1118 interrupts = <22>; 1119 clocks = <&osc24M>; 1120 }; 1121 1122 wdt: watchdog@01c20c90 { 1123 compatible = "allwinner,sun4i-a10-wdt"; 1124 reg = <0x01c20c90 0x10>; 1125 }; 1126 1127 rtc: rtc@01c20d00 { 1128 compatible = "allwinner,sun4i-a10-rtc"; 1129 reg = <0x01c20d00 0x20>; 1130 interrupts = <24>; 1131 }; 1132 1133 pwm: pwm@01c20e00 { 1134 compatible = "allwinner,sun4i-a10-pwm"; 1135 reg = <0x01c20e00 0xc>; 1136 clocks = <&osc24M>; 1137 #pwm-cells = <3>; 1138 status = "disabled"; 1139 }; 1140 1141 spdif: spdif@01c21000 { 1142 #sound-dai-cells = <0>; 1143 compatible = "allwinner,sun4i-a10-spdif"; 1144 reg = <0x01c21000 0x400>; 1145 interrupts = <13>; 1146 clocks = <&apb0_gates 1>, <&spdif_clk>; 1147 clock-names = "apb", "spdif"; 1148 dmas = <&dma SUN4I_DMA_NORMAL 2>, 1149 <&dma SUN4I_DMA_NORMAL 2>; 1150 dma-names = "rx", "tx"; 1151 status = "disabled"; 1152 }; 1153 1154 ir0: ir@01c21800 { 1155 compatible = "allwinner,sun4i-a10-ir"; 1156 clocks = <&apb0_gates 6>, <&ir0_clk>; 1157 clock-names = "apb", "ir"; 1158 interrupts = <5>; 1159 reg = <0x01c21800 0x40>; 1160 status = "disabled"; 1161 }; 1162 1163 ir1: ir@01c21c00 { 1164 compatible = "allwinner,sun4i-a10-ir"; 1165 clocks = <&apb0_gates 7>, <&ir1_clk>; 1166 clock-names = "apb", "ir"; 1167 interrupts = <6>; 1168 reg = <0x01c21c00 0x40>; 1169 status = "disabled"; 1170 }; 1171 1172 lradc: lradc@01c22800 { 1173 compatible = "allwinner,sun4i-a10-lradc-keys"; 1174 reg = <0x01c22800 0x100>; 1175 interrupts = <31>; 1176 status = "disabled"; 1177 }; 1178 1179 codec: codec@01c22c00 { 1180 #sound-dai-cells = <0>; 1181 compatible = "allwinner,sun4i-a10-codec"; 1182 reg = <0x01c22c00 0x40>; 1183 interrupts = <30>; 1184 clocks = <&apb0_gates 0>, <&codec_clk>; 1185 clock-names = "apb", "codec"; 1186 dmas = <&dma SUN4I_DMA_NORMAL 19>, 1187 <&dma SUN4I_DMA_NORMAL 19>; 1188 dma-names = "rx", "tx"; 1189 status = "disabled"; 1190 }; 1191 1192 sid: eeprom@01c23800 { 1193 compatible = "allwinner,sun4i-a10-sid"; 1194 reg = <0x01c23800 0x10>; 1195 }; 1196 1197 rtp: rtp@01c25000 { 1198 compatible = "allwinner,sun4i-a10-ts"; 1199 reg = <0x01c25000 0x100>; 1200 interrupts = <29>; 1201 #thermal-sensor-cells = <0>; 1202 }; 1203 1204 uart0: serial@01c28000 { 1205 compatible = "snps,dw-apb-uart"; 1206 reg = <0x01c28000 0x400>; 1207 interrupts = <1>; 1208 reg-shift = <2>; 1209 reg-io-width = <4>; 1210 clocks = <&apb1_gates 16>; 1211 status = "disabled"; 1212 }; 1213 1214 uart1: serial@01c28400 { 1215 compatible = "snps,dw-apb-uart"; 1216 reg = <0x01c28400 0x400>; 1217 interrupts = <2>; 1218 reg-shift = <2>; 1219 reg-io-width = <4>; 1220 clocks = <&apb1_gates 17>; 1221 status = "disabled"; 1222 }; 1223 1224 uart2: serial@01c28800 { 1225 compatible = "snps,dw-apb-uart"; 1226 reg = <0x01c28800 0x400>; 1227 interrupts = <3>; 1228 reg-shift = <2>; 1229 reg-io-width = <4>; 1230 clocks = <&apb1_gates 18>; 1231 status = "disabled"; 1232 }; 1233 1234 uart3: serial@01c28c00 { 1235 compatible = "snps,dw-apb-uart"; 1236 reg = <0x01c28c00 0x400>; 1237 interrupts = <4>; 1238 reg-shift = <2>; 1239 reg-io-width = <4>; 1240 clocks = <&apb1_gates 19>; 1241 status = "disabled"; 1242 }; 1243 1244 uart4: serial@01c29000 { 1245 compatible = "snps,dw-apb-uart"; 1246 reg = <0x01c29000 0x400>; 1247 interrupts = <17>; 1248 reg-shift = <2>; 1249 reg-io-width = <4>; 1250 clocks = <&apb1_gates 20>; 1251 status = "disabled"; 1252 }; 1253 1254 uart5: serial@01c29400 { 1255 compatible = "snps,dw-apb-uart"; 1256 reg = <0x01c29400 0x400>; 1257 interrupts = <18>; 1258 reg-shift = <2>; 1259 reg-io-width = <4>; 1260 clocks = <&apb1_gates 21>; 1261 status = "disabled"; 1262 }; 1263 1264 uart6: serial@01c29800 { 1265 compatible = "snps,dw-apb-uart"; 1266 reg = <0x01c29800 0x400>; 1267 interrupts = <19>; 1268 reg-shift = <2>; 1269 reg-io-width = <4>; 1270 clocks = <&apb1_gates 22>; 1271 status = "disabled"; 1272 }; 1273 1274 uart7: serial@01c29c00 { 1275 compatible = "snps,dw-apb-uart"; 1276 reg = <0x01c29c00 0x400>; 1277 interrupts = <20>; 1278 reg-shift = <2>; 1279 reg-io-width = <4>; 1280 clocks = <&apb1_gates 23>; 1281 status = "disabled"; 1282 }; 1283 1284 ps20: ps2@01c2a000 { 1285 compatible = "allwinner,sun4i-a10-ps2"; 1286 reg = <0x01c2a000 0x400>; 1287 interrupts = <62>; 1288 clocks = <&apb1_gates 6>; 1289 status = "disabled"; 1290 }; 1291 1292 ps21: ps2@01c2a400 { 1293 compatible = "allwinner,sun4i-a10-ps2"; 1294 reg = <0x01c2a400 0x400>; 1295 interrupts = <63>; 1296 clocks = <&apb1_gates 7>; 1297 status = "disabled"; 1298 }; 1299 1300 i2c0: i2c@01c2ac00 { 1301 compatible = "allwinner,sun4i-a10-i2c"; 1302 reg = <0x01c2ac00 0x400>; 1303 interrupts = <7>; 1304 clocks = <&apb1_gates 0>; 1305 status = "disabled"; 1306 #address-cells = <1>; 1307 #size-cells = <0>; 1308 }; 1309 1310 i2c1: i2c@01c2b000 { 1311 compatible = "allwinner,sun4i-a10-i2c"; 1312 reg = <0x01c2b000 0x400>; 1313 interrupts = <8>; 1314 clocks = <&apb1_gates 1>; 1315 status = "disabled"; 1316 #address-cells = <1>; 1317 #size-cells = <0>; 1318 }; 1319 1320 i2c2: i2c@01c2b400 { 1321 compatible = "allwinner,sun4i-a10-i2c"; 1322 reg = <0x01c2b400 0x400>; 1323 interrupts = <9>; 1324 clocks = <&apb1_gates 2>; 1325 status = "disabled"; 1326 #address-cells = <1>; 1327 #size-cells = <0>; 1328 }; 1329 1330 can0: can@01c2bc00 { 1331 compatible = "allwinner,sun4i-a10-can"; 1332 reg = <0x01c2bc00 0x400>; 1333 interrupts = <26>; 1334 clocks = <&apb1_gates 4>; 1335 status = "disabled"; 1336 }; 1337 }; 1338}; 1339