1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __pio_defs_asm_h 3 #define __pio_defs_asm_h 4 5 /* 6 * This file is autogenerated from 7 * file: pio.r 8 * 9 * by ../../../tools/rdesc/bin/rdes2c -asm -outfile pio_defs_asm.h pio.r 10 * Any changes here will be lost. 11 * 12 * -*- buffer-read-only: t -*- 13 */ 14 15 #ifndef REG_FIELD 16 #define REG_FIELD( scope, reg, field, value ) \ 17 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) 18 #define REG_FIELD_X_( value, shift ) ((value) << shift) 19 #endif 20 21 #ifndef REG_STATE 22 #define REG_STATE( scope, reg, field, symbolic_value ) \ 23 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) 24 #define REG_STATE_X_( k, shift ) (k << shift) 25 #endif 26 27 #ifndef REG_MASK 28 #define REG_MASK( scope, reg, field ) \ 29 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) 30 #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) 31 #endif 32 33 #ifndef REG_LSB 34 #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb 35 #endif 36 37 #ifndef REG_BIT 38 #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit 39 #endif 40 41 #ifndef REG_ADDR 42 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) 43 #define REG_ADDR_X_( inst, offs ) ((inst) + offs) 44 #endif 45 46 #ifndef REG_ADDR_VECT 47 #define REG_ADDR_VECT( scope, inst, reg, index ) \ 48 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ 49 STRIDE_##scope##_##reg ) 50 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ 51 ((inst) + offs + (index) * stride) 52 #endif 53 54 /* Register rw_data, scope pio, type rw */ 55 #define reg_pio_rw_data_offset 64 56 57 /* Register rw_io_access0, scope pio, type rw */ 58 #define reg_pio_rw_io_access0___data___lsb 0 59 #define reg_pio_rw_io_access0___data___width 8 60 #define reg_pio_rw_io_access0_offset 0 61 62 /* Register rw_io_access1, scope pio, type rw */ 63 #define reg_pio_rw_io_access1___data___lsb 0 64 #define reg_pio_rw_io_access1___data___width 8 65 #define reg_pio_rw_io_access1_offset 4 66 67 /* Register rw_io_access2, scope pio, type rw */ 68 #define reg_pio_rw_io_access2___data___lsb 0 69 #define reg_pio_rw_io_access2___data___width 8 70 #define reg_pio_rw_io_access2_offset 8 71 72 /* Register rw_io_access3, scope pio, type rw */ 73 #define reg_pio_rw_io_access3___data___lsb 0 74 #define reg_pio_rw_io_access3___data___width 8 75 #define reg_pio_rw_io_access3_offset 12 76 77 /* Register rw_io_access4, scope pio, type rw */ 78 #define reg_pio_rw_io_access4___data___lsb 0 79 #define reg_pio_rw_io_access4___data___width 8 80 #define reg_pio_rw_io_access4_offset 16 81 82 /* Register rw_io_access5, scope pio, type rw */ 83 #define reg_pio_rw_io_access5___data___lsb 0 84 #define reg_pio_rw_io_access5___data___width 8 85 #define reg_pio_rw_io_access5_offset 20 86 87 /* Register rw_io_access6, scope pio, type rw */ 88 #define reg_pio_rw_io_access6___data___lsb 0 89 #define reg_pio_rw_io_access6___data___width 8 90 #define reg_pio_rw_io_access6_offset 24 91 92 /* Register rw_io_access7, scope pio, type rw */ 93 #define reg_pio_rw_io_access7___data___lsb 0 94 #define reg_pio_rw_io_access7___data___width 8 95 #define reg_pio_rw_io_access7_offset 28 96 97 /* Register rw_io_access8, scope pio, type rw */ 98 #define reg_pio_rw_io_access8___data___lsb 0 99 #define reg_pio_rw_io_access8___data___width 8 100 #define reg_pio_rw_io_access8_offset 32 101 102 /* Register rw_io_access9, scope pio, type rw */ 103 #define reg_pio_rw_io_access9___data___lsb 0 104 #define reg_pio_rw_io_access9___data___width 8 105 #define reg_pio_rw_io_access9_offset 36 106 107 /* Register rw_io_access10, scope pio, type rw */ 108 #define reg_pio_rw_io_access10___data___lsb 0 109 #define reg_pio_rw_io_access10___data___width 8 110 #define reg_pio_rw_io_access10_offset 40 111 112 /* Register rw_io_access11, scope pio, type rw */ 113 #define reg_pio_rw_io_access11___data___lsb 0 114 #define reg_pio_rw_io_access11___data___width 8 115 #define reg_pio_rw_io_access11_offset 44 116 117 /* Register rw_io_access12, scope pio, type rw */ 118 #define reg_pio_rw_io_access12___data___lsb 0 119 #define reg_pio_rw_io_access12___data___width 8 120 #define reg_pio_rw_io_access12_offset 48 121 122 /* Register rw_io_access13, scope pio, type rw */ 123 #define reg_pio_rw_io_access13___data___lsb 0 124 #define reg_pio_rw_io_access13___data___width 8 125 #define reg_pio_rw_io_access13_offset 52 126 127 /* Register rw_io_access14, scope pio, type rw */ 128 #define reg_pio_rw_io_access14___data___lsb 0 129 #define reg_pio_rw_io_access14___data___width 8 130 #define reg_pio_rw_io_access14_offset 56 131 132 /* Register rw_io_access15, scope pio, type rw */ 133 #define reg_pio_rw_io_access15___data___lsb 0 134 #define reg_pio_rw_io_access15___data___width 8 135 #define reg_pio_rw_io_access15_offset 60 136 137 /* Register rw_ce0_cfg, scope pio, type rw */ 138 #define reg_pio_rw_ce0_cfg___lw___lsb 0 139 #define reg_pio_rw_ce0_cfg___lw___width 6 140 #define reg_pio_rw_ce0_cfg___ew___lsb 6 141 #define reg_pio_rw_ce0_cfg___ew___width 3 142 #define reg_pio_rw_ce0_cfg___zw___lsb 9 143 #define reg_pio_rw_ce0_cfg___zw___width 3 144 #define reg_pio_rw_ce0_cfg___aw___lsb 12 145 #define reg_pio_rw_ce0_cfg___aw___width 2 146 #define reg_pio_rw_ce0_cfg___mode___lsb 14 147 #define reg_pio_rw_ce0_cfg___mode___width 2 148 #define reg_pio_rw_ce0_cfg_offset 68 149 150 /* Register rw_ce1_cfg, scope pio, type rw */ 151 #define reg_pio_rw_ce1_cfg___lw___lsb 0 152 #define reg_pio_rw_ce1_cfg___lw___width 6 153 #define reg_pio_rw_ce1_cfg___ew___lsb 6 154 #define reg_pio_rw_ce1_cfg___ew___width 3 155 #define reg_pio_rw_ce1_cfg___zw___lsb 9 156 #define reg_pio_rw_ce1_cfg___zw___width 3 157 #define reg_pio_rw_ce1_cfg___aw___lsb 12 158 #define reg_pio_rw_ce1_cfg___aw___width 2 159 #define reg_pio_rw_ce1_cfg___mode___lsb 14 160 #define reg_pio_rw_ce1_cfg___mode___width 2 161 #define reg_pio_rw_ce1_cfg_offset 72 162 163 /* Register rw_ce2_cfg, scope pio, type rw */ 164 #define reg_pio_rw_ce2_cfg___lw___lsb 0 165 #define reg_pio_rw_ce2_cfg___lw___width 6 166 #define reg_pio_rw_ce2_cfg___ew___lsb 6 167 #define reg_pio_rw_ce2_cfg___ew___width 3 168 #define reg_pio_rw_ce2_cfg___zw___lsb 9 169 #define reg_pio_rw_ce2_cfg___zw___width 3 170 #define reg_pio_rw_ce2_cfg___aw___lsb 12 171 #define reg_pio_rw_ce2_cfg___aw___width 2 172 #define reg_pio_rw_ce2_cfg___mode___lsb 14 173 #define reg_pio_rw_ce2_cfg___mode___width 2 174 #define reg_pio_rw_ce2_cfg_offset 76 175 176 /* Register rw_dout, scope pio, type rw */ 177 #define reg_pio_rw_dout___data___lsb 0 178 #define reg_pio_rw_dout___data___width 8 179 #define reg_pio_rw_dout___rd_n___lsb 8 180 #define reg_pio_rw_dout___rd_n___width 1 181 #define reg_pio_rw_dout___rd_n___bit 8 182 #define reg_pio_rw_dout___wr_n___lsb 9 183 #define reg_pio_rw_dout___wr_n___width 1 184 #define reg_pio_rw_dout___wr_n___bit 9 185 #define reg_pio_rw_dout___a0___lsb 10 186 #define reg_pio_rw_dout___a0___width 1 187 #define reg_pio_rw_dout___a0___bit 10 188 #define reg_pio_rw_dout___a1___lsb 11 189 #define reg_pio_rw_dout___a1___width 1 190 #define reg_pio_rw_dout___a1___bit 11 191 #define reg_pio_rw_dout___ce0_n___lsb 12 192 #define reg_pio_rw_dout___ce0_n___width 1 193 #define reg_pio_rw_dout___ce0_n___bit 12 194 #define reg_pio_rw_dout___ce1_n___lsb 13 195 #define reg_pio_rw_dout___ce1_n___width 1 196 #define reg_pio_rw_dout___ce1_n___bit 13 197 #define reg_pio_rw_dout___ce2_n___lsb 14 198 #define reg_pio_rw_dout___ce2_n___width 1 199 #define reg_pio_rw_dout___ce2_n___bit 14 200 #define reg_pio_rw_dout___rdy___lsb 15 201 #define reg_pio_rw_dout___rdy___width 1 202 #define reg_pio_rw_dout___rdy___bit 15 203 #define reg_pio_rw_dout_offset 80 204 205 /* Register rw_oe, scope pio, type rw */ 206 #define reg_pio_rw_oe___data___lsb 0 207 #define reg_pio_rw_oe___data___width 8 208 #define reg_pio_rw_oe___rd_n___lsb 8 209 #define reg_pio_rw_oe___rd_n___width 1 210 #define reg_pio_rw_oe___rd_n___bit 8 211 #define reg_pio_rw_oe___wr_n___lsb 9 212 #define reg_pio_rw_oe___wr_n___width 1 213 #define reg_pio_rw_oe___wr_n___bit 9 214 #define reg_pio_rw_oe___a0___lsb 10 215 #define reg_pio_rw_oe___a0___width 1 216 #define reg_pio_rw_oe___a0___bit 10 217 #define reg_pio_rw_oe___a1___lsb 11 218 #define reg_pio_rw_oe___a1___width 1 219 #define reg_pio_rw_oe___a1___bit 11 220 #define reg_pio_rw_oe___ce0_n___lsb 12 221 #define reg_pio_rw_oe___ce0_n___width 1 222 #define reg_pio_rw_oe___ce0_n___bit 12 223 #define reg_pio_rw_oe___ce1_n___lsb 13 224 #define reg_pio_rw_oe___ce1_n___width 1 225 #define reg_pio_rw_oe___ce1_n___bit 13 226 #define reg_pio_rw_oe___ce2_n___lsb 14 227 #define reg_pio_rw_oe___ce2_n___width 1 228 #define reg_pio_rw_oe___ce2_n___bit 14 229 #define reg_pio_rw_oe___rdy___lsb 15 230 #define reg_pio_rw_oe___rdy___width 1 231 #define reg_pio_rw_oe___rdy___bit 15 232 #define reg_pio_rw_oe_offset 84 233 234 /* Register rw_man_ctrl, scope pio, type rw */ 235 #define reg_pio_rw_man_ctrl___data___lsb 0 236 #define reg_pio_rw_man_ctrl___data___width 8 237 #define reg_pio_rw_man_ctrl___rd_n___lsb 8 238 #define reg_pio_rw_man_ctrl___rd_n___width 1 239 #define reg_pio_rw_man_ctrl___rd_n___bit 8 240 #define reg_pio_rw_man_ctrl___wr_n___lsb 9 241 #define reg_pio_rw_man_ctrl___wr_n___width 1 242 #define reg_pio_rw_man_ctrl___wr_n___bit 9 243 #define reg_pio_rw_man_ctrl___a0___lsb 10 244 #define reg_pio_rw_man_ctrl___a0___width 1 245 #define reg_pio_rw_man_ctrl___a0___bit 10 246 #define reg_pio_rw_man_ctrl___a1___lsb 11 247 #define reg_pio_rw_man_ctrl___a1___width 1 248 #define reg_pio_rw_man_ctrl___a1___bit 11 249 #define reg_pio_rw_man_ctrl___ce0_n___lsb 12 250 #define reg_pio_rw_man_ctrl___ce0_n___width 1 251 #define reg_pio_rw_man_ctrl___ce0_n___bit 12 252 #define reg_pio_rw_man_ctrl___ce1_n___lsb 13 253 #define reg_pio_rw_man_ctrl___ce1_n___width 1 254 #define reg_pio_rw_man_ctrl___ce1_n___bit 13 255 #define reg_pio_rw_man_ctrl___ce2_n___lsb 14 256 #define reg_pio_rw_man_ctrl___ce2_n___width 1 257 #define reg_pio_rw_man_ctrl___ce2_n___bit 14 258 #define reg_pio_rw_man_ctrl___rdy___lsb 15 259 #define reg_pio_rw_man_ctrl___rdy___width 1 260 #define reg_pio_rw_man_ctrl___rdy___bit 15 261 #define reg_pio_rw_man_ctrl_offset 88 262 263 /* Register r_din, scope pio, type r */ 264 #define reg_pio_r_din___data___lsb 0 265 #define reg_pio_r_din___data___width 8 266 #define reg_pio_r_din___rd_n___lsb 8 267 #define reg_pio_r_din___rd_n___width 1 268 #define reg_pio_r_din___rd_n___bit 8 269 #define reg_pio_r_din___wr_n___lsb 9 270 #define reg_pio_r_din___wr_n___width 1 271 #define reg_pio_r_din___wr_n___bit 9 272 #define reg_pio_r_din___a0___lsb 10 273 #define reg_pio_r_din___a0___width 1 274 #define reg_pio_r_din___a0___bit 10 275 #define reg_pio_r_din___a1___lsb 11 276 #define reg_pio_r_din___a1___width 1 277 #define reg_pio_r_din___a1___bit 11 278 #define reg_pio_r_din___ce0_n___lsb 12 279 #define reg_pio_r_din___ce0_n___width 1 280 #define reg_pio_r_din___ce0_n___bit 12 281 #define reg_pio_r_din___ce1_n___lsb 13 282 #define reg_pio_r_din___ce1_n___width 1 283 #define reg_pio_r_din___ce1_n___bit 13 284 #define reg_pio_r_din___ce2_n___lsb 14 285 #define reg_pio_r_din___ce2_n___width 1 286 #define reg_pio_r_din___ce2_n___bit 14 287 #define reg_pio_r_din___rdy___lsb 15 288 #define reg_pio_r_din___rdy___width 1 289 #define reg_pio_r_din___rdy___bit 15 290 #define reg_pio_r_din_offset 92 291 292 /* Register r_stat, scope pio, type r */ 293 #define reg_pio_r_stat___busy___lsb 0 294 #define reg_pio_r_stat___busy___width 1 295 #define reg_pio_r_stat___busy___bit 0 296 #define reg_pio_r_stat_offset 96 297 298 /* Register rw_intr_mask, scope pio, type rw */ 299 #define reg_pio_rw_intr_mask___rdy___lsb 0 300 #define reg_pio_rw_intr_mask___rdy___width 1 301 #define reg_pio_rw_intr_mask___rdy___bit 0 302 #define reg_pio_rw_intr_mask_offset 100 303 304 /* Register rw_ack_intr, scope pio, type rw */ 305 #define reg_pio_rw_ack_intr___rdy___lsb 0 306 #define reg_pio_rw_ack_intr___rdy___width 1 307 #define reg_pio_rw_ack_intr___rdy___bit 0 308 #define reg_pio_rw_ack_intr_offset 104 309 310 /* Register r_intr, scope pio, type r */ 311 #define reg_pio_r_intr___rdy___lsb 0 312 #define reg_pio_r_intr___rdy___width 1 313 #define reg_pio_r_intr___rdy___bit 0 314 #define reg_pio_r_intr_offset 108 315 316 /* Register r_masked_intr, scope pio, type r */ 317 #define reg_pio_r_masked_intr___rdy___lsb 0 318 #define reg_pio_r_masked_intr___rdy___width 1 319 #define reg_pio_r_masked_intr___rdy___bit 0 320 #define reg_pio_r_masked_intr_offset 112 321 322 323 /* Constants */ 324 #define regk_pio_a2 0x00000003 325 #define regk_pio_no 0x00000000 326 #define regk_pio_normal 0x00000000 327 #define regk_pio_rd 0x00000001 328 #define regk_pio_rw_ce0_cfg_default 0x00000000 329 #define regk_pio_rw_ce1_cfg_default 0x00000000 330 #define regk_pio_rw_ce2_cfg_default 0x00000000 331 #define regk_pio_rw_intr_mask_default 0x00000000 332 #define regk_pio_rw_man_ctrl_default 0x00000000 333 #define regk_pio_rw_oe_default 0x00000000 334 #define regk_pio_wr 0x00000002 335 #define regk_pio_wr_ce2 0x00000003 336 #define regk_pio_yes 0x00000001 337 #define regk_pio_yes_all 0x000000ff 338 #endif /* __pio_defs_asm_h */ 339