1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __timer_defs_h 3 #define __timer_defs_h 4 5 /* 6 * This file is autogenerated from 7 * file: timer.r 8 * 9 * by ../../../tools/rdesc/bin/rdes2c -outfile timer_defs.h timer.r 10 * Any changes here will be lost. 11 * 12 * -*- buffer-read-only: t -*- 13 */ 14 /* Main access macros */ 15 #ifndef REG_RD 16 #define REG_RD( scope, inst, reg ) \ 17 REG_READ( reg_##scope##_##reg, \ 18 (inst) + REG_RD_ADDR_##scope##_##reg ) 19 #endif 20 21 #ifndef REG_WR 22 #define REG_WR( scope, inst, reg, val ) \ 23 REG_WRITE( reg_##scope##_##reg, \ 24 (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 25 #endif 26 27 #ifndef REG_RD_VECT 28 #define REG_RD_VECT( scope, inst, reg, index ) \ 29 REG_READ( reg_##scope##_##reg, \ 30 (inst) + REG_RD_ADDR_##scope##_##reg + \ 31 (index) * STRIDE_##scope##_##reg ) 32 #endif 33 34 #ifndef REG_WR_VECT 35 #define REG_WR_VECT( scope, inst, reg, index, val ) \ 36 REG_WRITE( reg_##scope##_##reg, \ 37 (inst) + REG_WR_ADDR_##scope##_##reg + \ 38 (index) * STRIDE_##scope##_##reg, (val) ) 39 #endif 40 41 #ifndef REG_RD_INT 42 #define REG_RD_INT( scope, inst, reg ) \ 43 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) 44 #endif 45 46 #ifndef REG_WR_INT 47 #define REG_WR_INT( scope, inst, reg, val ) \ 48 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 49 #endif 50 51 #ifndef REG_RD_INT_VECT 52 #define REG_RD_INT_VECT( scope, inst, reg, index ) \ 53 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ 54 (index) * STRIDE_##scope##_##reg ) 55 #endif 56 57 #ifndef REG_WR_INT_VECT 58 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ 59 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ 60 (index) * STRIDE_##scope##_##reg, (val) ) 61 #endif 62 63 #ifndef REG_TYPE_CONV 64 #define REG_TYPE_CONV( type, orgtype, val ) \ 65 ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) 66 #endif 67 68 #ifndef reg_page_size 69 #define reg_page_size 8192 70 #endif 71 72 #ifndef REG_ADDR 73 #define REG_ADDR( scope, inst, reg ) \ 74 ( (inst) + REG_RD_ADDR_##scope##_##reg ) 75 #endif 76 77 #ifndef REG_ADDR_VECT 78 #define REG_ADDR_VECT( scope, inst, reg, index ) \ 79 ( (inst) + REG_RD_ADDR_##scope##_##reg + \ 80 (index) * STRIDE_##scope##_##reg ) 81 #endif 82 83 /* C-code for register scope timer */ 84 85 /* Register rw_tmr0_div, scope timer, type rw */ 86 typedef unsigned int reg_timer_rw_tmr0_div; 87 #define REG_RD_ADDR_timer_rw_tmr0_div 0 88 #define REG_WR_ADDR_timer_rw_tmr0_div 0 89 90 /* Register r_tmr0_data, scope timer, type r */ 91 typedef unsigned int reg_timer_r_tmr0_data; 92 #define REG_RD_ADDR_timer_r_tmr0_data 4 93 94 /* Register rw_tmr0_ctrl, scope timer, type rw */ 95 typedef struct { 96 unsigned int op : 2; 97 unsigned int freq : 3; 98 unsigned int dummy1 : 27; 99 } reg_timer_rw_tmr0_ctrl; 100 #define REG_RD_ADDR_timer_rw_tmr0_ctrl 8 101 #define REG_WR_ADDR_timer_rw_tmr0_ctrl 8 102 103 /* Register rw_tmr1_div, scope timer, type rw */ 104 typedef unsigned int reg_timer_rw_tmr1_div; 105 #define REG_RD_ADDR_timer_rw_tmr1_div 16 106 #define REG_WR_ADDR_timer_rw_tmr1_div 16 107 108 /* Register r_tmr1_data, scope timer, type r */ 109 typedef unsigned int reg_timer_r_tmr1_data; 110 #define REG_RD_ADDR_timer_r_tmr1_data 20 111 112 /* Register rw_tmr1_ctrl, scope timer, type rw */ 113 typedef struct { 114 unsigned int op : 2; 115 unsigned int freq : 3; 116 unsigned int dummy1 : 27; 117 } reg_timer_rw_tmr1_ctrl; 118 #define REG_RD_ADDR_timer_rw_tmr1_ctrl 24 119 #define REG_WR_ADDR_timer_rw_tmr1_ctrl 24 120 121 /* Register rs_cnt_data, scope timer, type rs */ 122 typedef struct { 123 unsigned int tmr : 24; 124 unsigned int cnt : 8; 125 } reg_timer_rs_cnt_data; 126 #define REG_RD_ADDR_timer_rs_cnt_data 32 127 128 /* Register r_cnt_data, scope timer, type r */ 129 typedef struct { 130 unsigned int tmr : 24; 131 unsigned int cnt : 8; 132 } reg_timer_r_cnt_data; 133 #define REG_RD_ADDR_timer_r_cnt_data 36 134 135 /* Register rw_cnt_cfg, scope timer, type rw */ 136 typedef struct { 137 unsigned int clk : 2; 138 unsigned int dummy1 : 30; 139 } reg_timer_rw_cnt_cfg; 140 #define REG_RD_ADDR_timer_rw_cnt_cfg 40 141 #define REG_WR_ADDR_timer_rw_cnt_cfg 40 142 143 /* Register rw_trig, scope timer, type rw */ 144 typedef unsigned int reg_timer_rw_trig; 145 #define REG_RD_ADDR_timer_rw_trig 48 146 #define REG_WR_ADDR_timer_rw_trig 48 147 148 /* Register rw_trig_cfg, scope timer, type rw */ 149 typedef struct { 150 unsigned int tmr : 2; 151 unsigned int dummy1 : 30; 152 } reg_timer_rw_trig_cfg; 153 #define REG_RD_ADDR_timer_rw_trig_cfg 52 154 #define REG_WR_ADDR_timer_rw_trig_cfg 52 155 156 /* Register r_time, scope timer, type r */ 157 typedef unsigned int reg_timer_r_time; 158 #define REG_RD_ADDR_timer_r_time 56 159 160 /* Register rw_out, scope timer, type rw */ 161 typedef struct { 162 unsigned int tmr : 2; 163 unsigned int dummy1 : 30; 164 } reg_timer_rw_out; 165 #define REG_RD_ADDR_timer_rw_out 60 166 #define REG_WR_ADDR_timer_rw_out 60 167 168 /* Register rw_wd_ctrl, scope timer, type rw */ 169 typedef struct { 170 unsigned int cnt : 8; 171 unsigned int cmd : 1; 172 unsigned int key : 7; 173 unsigned int dummy1 : 16; 174 } reg_timer_rw_wd_ctrl; 175 #define REG_RD_ADDR_timer_rw_wd_ctrl 64 176 #define REG_WR_ADDR_timer_rw_wd_ctrl 64 177 178 /* Register r_wd_stat, scope timer, type r */ 179 typedef struct { 180 unsigned int cnt : 8; 181 unsigned int cmd : 1; 182 unsigned int dummy1 : 23; 183 } reg_timer_r_wd_stat; 184 #define REG_RD_ADDR_timer_r_wd_stat 68 185 186 /* Register rw_intr_mask, scope timer, type rw */ 187 typedef struct { 188 unsigned int tmr0 : 1; 189 unsigned int tmr1 : 1; 190 unsigned int cnt : 1; 191 unsigned int trig : 1; 192 unsigned int dummy1 : 28; 193 } reg_timer_rw_intr_mask; 194 #define REG_RD_ADDR_timer_rw_intr_mask 72 195 #define REG_WR_ADDR_timer_rw_intr_mask 72 196 197 /* Register rw_ack_intr, scope timer, type rw */ 198 typedef struct { 199 unsigned int tmr0 : 1; 200 unsigned int tmr1 : 1; 201 unsigned int cnt : 1; 202 unsigned int trig : 1; 203 unsigned int dummy1 : 28; 204 } reg_timer_rw_ack_intr; 205 #define REG_RD_ADDR_timer_rw_ack_intr 76 206 #define REG_WR_ADDR_timer_rw_ack_intr 76 207 208 /* Register r_intr, scope timer, type r */ 209 typedef struct { 210 unsigned int tmr0 : 1; 211 unsigned int tmr1 : 1; 212 unsigned int cnt : 1; 213 unsigned int trig : 1; 214 unsigned int dummy1 : 28; 215 } reg_timer_r_intr; 216 #define REG_RD_ADDR_timer_r_intr 80 217 218 /* Register r_masked_intr, scope timer, type r */ 219 typedef struct { 220 unsigned int tmr0 : 1; 221 unsigned int tmr1 : 1; 222 unsigned int cnt : 1; 223 unsigned int trig : 1; 224 unsigned int dummy1 : 28; 225 } reg_timer_r_masked_intr; 226 #define REG_RD_ADDR_timer_r_masked_intr 84 227 228 /* Register rw_test, scope timer, type rw */ 229 typedef struct { 230 unsigned int dis : 1; 231 unsigned int en : 1; 232 unsigned int dummy1 : 30; 233 } reg_timer_rw_test; 234 #define REG_RD_ADDR_timer_rw_test 88 235 #define REG_WR_ADDR_timer_rw_test 88 236 237 238 /* Constants */ 239 enum { 240 regk_timer_ext = 0x00000001, 241 regk_timer_f100 = 0x00000007, 242 regk_timer_f29_493 = 0x00000004, 243 regk_timer_f32 = 0x00000005, 244 regk_timer_f32_768 = 0x00000006, 245 regk_timer_f90 = 0x00000003, 246 regk_timer_hold = 0x00000001, 247 regk_timer_ld = 0x00000000, 248 regk_timer_no = 0x00000000, 249 regk_timer_off = 0x00000000, 250 regk_timer_run = 0x00000002, 251 regk_timer_rw_cnt_cfg_default = 0x00000000, 252 regk_timer_rw_intr_mask_default = 0x00000000, 253 regk_timer_rw_out_default = 0x00000000, 254 regk_timer_rw_test_default = 0x00000000, 255 regk_timer_rw_tmr0_ctrl_default = 0x00000000, 256 regk_timer_rw_tmr1_ctrl_default = 0x00000000, 257 regk_timer_rw_trig_cfg_default = 0x00000000, 258 regk_timer_start = 0x00000001, 259 regk_timer_stop = 0x00000000, 260 regk_timer_time = 0x00000001, 261 regk_timer_tmr0 = 0x00000002, 262 regk_timer_tmr1 = 0x00000003, 263 regk_timer_vclk = 0x00000002, 264 regk_timer_yes = 0x00000001 265 }; 266 #endif /* __timer_defs_h */ 267