README.openrisc
1OpenRISC Linux
2==============
3
4This is a port of Linux to the OpenRISC class of microprocessors; the initial
5target architecture, specifically, is the 32-bit OpenRISC 1000 family (or1k).
6
7For information about OpenRISC processors and ongoing development:
8
9 website http://openrisc.io
10
11For more information about Linux on OpenRISC, please contact South Pole AB.
12
13 email: info@southpole.se
14
15 website: http://southpole.se
16 http://southpoleconsulting.com
17
18---------------------------------------------------------------------
19
20Build instructions for OpenRISC toolchain and Linux
21===================================================
22
23In order to build and run Linux for OpenRISC, you'll need at least a basic
24toolchain and, perhaps, the architectural simulator. Steps to get these bits
25in place are outlined here.
26
271) The toolchain can be obtained from openrisc.io. Instructions for building
28a toolchain can be found at:
29
30https://github.com/openrisc/tutorials
31
322) or1ksim (optional)
33
34or1ksim is the architectural simulator which will allow you to actually run
35your OpenRISC Linux kernel if you don't have an OpenRISC processor at hand.
36
37 git clone https://github.com/openrisc/or1ksim.git
38
39 cd or1ksim
40 ./configure --prefix=$OPENRISC_PREFIX
41 make
42 make install
43
443) Linux kernel
45
46Build the kernel as usual
47
48 make ARCH=openrisc defconfig
49 make ARCH=openrisc
50
514) Run in architectural simulator
52
53Grab the or1ksim platform configuration file (from the or1ksim source) and
54together with your freshly built vmlinux, run your kernel with the following
55incantation:
56
57 sim -f arch/openrisc/or1ksim.cfg vmlinux
58
59---------------------------------------------------------------------
60
61Terminology
62===========
63
64In the code, the following particles are used on symbols to limit the scope
65to more or less specific processor implementations:
66
67openrisc: the OpenRISC class of processors
68or1k: the OpenRISC 1000 family of processors
69or1200: the OpenRISC 1200 processor
70
71---------------------------------------------------------------------
72
73History
74========
75
7618. 11. 2003 Matjaz Breskvar (phoenix@bsemi.com)
77 initial port of linux to OpenRISC/or32 architecture.
78 all the core stuff is implemented and seams usable.
79
8008. 12. 2003 Matjaz Breskvar (phoenix@bsemi.com)
81 complete change of TLB miss handling.
82 rewrite of exceptions handling.
83 fully functional sash-3.6 in default initrd.
84 a much improved version with changes all around.
85
8610. 04. 2004 Matjaz Breskvar (phoenix@bsemi.com)
87 alot of bugfixes all over.
88 ethernet support, functional http and telnet servers.
89 running many standard linux apps.
90
9126. 06. 2004 Matjaz Breskvar (phoenix@bsemi.com)
92 port to 2.6.x
93
9430. 11. 2004 Matjaz Breskvar (phoenix@bsemi.com)
95 lots of bugfixes and enhancments.
96 added opencores framebuffer driver.
97
9809. 10. 2010 Jonas Bonn (jonas@southpole.se)
99 major rewrite to bring up to par with upstream Linux 2.6.36
100