1 /*
2 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 */
10
11 #include <linux/clk-provider.h>
12 #include <linux/clkdev.h>
13 #include <linux/clk/at91_pmc.h>
14 #include <linux/of.h>
15 #include <linux/mfd/syscon.h>
16 #include <linux/regmap.h>
17
18 #include "pmc.h"
19
20 #define PLL_STATUS_MASK(id) (1 << (1 + (id)))
21 #define PLL_REG(id) (AT91_CKGR_PLLAR + ((id) * 4))
22 #define PLL_DIV_MASK 0xff
23 #define PLL_DIV_MAX PLL_DIV_MASK
24 #define PLL_DIV(reg) ((reg) & PLL_DIV_MASK)
25 #define PLL_MUL(reg, layout) (((reg) >> (layout)->mul_shift) & \
26 (layout)->mul_mask)
27 #define PLL_MUL_MIN 2
28 #define PLL_MUL_MASK(layout) ((layout)->mul_mask)
29 #define PLL_MUL_MAX(layout) (PLL_MUL_MASK(layout) + 1)
30 #define PLL_ICPR_SHIFT(id) ((id) * 16)
31 #define PLL_ICPR_MASK(id) (0xffff << PLL_ICPR_SHIFT(id))
32 #define PLL_MAX_COUNT 0x3f
33 #define PLL_COUNT_SHIFT 8
34 #define PLL_OUT_SHIFT 14
35 #define PLL_MAX_ID 1
36
37 struct clk_pll_characteristics {
38 struct clk_range input;
39 int num_output;
40 struct clk_range *output;
41 u16 *icpll;
42 u8 *out;
43 };
44
45 struct clk_pll_layout {
46 u32 pllr_mask;
47 u16 mul_mask;
48 u8 mul_shift;
49 };
50
51 #define to_clk_pll(hw) container_of(hw, struct clk_pll, hw)
52
53 struct clk_pll {
54 struct clk_hw hw;
55 struct regmap *regmap;
56 u8 id;
57 u8 div;
58 u8 range;
59 u16 mul;
60 const struct clk_pll_layout *layout;
61 const struct clk_pll_characteristics *characteristics;
62 };
63
clk_pll_ready(struct regmap * regmap,int id)64 static inline bool clk_pll_ready(struct regmap *regmap, int id)
65 {
66 unsigned int status;
67
68 regmap_read(regmap, AT91_PMC_SR, &status);
69
70 return status & PLL_STATUS_MASK(id) ? 1 : 0;
71 }
72
clk_pll_prepare(struct clk_hw * hw)73 static int clk_pll_prepare(struct clk_hw *hw)
74 {
75 struct clk_pll *pll = to_clk_pll(hw);
76 struct regmap *regmap = pll->regmap;
77 const struct clk_pll_layout *layout = pll->layout;
78 const struct clk_pll_characteristics *characteristics =
79 pll->characteristics;
80 u8 id = pll->id;
81 u32 mask = PLL_STATUS_MASK(id);
82 int offset = PLL_REG(id);
83 u8 out = 0;
84 unsigned int pllr;
85 unsigned int status;
86 u8 div;
87 u16 mul;
88
89 regmap_read(regmap, offset, &pllr);
90 div = PLL_DIV(pllr);
91 mul = PLL_MUL(pllr, layout);
92
93 regmap_read(regmap, AT91_PMC_SR, &status);
94 if ((status & mask) &&
95 (div == pll->div && mul == pll->mul))
96 return 0;
97
98 if (characteristics->out)
99 out = characteristics->out[pll->range];
100
101 if (characteristics->icpll)
102 regmap_update_bits(regmap, AT91_PMC_PLLICPR, PLL_ICPR_MASK(id),
103 characteristics->icpll[pll->range] << PLL_ICPR_SHIFT(id));
104
105 regmap_update_bits(regmap, offset, layout->pllr_mask,
106 pll->div | (PLL_MAX_COUNT << PLL_COUNT_SHIFT) |
107 (out << PLL_OUT_SHIFT) |
108 ((pll->mul & layout->mul_mask) << layout->mul_shift));
109
110 while (!clk_pll_ready(regmap, pll->id))
111 cpu_relax();
112
113 return 0;
114 }
115
clk_pll_is_prepared(struct clk_hw * hw)116 static int clk_pll_is_prepared(struct clk_hw *hw)
117 {
118 struct clk_pll *pll = to_clk_pll(hw);
119
120 return clk_pll_ready(pll->regmap, pll->id);
121 }
122
clk_pll_unprepare(struct clk_hw * hw)123 static void clk_pll_unprepare(struct clk_hw *hw)
124 {
125 struct clk_pll *pll = to_clk_pll(hw);
126 unsigned int mask = pll->layout->pllr_mask;
127
128 regmap_update_bits(pll->regmap, PLL_REG(pll->id), mask, ~mask);
129 }
130
clk_pll_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)131 static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
132 unsigned long parent_rate)
133 {
134 struct clk_pll *pll = to_clk_pll(hw);
135
136 if (!pll->div || !pll->mul)
137 return 0;
138
139 return (parent_rate / pll->div) * (pll->mul + 1);
140 }
141
clk_pll_get_best_div_mul(struct clk_pll * pll,unsigned long rate,unsigned long parent_rate,u32 * div,u32 * mul,u32 * index)142 static long clk_pll_get_best_div_mul(struct clk_pll *pll, unsigned long rate,
143 unsigned long parent_rate,
144 u32 *div, u32 *mul,
145 u32 *index) {
146 const struct clk_pll_layout *layout = pll->layout;
147 const struct clk_pll_characteristics *characteristics =
148 pll->characteristics;
149 unsigned long bestremainder = ULONG_MAX;
150 unsigned long maxdiv, mindiv, tmpdiv;
151 long bestrate = -ERANGE;
152 unsigned long bestdiv;
153 unsigned long bestmul;
154 int i = 0;
155
156 /* Check if parent_rate is a valid input rate */
157 if (parent_rate < characteristics->input.min)
158 return -ERANGE;
159
160 /*
161 * Calculate minimum divider based on the minimum multiplier, the
162 * parent_rate and the requested rate.
163 * Should always be 2 according to the input and output characteristics
164 * of the PLL blocks.
165 */
166 mindiv = (parent_rate * PLL_MUL_MIN) / rate;
167 if (!mindiv)
168 mindiv = 1;
169
170 if (parent_rate > characteristics->input.max) {
171 tmpdiv = DIV_ROUND_UP(parent_rate, characteristics->input.max);
172 if (tmpdiv > PLL_DIV_MAX)
173 return -ERANGE;
174
175 if (tmpdiv > mindiv)
176 mindiv = tmpdiv;
177 }
178
179 /*
180 * Calculate the maximum divider which is limited by PLL register
181 * layout (limited by the MUL or DIV field size).
182 */
183 maxdiv = DIV_ROUND_UP(parent_rate * PLL_MUL_MAX(layout), rate);
184 if (maxdiv > PLL_DIV_MAX)
185 maxdiv = PLL_DIV_MAX;
186
187 /*
188 * Iterate over the acceptable divider values to find the best
189 * divider/multiplier pair (the one that generates the closest
190 * rate to the requested one).
191 */
192 for (tmpdiv = mindiv; tmpdiv <= maxdiv; tmpdiv++) {
193 unsigned long remainder;
194 unsigned long tmprate;
195 unsigned long tmpmul;
196
197 /*
198 * Calculate the multiplier associated with the current
199 * divider that provide the closest rate to the requested one.
200 */
201 tmpmul = DIV_ROUND_CLOSEST(rate, parent_rate / tmpdiv);
202 tmprate = (parent_rate / tmpdiv) * tmpmul;
203 if (tmprate > rate)
204 remainder = tmprate - rate;
205 else
206 remainder = rate - tmprate;
207
208 /*
209 * Compare the remainder with the best remainder found until
210 * now and elect a new best multiplier/divider pair if the
211 * current remainder is smaller than the best one.
212 */
213 if (remainder < bestremainder) {
214 bestremainder = remainder;
215 bestdiv = tmpdiv;
216 bestmul = tmpmul;
217 bestrate = tmprate;
218 }
219
220 /*
221 * We've found a perfect match!
222 * Stop searching now and use this multiplier/divider pair.
223 */
224 if (!remainder)
225 break;
226 }
227
228 /* We haven't found any multiplier/divider pair => return -ERANGE */
229 if (bestrate < 0)
230 return bestrate;
231
232 /* Check if bestrate is a valid output rate */
233 for (i = 0; i < characteristics->num_output; i++) {
234 if (bestrate >= characteristics->output[i].min &&
235 bestrate <= characteristics->output[i].max)
236 break;
237 }
238
239 if (i >= characteristics->num_output)
240 return -ERANGE;
241
242 if (div)
243 *div = bestdiv;
244 if (mul)
245 *mul = bestmul - 1;
246 if (index)
247 *index = i;
248
249 return bestrate;
250 }
251
clk_pll_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * parent_rate)252 static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
253 unsigned long *parent_rate)
254 {
255 struct clk_pll *pll = to_clk_pll(hw);
256
257 return clk_pll_get_best_div_mul(pll, rate, *parent_rate,
258 NULL, NULL, NULL);
259 }
260
clk_pll_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)261 static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
262 unsigned long parent_rate)
263 {
264 struct clk_pll *pll = to_clk_pll(hw);
265 long ret;
266 u32 div;
267 u32 mul;
268 u32 index;
269
270 ret = clk_pll_get_best_div_mul(pll, rate, parent_rate,
271 &div, &mul, &index);
272 if (ret < 0)
273 return ret;
274
275 pll->range = index;
276 pll->div = div;
277 pll->mul = mul;
278
279 return 0;
280 }
281
282 static const struct clk_ops pll_ops = {
283 .prepare = clk_pll_prepare,
284 .unprepare = clk_pll_unprepare,
285 .is_prepared = clk_pll_is_prepared,
286 .recalc_rate = clk_pll_recalc_rate,
287 .round_rate = clk_pll_round_rate,
288 .set_rate = clk_pll_set_rate,
289 };
290
291 static struct clk_hw * __init
at91_clk_register_pll(struct regmap * regmap,const char * name,const char * parent_name,u8 id,const struct clk_pll_layout * layout,const struct clk_pll_characteristics * characteristics)292 at91_clk_register_pll(struct regmap *regmap, const char *name,
293 const char *parent_name, u8 id,
294 const struct clk_pll_layout *layout,
295 const struct clk_pll_characteristics *characteristics)
296 {
297 struct clk_pll *pll;
298 struct clk_hw *hw;
299 struct clk_init_data init;
300 int offset = PLL_REG(id);
301 unsigned int pllr;
302 int ret;
303
304 if (id > PLL_MAX_ID)
305 return ERR_PTR(-EINVAL);
306
307 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
308 if (!pll)
309 return ERR_PTR(-ENOMEM);
310
311 init.name = name;
312 init.ops = &pll_ops;
313 init.parent_names = &parent_name;
314 init.num_parents = 1;
315 init.flags = CLK_SET_RATE_GATE;
316
317 pll->id = id;
318 pll->hw.init = &init;
319 pll->layout = layout;
320 pll->characteristics = characteristics;
321 pll->regmap = regmap;
322 regmap_read(regmap, offset, &pllr);
323 pll->div = PLL_DIV(pllr);
324 pll->mul = PLL_MUL(pllr, layout);
325
326 hw = &pll->hw;
327 ret = clk_hw_register(NULL, &pll->hw);
328 if (ret) {
329 kfree(pll);
330 hw = ERR_PTR(ret);
331 }
332
333 return hw;
334 }
335
336
337 static const struct clk_pll_layout at91rm9200_pll_layout = {
338 .pllr_mask = 0x7FFFFFF,
339 .mul_shift = 16,
340 .mul_mask = 0x7FF,
341 };
342
343 static const struct clk_pll_layout at91sam9g45_pll_layout = {
344 .pllr_mask = 0xFFFFFF,
345 .mul_shift = 16,
346 .mul_mask = 0xFF,
347 };
348
349 static const struct clk_pll_layout at91sam9g20_pllb_layout = {
350 .pllr_mask = 0x3FFFFF,
351 .mul_shift = 16,
352 .mul_mask = 0x3F,
353 };
354
355 static const struct clk_pll_layout sama5d3_pll_layout = {
356 .pllr_mask = 0x1FFFFFF,
357 .mul_shift = 18,
358 .mul_mask = 0x7F,
359 };
360
361
362 static struct clk_pll_characteristics * __init
of_at91_clk_pll_get_characteristics(struct device_node * np)363 of_at91_clk_pll_get_characteristics(struct device_node *np)
364 {
365 int i;
366 int offset;
367 u32 tmp;
368 int num_output;
369 u32 num_cells;
370 struct clk_range input;
371 struct clk_range *output;
372 u8 *out = NULL;
373 u16 *icpll = NULL;
374 struct clk_pll_characteristics *characteristics;
375
376 if (of_at91_get_clk_range(np, "atmel,clk-input-range", &input))
377 return NULL;
378
379 if (of_property_read_u32(np, "#atmel,pll-clk-output-range-cells",
380 &num_cells))
381 return NULL;
382
383 if (num_cells < 2 || num_cells > 4)
384 return NULL;
385
386 if (!of_get_property(np, "atmel,pll-clk-output-ranges", &tmp))
387 return NULL;
388 num_output = tmp / (sizeof(u32) * num_cells);
389
390 characteristics = kzalloc(sizeof(*characteristics), GFP_KERNEL);
391 if (!characteristics)
392 return NULL;
393
394 output = kcalloc(num_output, sizeof(*output), GFP_KERNEL);
395 if (!output)
396 goto out_free_characteristics;
397
398 if (num_cells > 2) {
399 out = kcalloc(num_output, sizeof(*out), GFP_KERNEL);
400 if (!out)
401 goto out_free_output;
402 }
403
404 if (num_cells > 3) {
405 icpll = kcalloc(num_output, sizeof(*icpll), GFP_KERNEL);
406 if (!icpll)
407 goto out_free_output;
408 }
409
410 for (i = 0; i < num_output; i++) {
411 offset = i * num_cells;
412 if (of_property_read_u32_index(np,
413 "atmel,pll-clk-output-ranges",
414 offset, &tmp))
415 goto out_free_output;
416 output[i].min = tmp;
417 if (of_property_read_u32_index(np,
418 "atmel,pll-clk-output-ranges",
419 offset + 1, &tmp))
420 goto out_free_output;
421 output[i].max = tmp;
422
423 if (num_cells == 2)
424 continue;
425
426 if (of_property_read_u32_index(np,
427 "atmel,pll-clk-output-ranges",
428 offset + 2, &tmp))
429 goto out_free_output;
430 out[i] = tmp;
431
432 if (num_cells == 3)
433 continue;
434
435 if (of_property_read_u32_index(np,
436 "atmel,pll-clk-output-ranges",
437 offset + 3, &tmp))
438 goto out_free_output;
439 icpll[i] = tmp;
440 }
441
442 characteristics->input = input;
443 characteristics->num_output = num_output;
444 characteristics->output = output;
445 characteristics->out = out;
446 characteristics->icpll = icpll;
447 return characteristics;
448
449 out_free_output:
450 kfree(icpll);
451 kfree(out);
452 kfree(output);
453 out_free_characteristics:
454 kfree(characteristics);
455 return NULL;
456 }
457
458 static void __init
of_at91_clk_pll_setup(struct device_node * np,const struct clk_pll_layout * layout)459 of_at91_clk_pll_setup(struct device_node *np,
460 const struct clk_pll_layout *layout)
461 {
462 u32 id;
463 struct clk_hw *hw;
464 struct regmap *regmap;
465 const char *parent_name;
466 const char *name = np->name;
467 struct clk_pll_characteristics *characteristics;
468
469 if (of_property_read_u32(np, "reg", &id))
470 return;
471
472 parent_name = of_clk_get_parent_name(np, 0);
473
474 of_property_read_string(np, "clock-output-names", &name);
475
476 regmap = syscon_node_to_regmap(of_get_parent(np));
477 if (IS_ERR(regmap))
478 return;
479
480 characteristics = of_at91_clk_pll_get_characteristics(np);
481 if (!characteristics)
482 return;
483
484 hw = at91_clk_register_pll(regmap, name, parent_name, id, layout,
485 characteristics);
486 if (IS_ERR(hw))
487 goto out_free_characteristics;
488
489 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
490 return;
491
492 out_free_characteristics:
493 kfree(characteristics);
494 }
495
of_at91rm9200_clk_pll_setup(struct device_node * np)496 static void __init of_at91rm9200_clk_pll_setup(struct device_node *np)
497 {
498 of_at91_clk_pll_setup(np, &at91rm9200_pll_layout);
499 }
500 CLK_OF_DECLARE(at91rm9200_clk_pll, "atmel,at91rm9200-clk-pll",
501 of_at91rm9200_clk_pll_setup);
502
of_at91sam9g45_clk_pll_setup(struct device_node * np)503 static void __init of_at91sam9g45_clk_pll_setup(struct device_node *np)
504 {
505 of_at91_clk_pll_setup(np, &at91sam9g45_pll_layout);
506 }
507 CLK_OF_DECLARE(at91sam9g45_clk_pll, "atmel,at91sam9g45-clk-pll",
508 of_at91sam9g45_clk_pll_setup);
509
of_at91sam9g20_clk_pllb_setup(struct device_node * np)510 static void __init of_at91sam9g20_clk_pllb_setup(struct device_node *np)
511 {
512 of_at91_clk_pll_setup(np, &at91sam9g20_pllb_layout);
513 }
514 CLK_OF_DECLARE(at91sam9g20_clk_pllb, "atmel,at91sam9g20-clk-pllb",
515 of_at91sam9g20_clk_pllb_setup);
516
of_sama5d3_clk_pll_setup(struct device_node * np)517 static void __init of_sama5d3_clk_pll_setup(struct device_node *np)
518 {
519 of_at91_clk_pll_setup(np, &sama5d3_pll_layout);
520 }
521 CLK_OF_DECLARE(sama5d3_clk_pll, "atmel,sama5d3-clk-pll",
522 of_sama5d3_clk_pll_setup);
523