1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef _SMU7_HWMGR_H 25 #define _SMU7_HWMGR_H 26 27 #include "hwmgr.h" 28 #include "ppatomctrl.h" 29 30 #define SMU7_MAX_HARDWARE_POWERLEVELS 2 31 32 #define SMU7_VOLTAGE_CONTROL_NONE 0x0 33 #define SMU7_VOLTAGE_CONTROL_BY_GPIO 0x1 34 #define SMU7_VOLTAGE_CONTROL_BY_SVID2 0x2 35 #define SMU7_VOLTAGE_CONTROL_MERGED 0x3 36 37 #define DPMTABLE_OD_UPDATE_SCLK 0x00000001 38 #define DPMTABLE_OD_UPDATE_MCLK 0x00000002 39 #define DPMTABLE_UPDATE_SCLK 0x00000004 40 #define DPMTABLE_UPDATE_MCLK 0x00000008 41 42 enum gpu_pt_config_reg_type { 43 GPU_CONFIGREG_MMR = 0, 44 GPU_CONFIGREG_SMC_IND, 45 GPU_CONFIGREG_DIDT_IND, 46 GPU_CONFIGREG_GC_CAC_IND, 47 GPU_CONFIGREG_CACHE, 48 GPU_CONFIGREG_MAX 49 }; 50 51 struct gpu_pt_config_reg { 52 uint32_t offset; 53 uint32_t mask; 54 uint32_t shift; 55 uint32_t value; 56 enum gpu_pt_config_reg_type type; 57 }; 58 59 struct smu7_performance_level { 60 uint32_t memory_clock; 61 uint32_t engine_clock; 62 uint16_t pcie_gen; 63 uint16_t pcie_lane; 64 }; 65 66 struct smu7_thermal_temperature_setting { 67 long temperature_low; 68 long temperature_high; 69 long temperature_shutdown; 70 }; 71 72 struct smu7_uvd_clocks { 73 uint32_t vclk; 74 uint32_t dclk; 75 }; 76 77 struct smu7_vce_clocks { 78 uint32_t evclk; 79 uint32_t ecclk; 80 }; 81 82 struct smu7_power_state { 83 uint32_t magic; 84 struct smu7_uvd_clocks uvd_clks; 85 struct smu7_vce_clocks vce_clks; 86 uint32_t sam_clk; 87 uint16_t performance_level_count; 88 bool dc_compatible; 89 uint32_t sclk_threshold; 90 struct smu7_performance_level performance_levels[SMU7_MAX_HARDWARE_POWERLEVELS]; 91 }; 92 93 struct smu7_dpm_level { 94 bool enabled; 95 uint32_t value; 96 uint32_t param1; 97 }; 98 99 #define SMU7_MAX_DEEPSLEEP_DIVIDER_ID 5 100 #define MAX_REGULAR_DPM_NUMBER 8 101 #define SMU7_MINIMUM_ENGINE_CLOCK 2500 102 103 struct smu7_single_dpm_table { 104 uint32_t count; 105 struct smu7_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER]; 106 }; 107 108 struct smu7_dpm_table { 109 struct smu7_single_dpm_table sclk_table; 110 struct smu7_single_dpm_table mclk_table; 111 struct smu7_single_dpm_table pcie_speed_table; 112 struct smu7_single_dpm_table vddc_table; 113 struct smu7_single_dpm_table vddci_table; 114 struct smu7_single_dpm_table mvdd_table; 115 }; 116 117 struct smu7_clock_registers { 118 uint32_t vCG_SPLL_FUNC_CNTL; 119 uint32_t vCG_SPLL_FUNC_CNTL_2; 120 uint32_t vCG_SPLL_FUNC_CNTL_3; 121 uint32_t vCG_SPLL_FUNC_CNTL_4; 122 uint32_t vCG_SPLL_SPREAD_SPECTRUM; 123 uint32_t vCG_SPLL_SPREAD_SPECTRUM_2; 124 uint32_t vDLL_CNTL; 125 uint32_t vMCLK_PWRMGT_CNTL; 126 uint32_t vMPLL_AD_FUNC_CNTL; 127 uint32_t vMPLL_DQ_FUNC_CNTL; 128 uint32_t vMPLL_FUNC_CNTL; 129 uint32_t vMPLL_FUNC_CNTL_1; 130 uint32_t vMPLL_FUNC_CNTL_2; 131 uint32_t vMPLL_SS1; 132 uint32_t vMPLL_SS2; 133 }; 134 135 #define DISABLE_MC_LOADMICROCODE 1 136 #define DISABLE_MC_CFGPROGRAMMING 2 137 138 struct smu7_voltage_smio_registers { 139 uint32_t vS0_VID_LOWER_SMIO_CNTL; 140 }; 141 142 #define SMU7_MAX_LEAKAGE_COUNT 8 143 144 struct smu7_leakage_voltage { 145 uint16_t count; 146 uint16_t leakage_id[SMU7_MAX_LEAKAGE_COUNT]; 147 uint16_t actual_voltage[SMU7_MAX_LEAKAGE_COUNT]; 148 }; 149 150 struct smu7_vbios_boot_state { 151 uint16_t mvdd_bootup_value; 152 uint16_t vddc_bootup_value; 153 uint16_t vddci_bootup_value; 154 uint16_t vddgfx_bootup_value; 155 uint32_t sclk_bootup_value; 156 uint32_t mclk_bootup_value; 157 uint16_t pcie_gen_bootup_value; 158 uint16_t pcie_lane_bootup_value; 159 }; 160 161 struct smu7_display_timing { 162 uint32_t min_clock_in_sr; 163 uint32_t num_existing_displays; 164 }; 165 166 struct smu7_dpmlevel_enable_mask { 167 uint32_t uvd_dpm_enable_mask; 168 uint32_t vce_dpm_enable_mask; 169 uint32_t acp_dpm_enable_mask; 170 uint32_t samu_dpm_enable_mask; 171 uint32_t sclk_dpm_enable_mask; 172 uint32_t mclk_dpm_enable_mask; 173 uint32_t pcie_dpm_enable_mask; 174 }; 175 176 struct smu7_pcie_perf_range { 177 uint16_t max; 178 uint16_t min; 179 }; 180 181 struct smu7_hwmgr { 182 struct smu7_dpm_table dpm_table; 183 struct smu7_dpm_table golden_dpm_table; 184 185 uint32_t voting_rights_clients0; 186 uint32_t voting_rights_clients1; 187 uint32_t voting_rights_clients2; 188 uint32_t voting_rights_clients3; 189 uint32_t voting_rights_clients4; 190 uint32_t voting_rights_clients5; 191 uint32_t voting_rights_clients6; 192 uint32_t voting_rights_clients7; 193 uint32_t static_screen_threshold_unit; 194 uint32_t static_screen_threshold; 195 uint32_t voltage_control; 196 uint32_t vdd_gfx_control; 197 uint32_t vddc_vddgfx_delta; 198 uint32_t active_auto_throttle_sources; 199 200 struct smu7_clock_registers clock_registers; 201 202 bool is_memory_gddr5; 203 uint16_t acpi_vddc; 204 bool pspp_notify_required; 205 uint16_t force_pcie_gen; 206 uint16_t acpi_pcie_gen; 207 uint32_t pcie_gen_cap; 208 uint32_t pcie_lane_cap; 209 uint32_t pcie_spc_cap; 210 struct smu7_leakage_voltage vddc_leakage; 211 struct smu7_leakage_voltage vddci_leakage; 212 struct smu7_leakage_voltage vddcgfx_leakage; 213 214 uint32_t mvdd_control; 215 uint32_t vddc_mask_low; 216 uint32_t mvdd_mask_low; 217 uint16_t max_vddc_in_pptable; 218 uint16_t min_vddc_in_pptable; 219 uint16_t max_vddci_in_pptable; 220 uint16_t min_vddci_in_pptable; 221 bool is_uvd_enabled; 222 struct smu7_vbios_boot_state vbios_boot_state; 223 224 bool pcie_performance_request; 225 bool battery_state; 226 bool is_tlu_enabled; 227 bool disable_handshake; 228 bool smc_voltage_control_enabled; 229 bool vbi_time_out_support; 230 231 uint32_t soft_regs_start; 232 /* ---- Stuff originally coming from Evergreen ---- */ 233 uint32_t vddci_control; 234 struct pp_atomctrl_voltage_table vddc_voltage_table; 235 struct pp_atomctrl_voltage_table vddci_voltage_table; 236 struct pp_atomctrl_voltage_table mvdd_voltage_table; 237 struct pp_atomctrl_voltage_table vddgfx_voltage_table; 238 239 uint32_t mgcg_cgtt_local2; 240 uint32_t mgcg_cgtt_local3; 241 uint32_t gpio_debug; 242 uint32_t mc_micro_code_feature; 243 uint32_t highest_mclk; 244 uint16_t acpi_vddci; 245 uint8_t mvdd_high_index; 246 uint8_t mvdd_low_index; 247 bool dll_default_on; 248 bool performance_request_registered; 249 250 /* ---- Low Power Features ---- */ 251 bool ulv_supported; 252 253 /* ---- CAC Stuff ---- */ 254 uint32_t cac_table_start; 255 bool cac_configuration_required; 256 bool driver_calculate_cac_leakage; 257 bool cac_enabled; 258 259 /* ---- DPM2 Parameters ---- */ 260 uint32_t power_containment_features; 261 bool enable_dte_feature; 262 bool enable_tdc_limit_feature; 263 bool enable_pkg_pwr_tracking_feature; 264 bool disable_uvd_power_tune_feature; 265 266 267 uint32_t dte_tj_offset; 268 uint32_t fast_watermark_threshold; 269 270 /* ---- Phase Shedding ---- */ 271 uint8_t vddc_phase_shed_control; 272 273 /* ---- DI/DT ---- */ 274 struct smu7_display_timing display_timing; 275 276 /* ---- Thermal Temperature Setting ---- */ 277 struct smu7_thermal_temperature_setting thermal_temp_setting; 278 struct smu7_dpmlevel_enable_mask dpm_level_enable_mask; 279 uint32_t need_update_smu7_dpm_table; 280 uint32_t sclk_dpm_key_disabled; 281 uint32_t mclk_dpm_key_disabled; 282 uint32_t pcie_dpm_key_disabled; 283 uint32_t min_engine_clocks; 284 struct smu7_pcie_perf_range pcie_gen_performance; 285 struct smu7_pcie_perf_range pcie_lane_performance; 286 struct smu7_pcie_perf_range pcie_gen_power_saving; 287 struct smu7_pcie_perf_range pcie_lane_power_saving; 288 bool use_pcie_performance_levels; 289 bool use_pcie_power_saving_levels; 290 uint32_t mclk_activity_target; 291 uint32_t mclk_dpm0_activity_target; 292 uint32_t low_sclk_interrupt_threshold; 293 uint32_t last_mclk_dpm_enable_mask; 294 bool uvd_enabled; 295 296 /* ---- Power Gating States ---- */ 297 bool uvd_power_gated; 298 bool vce_power_gated; 299 bool samu_power_gated; 300 bool need_long_memory_training; 301 302 /* Application power optimization parameters */ 303 bool update_up_hyst; 304 bool update_down_hyst; 305 uint32_t down_hyst; 306 uint32_t up_hyst; 307 uint32_t disable_dpm_mask; 308 bool apply_optimized_settings; 309 310 uint32_t avfs_vdroop_override_setting; 311 bool apply_avfs_cks_off_voltage; 312 uint32_t frame_time_x2; 313 uint16_t mem_latency_high; 314 uint16_t mem_latency_low; 315 }; 316 317 /* To convert to Q8.8 format for firmware */ 318 #define SMU7_Q88_FORMAT_CONVERSION_UNIT 256 319 320 enum SMU7_I2CLineID { 321 SMU7_I2CLineID_DDC1 = 0x90, 322 SMU7_I2CLineID_DDC2 = 0x91, 323 SMU7_I2CLineID_DDC3 = 0x92, 324 SMU7_I2CLineID_DDC4 = 0x93, 325 SMU7_I2CLineID_DDC5 = 0x94, 326 SMU7_I2CLineID_DDC6 = 0x95, 327 SMU7_I2CLineID_SCLSDA = 0x96, 328 SMU7_I2CLineID_DDCVGA = 0x97 329 }; 330 331 #define SMU7_I2C_DDC1DATA 0 332 #define SMU7_I2C_DDC1CLK 1 333 #define SMU7_I2C_DDC2DATA 2 334 #define SMU7_I2C_DDC2CLK 3 335 #define SMU7_I2C_DDC3DATA 4 336 #define SMU7_I2C_DDC3CLK 5 337 #define SMU7_I2C_SDA 40 338 #define SMU7_I2C_SCL 41 339 #define SMU7_I2C_DDC4DATA 65 340 #define SMU7_I2C_DDC4CLK 66 341 #define SMU7_I2C_DDC5DATA 0x48 342 #define SMU7_I2C_DDC5CLK 0x49 343 #define SMU7_I2C_DDC6DATA 0x4a 344 #define SMU7_I2C_DDC6CLK 0x4b 345 #define SMU7_I2C_DDCVGADATA 0x4c 346 #define SMU7_I2C_DDCVGACLK 0x4d 347 348 #define SMU7_UNUSED_GPIO_PIN 0x7F 349 uint32_t smu7_get_xclk(struct pp_hwmgr *hwmgr); 350 uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock, 351 uint32_t clock_insr); 352 #endif 353 354