1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include <linux/module.h>
24 #include <linux/slab.h>
25 #include <linux/fb.h>
26
27 #include "vega10_processpptables.h"
28 #include "ppatomfwctrl.h"
29 #include "atomfirmware.h"
30 #include "pp_debug.h"
31 #include "cgs_common.h"
32 #include "vega10_pptable.h"
33
34 #define NUM_DSPCLK_LEVELS 8
35 #define VEGA10_ENGINECLOCK_HARDMAX 198000
36
set_hw_cap(struct pp_hwmgr * hwmgr,bool enable,enum phm_platform_caps cap)37 static void set_hw_cap(struct pp_hwmgr *hwmgr, bool enable,
38 enum phm_platform_caps cap)
39 {
40 if (enable)
41 phm_cap_set(hwmgr->platform_descriptor.platformCaps, cap);
42 else
43 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, cap);
44 }
45
get_powerplay_table(struct pp_hwmgr * hwmgr)46 static const void *get_powerplay_table(struct pp_hwmgr *hwmgr)
47 {
48 int index = GetIndexIntoMasterDataTable(powerplayinfo);
49
50 u16 size;
51 u8 frev, crev;
52 const void *table_address = hwmgr->soft_pp_table;
53
54 if (!table_address) {
55 table_address = (ATOM_Vega10_POWERPLAYTABLE *)
56 cgs_atom_get_data_table(hwmgr->device, index,
57 &size, &frev, &crev);
58
59 hwmgr->soft_pp_table = table_address; /*Cache the result in RAM.*/
60 hwmgr->soft_pp_table_size = size;
61 }
62
63 return table_address;
64 }
65
check_powerplay_tables(struct pp_hwmgr * hwmgr,const ATOM_Vega10_POWERPLAYTABLE * powerplay_table)66 static int check_powerplay_tables(
67 struct pp_hwmgr *hwmgr,
68 const ATOM_Vega10_POWERPLAYTABLE *powerplay_table)
69 {
70 const ATOM_Vega10_State_Array *state_arrays;
71
72 state_arrays = (ATOM_Vega10_State_Array *)(((unsigned long)powerplay_table) +
73 le16_to_cpu(powerplay_table->usStateArrayOffset));
74
75 PP_ASSERT_WITH_CODE((powerplay_table->sHeader.format_revision >=
76 ATOM_Vega10_TABLE_REVISION_VEGA10),
77 "Unsupported PPTable format!", return -1);
78 PP_ASSERT_WITH_CODE(powerplay_table->usStateArrayOffset,
79 "State table is not set!", return -1);
80 PP_ASSERT_WITH_CODE(powerplay_table->sHeader.structuresize > 0,
81 "Invalid PowerPlay Table!", return -1);
82 PP_ASSERT_WITH_CODE(state_arrays->ucNumEntries > 0,
83 "Invalid PowerPlay Table!", return -1);
84
85 return 0;
86 }
87
set_platform_caps(struct pp_hwmgr * hwmgr,uint32_t powerplay_caps)88 static int set_platform_caps(struct pp_hwmgr *hwmgr, uint32_t powerplay_caps)
89 {
90 set_hw_cap(
91 hwmgr,
92 0 != (powerplay_caps & ATOM_VEGA10_PP_PLATFORM_CAP_POWERPLAY),
93 PHM_PlatformCaps_PowerPlaySupport);
94
95 set_hw_cap(
96 hwmgr,
97 0 != (powerplay_caps & ATOM_VEGA10_PP_PLATFORM_CAP_SBIOSPOWERSOURCE),
98 PHM_PlatformCaps_BiosPowerSourceControl);
99
100 set_hw_cap(
101 hwmgr,
102 0 != (powerplay_caps & ATOM_VEGA10_PP_PLATFORM_CAP_HARDWAREDC),
103 PHM_PlatformCaps_AutomaticDCTransition);
104
105 set_hw_cap(
106 hwmgr,
107 0 != (powerplay_caps & ATOM_VEGA10_PP_PLATFORM_CAP_BACO),
108 PHM_PlatformCaps_BACO);
109
110 set_hw_cap(
111 hwmgr,
112 0 != (powerplay_caps & ATOM_VEGA10_PP_PLATFORM_COMBINE_PCC_WITH_THERMAL_SIGNAL),
113 PHM_PlatformCaps_CombinePCCWithThermalSignal);
114
115 return 0;
116 }
117
init_thermal_controller(struct pp_hwmgr * hwmgr,const ATOM_Vega10_POWERPLAYTABLE * powerplay_table)118 static int init_thermal_controller(
119 struct pp_hwmgr *hwmgr,
120 const ATOM_Vega10_POWERPLAYTABLE *powerplay_table)
121 {
122 const ATOM_Vega10_Thermal_Controller *thermal_controller;
123 const Vega10_PPTable_Generic_SubTable_Header *header;
124 const ATOM_Vega10_Fan_Table *fan_table_v1;
125 const ATOM_Vega10_Fan_Table_V2 *fan_table_v2;
126
127 thermal_controller = (ATOM_Vega10_Thermal_Controller *)
128 (((unsigned long)powerplay_table) +
129 le16_to_cpu(powerplay_table->usThermalControllerOffset));
130
131 PP_ASSERT_WITH_CODE((powerplay_table->usThermalControllerOffset != 0),
132 "Thermal controller table not set!", return -EINVAL);
133
134 hwmgr->thermal_controller.ucType = thermal_controller->ucType;
135 hwmgr->thermal_controller.ucI2cLine = thermal_controller->ucI2cLine;
136 hwmgr->thermal_controller.ucI2cAddress = thermal_controller->ucI2cAddress;
137
138 hwmgr->thermal_controller.fanInfo.bNoFan =
139 (0 != (thermal_controller->ucFanParameters &
140 ATOM_VEGA10_PP_FANPARAMETERS_NOFAN));
141
142 hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution =
143 thermal_controller->ucFanParameters &
144 ATOM_VEGA10_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK;
145
146 hwmgr->thermal_controller.fanInfo.ulMinRPM =
147 thermal_controller->ucFanMinRPM * 100UL;
148 hwmgr->thermal_controller.fanInfo.ulMaxRPM =
149 thermal_controller->ucFanMaxRPM * 100UL;
150
151 hwmgr->thermal_controller.advanceFanControlParameters.ulCycleDelay
152 = 100000;
153
154 set_hw_cap(
155 hwmgr,
156 ATOM_VEGA10_PP_THERMALCONTROLLER_NONE != hwmgr->thermal_controller.ucType,
157 PHM_PlatformCaps_ThermalController);
158
159 if (!powerplay_table->usFanTableOffset)
160 return 0;
161
162 header = (const Vega10_PPTable_Generic_SubTable_Header *)
163 (((unsigned long)powerplay_table) +
164 le16_to_cpu(powerplay_table->usFanTableOffset));
165
166 if (header->ucRevId == 10) {
167 fan_table_v1 = (ATOM_Vega10_Fan_Table *)header;
168
169 PP_ASSERT_WITH_CODE((fan_table_v1->ucRevId >= 8),
170 "Invalid Input Fan Table!", return -EINVAL);
171
172 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
173 PHM_PlatformCaps_MicrocodeFanControl);
174
175 hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity =
176 le16_to_cpu(fan_table_v1->usFanOutputSensitivity);
177 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM =
178 le16_to_cpu(fan_table_v1->usFanRPMMax);
179 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMaxLimit =
180 le16_to_cpu(fan_table_v1->usThrottlingRPM);
181 hwmgr->thermal_controller.advanceFanControlParameters.ulMinFanSCLKAcousticLimit =
182 le16_to_cpu(fan_table_v1->usFanAcousticLimit);
183 hwmgr->thermal_controller.advanceFanControlParameters.usTMax =
184 le16_to_cpu(fan_table_v1->usTargetTemperature);
185 hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin =
186 le16_to_cpu(fan_table_v1->usMinimumPWMLimit);
187 hwmgr->thermal_controller.advanceFanControlParameters.ulTargetGfxClk =
188 le16_to_cpu(fan_table_v1->usTargetGfxClk);
189 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainEdge =
190 le16_to_cpu(fan_table_v1->usFanGainEdge);
191 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainHotspot =
192 le16_to_cpu(fan_table_v1->usFanGainHotspot);
193 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainLiquid =
194 le16_to_cpu(fan_table_v1->usFanGainLiquid);
195 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainVrVddc =
196 le16_to_cpu(fan_table_v1->usFanGainVrVddc);
197 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainVrMvdd =
198 le16_to_cpu(fan_table_v1->usFanGainVrMvdd);
199 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainPlx =
200 le16_to_cpu(fan_table_v1->usFanGainPlx);
201 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainHbm =
202 le16_to_cpu(fan_table_v1->usFanGainHbm);
203
204 hwmgr->thermal_controller.advanceFanControlParameters.ucEnableZeroRPM =
205 fan_table_v1->ucEnableZeroRPM;
206 hwmgr->thermal_controller.advanceFanControlParameters.usZeroRPMStopTemperature =
207 le16_to_cpu(fan_table_v1->usFanStopTemperature);
208 hwmgr->thermal_controller.advanceFanControlParameters.usZeroRPMStartTemperature =
209 le16_to_cpu(fan_table_v1->usFanStartTemperature);
210 } else if (header->ucRevId > 10) {
211 fan_table_v2 = (ATOM_Vega10_Fan_Table_V2 *)header;
212
213 hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution =
214 fan_table_v2->ucFanParameters & ATOM_VEGA10_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK;
215 hwmgr->thermal_controller.fanInfo.ulMinRPM = fan_table_v2->ucFanMinRPM * 100UL;
216 hwmgr->thermal_controller.fanInfo.ulMaxRPM = fan_table_v2->ucFanMaxRPM * 100UL;
217 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
218 PHM_PlatformCaps_MicrocodeFanControl);
219 hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity =
220 le16_to_cpu(fan_table_v2->usFanOutputSensitivity);
221 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM =
222 fan_table_v2->ucFanMaxRPM * 100UL;
223 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMaxLimit =
224 le16_to_cpu(fan_table_v2->usThrottlingRPM);
225 hwmgr->thermal_controller.advanceFanControlParameters.ulMinFanSCLKAcousticLimit =
226 le16_to_cpu(fan_table_v2->usFanAcousticLimitRpm);
227 hwmgr->thermal_controller.advanceFanControlParameters.usTMax =
228 le16_to_cpu(fan_table_v2->usTargetTemperature);
229 hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin =
230 le16_to_cpu(fan_table_v2->usMinimumPWMLimit);
231 hwmgr->thermal_controller.advanceFanControlParameters.ulTargetGfxClk =
232 le16_to_cpu(fan_table_v2->usTargetGfxClk);
233 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainEdge =
234 le16_to_cpu(fan_table_v2->usFanGainEdge);
235 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainHotspot =
236 le16_to_cpu(fan_table_v2->usFanGainHotspot);
237 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainLiquid =
238 le16_to_cpu(fan_table_v2->usFanGainLiquid);
239 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainVrVddc =
240 le16_to_cpu(fan_table_v2->usFanGainVrVddc);
241 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainVrMvdd =
242 le16_to_cpu(fan_table_v2->usFanGainVrMvdd);
243 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainPlx =
244 le16_to_cpu(fan_table_v2->usFanGainPlx);
245 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainHbm =
246 le16_to_cpu(fan_table_v2->usFanGainHbm);
247
248 hwmgr->thermal_controller.advanceFanControlParameters.ucEnableZeroRPM =
249 fan_table_v2->ucEnableZeroRPM;
250 hwmgr->thermal_controller.advanceFanControlParameters.usZeroRPMStopTemperature =
251 le16_to_cpu(fan_table_v2->usFanStopTemperature);
252 hwmgr->thermal_controller.advanceFanControlParameters.usZeroRPMStartTemperature =
253 le16_to_cpu(fan_table_v2->usFanStartTemperature);
254 }
255 return 0;
256 }
257
init_over_drive_limits(struct pp_hwmgr * hwmgr,const ATOM_Vega10_POWERPLAYTABLE * powerplay_table)258 static int init_over_drive_limits(
259 struct pp_hwmgr *hwmgr,
260 const ATOM_Vega10_POWERPLAYTABLE *powerplay_table)
261 {
262 const ATOM_Vega10_GFXCLK_Dependency_Table *gfxclk_dep_table =
263 (const ATOM_Vega10_GFXCLK_Dependency_Table *)
264 (((unsigned long) powerplay_table) +
265 le16_to_cpu(powerplay_table->usGfxclkDependencyTableOffset));
266 bool is_acg_enabled = false;
267 ATOM_Vega10_GFXCLK_Dependency_Record_V2 *patom_record_v2;
268
269 if (gfxclk_dep_table->ucRevId == 1) {
270 patom_record_v2 =
271 (ATOM_Vega10_GFXCLK_Dependency_Record_V2 *)gfxclk_dep_table->entries;
272 is_acg_enabled =
273 (bool)patom_record_v2[gfxclk_dep_table->ucNumEntries-1].ucACGEnable;
274 }
275
276 if (powerplay_table->ulMaxODEngineClock > VEGA10_ENGINECLOCK_HARDMAX &&
277 !is_acg_enabled)
278 hwmgr->platform_descriptor.overdriveLimit.engineClock =
279 VEGA10_ENGINECLOCK_HARDMAX;
280 else
281 hwmgr->platform_descriptor.overdriveLimit.engineClock =
282 le32_to_cpu(powerplay_table->ulMaxODEngineClock);
283 hwmgr->platform_descriptor.overdriveLimit.memoryClock =
284 le32_to_cpu(powerplay_table->ulMaxODMemoryClock);
285
286 hwmgr->platform_descriptor.minOverdriveVDDC = 0;
287 hwmgr->platform_descriptor.maxOverdriveVDDC = 0;
288 hwmgr->platform_descriptor.overdriveVDDCStep = 0;
289
290 if (hwmgr->platform_descriptor.overdriveLimit.engineClock > 0 &&
291 hwmgr->platform_descriptor.overdriveLimit.memoryClock > 0) {
292 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
293 PHM_PlatformCaps_ACOverdriveSupport);
294 }
295
296 return 0;
297 }
298
get_mm_clock_voltage_table(struct pp_hwmgr * hwmgr,phm_ppt_v1_mm_clock_voltage_dependency_table ** vega10_mm_table,const ATOM_Vega10_MM_Dependency_Table * mm_dependency_table)299 static int get_mm_clock_voltage_table(
300 struct pp_hwmgr *hwmgr,
301 phm_ppt_v1_mm_clock_voltage_dependency_table **vega10_mm_table,
302 const ATOM_Vega10_MM_Dependency_Table *mm_dependency_table)
303 {
304 uint32_t table_size, i;
305 const ATOM_Vega10_MM_Dependency_Record *mm_dependency_record;
306 phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table;
307
308 PP_ASSERT_WITH_CODE((mm_dependency_table->ucNumEntries != 0),
309 "Invalid PowerPlay Table!", return -1);
310
311 table_size = sizeof(uint32_t) +
312 sizeof(phm_ppt_v1_mm_clock_voltage_dependency_record) *
313 mm_dependency_table->ucNumEntries;
314 mm_table = (phm_ppt_v1_mm_clock_voltage_dependency_table *)
315 kzalloc(table_size, GFP_KERNEL);
316
317 if (!mm_table)
318 return -ENOMEM;
319
320 mm_table->count = mm_dependency_table->ucNumEntries;
321
322 for (i = 0; i < mm_dependency_table->ucNumEntries; i++) {
323 mm_dependency_record = &mm_dependency_table->entries[i];
324 mm_table->entries[i].vddcInd = mm_dependency_record->ucVddcInd;
325 mm_table->entries[i].samclock =
326 le32_to_cpu(mm_dependency_record->ulPSPClk);
327 mm_table->entries[i].eclk = le32_to_cpu(mm_dependency_record->ulEClk);
328 mm_table->entries[i].vclk = le32_to_cpu(mm_dependency_record->ulVClk);
329 mm_table->entries[i].dclk = le32_to_cpu(mm_dependency_record->ulDClk);
330 }
331
332 *vega10_mm_table = mm_table;
333
334 return 0;
335 }
336
get_scl_sda_value(uint8_t line,uint8_t * scl,uint8_t * sda)337 static void get_scl_sda_value(uint8_t line, uint8_t *scl, uint8_t* sda)
338 {
339 switch(line){
340 case Vega10_I2CLineID_DDC1:
341 *scl = Vega10_I2C_DDC1CLK;
342 *sda = Vega10_I2C_DDC1DATA;
343 break;
344 case Vega10_I2CLineID_DDC2:
345 *scl = Vega10_I2C_DDC2CLK;
346 *sda = Vega10_I2C_DDC2DATA;
347 break;
348 case Vega10_I2CLineID_DDC3:
349 *scl = Vega10_I2C_DDC3CLK;
350 *sda = Vega10_I2C_DDC3DATA;
351 break;
352 case Vega10_I2CLineID_DDC4:
353 *scl = Vega10_I2C_DDC4CLK;
354 *sda = Vega10_I2C_DDC4DATA;
355 break;
356 case Vega10_I2CLineID_DDC5:
357 *scl = Vega10_I2C_DDC5CLK;
358 *sda = Vega10_I2C_DDC5DATA;
359 break;
360 case Vega10_I2CLineID_DDC6:
361 *scl = Vega10_I2C_DDC6CLK;
362 *sda = Vega10_I2C_DDC6DATA;
363 break;
364 case Vega10_I2CLineID_SCLSDA:
365 *scl = Vega10_I2C_SCL;
366 *sda = Vega10_I2C_SDA;
367 break;
368 case Vega10_I2CLineID_DDCVGA:
369 *scl = Vega10_I2C_DDCVGACLK;
370 *sda = Vega10_I2C_DDCVGADATA;
371 break;
372 default:
373 *scl = 0;
374 *sda = 0;
375 break;
376 }
377 }
378
get_tdp_table(struct pp_hwmgr * hwmgr,struct phm_tdp_table ** info_tdp_table,const Vega10_PPTable_Generic_SubTable_Header * table)379 static int get_tdp_table(
380 struct pp_hwmgr *hwmgr,
381 struct phm_tdp_table **info_tdp_table,
382 const Vega10_PPTable_Generic_SubTable_Header *table)
383 {
384 uint32_t table_size;
385 struct phm_tdp_table *tdp_table;
386 uint8_t scl;
387 uint8_t sda;
388 const ATOM_Vega10_PowerTune_Table *power_tune_table;
389 const ATOM_Vega10_PowerTune_Table_V2 *power_tune_table_v2;
390 const ATOM_Vega10_PowerTune_Table_V3 *power_tune_table_v3;
391
392 table_size = sizeof(uint32_t) + sizeof(struct phm_tdp_table);
393
394 tdp_table = kzalloc(table_size, GFP_KERNEL);
395
396 if (!tdp_table)
397 return -ENOMEM;
398
399 if (table->ucRevId == 5) {
400 power_tune_table = (ATOM_Vega10_PowerTune_Table *)table;
401 tdp_table->usMaximumPowerDeliveryLimit = le16_to_cpu(power_tune_table->usSocketPowerLimit);
402 tdp_table->usTDC = le16_to_cpu(power_tune_table->usTdcLimit);
403 tdp_table->usEDCLimit = le16_to_cpu(power_tune_table->usEdcLimit);
404 tdp_table->usSoftwareShutdownTemp =
405 le16_to_cpu(power_tune_table->usSoftwareShutdownTemp);
406 tdp_table->usTemperatureLimitTedge =
407 le16_to_cpu(power_tune_table->usTemperatureLimitTedge);
408 tdp_table->usTemperatureLimitHotspot =
409 le16_to_cpu(power_tune_table->usTemperatureLimitHotSpot);
410 tdp_table->usTemperatureLimitLiquid1 =
411 le16_to_cpu(power_tune_table->usTemperatureLimitLiquid1);
412 tdp_table->usTemperatureLimitLiquid2 =
413 le16_to_cpu(power_tune_table->usTemperatureLimitLiquid2);
414 tdp_table->usTemperatureLimitHBM =
415 le16_to_cpu(power_tune_table->usTemperatureLimitHBM);
416 tdp_table->usTemperatureLimitVrVddc =
417 le16_to_cpu(power_tune_table->usTemperatureLimitVrSoc);
418 tdp_table->usTemperatureLimitVrMvdd =
419 le16_to_cpu(power_tune_table->usTemperatureLimitVrMem);
420 tdp_table->usTemperatureLimitPlx =
421 le16_to_cpu(power_tune_table->usTemperatureLimitPlx);
422 tdp_table->ucLiquid1_I2C_address = power_tune_table->ucLiquid1_I2C_address;
423 tdp_table->ucLiquid2_I2C_address = power_tune_table->ucLiquid2_I2C_address;
424 tdp_table->ucLiquid_I2C_Line = power_tune_table->ucLiquid_I2C_LineSCL;
425 tdp_table->ucLiquid_I2C_LineSDA = power_tune_table->ucLiquid_I2C_LineSDA;
426 tdp_table->ucVr_I2C_address = power_tune_table->ucVr_I2C_address;
427 tdp_table->ucVr_I2C_Line = power_tune_table->ucVr_I2C_LineSCL;
428 tdp_table->ucVr_I2C_LineSDA = power_tune_table->ucVr_I2C_LineSDA;
429 tdp_table->ucPlx_I2C_address = power_tune_table->ucPlx_I2C_address;
430 tdp_table->ucPlx_I2C_Line = power_tune_table->ucPlx_I2C_LineSCL;
431 tdp_table->ucPlx_I2C_LineSDA = power_tune_table->ucPlx_I2C_LineSDA;
432 hwmgr->platform_descriptor.LoadLineSlope = le16_to_cpu(power_tune_table->usLoadLineResistance);
433 } else if (table->ucRevId == 6) {
434 power_tune_table_v2 = (ATOM_Vega10_PowerTune_Table_V2 *)table;
435 tdp_table->usMaximumPowerDeliveryLimit = le16_to_cpu(power_tune_table_v2->usSocketPowerLimit);
436 tdp_table->usTDC = le16_to_cpu(power_tune_table_v2->usTdcLimit);
437 tdp_table->usEDCLimit = le16_to_cpu(power_tune_table_v2->usEdcLimit);
438 tdp_table->usSoftwareShutdownTemp =
439 le16_to_cpu(power_tune_table_v2->usSoftwareShutdownTemp);
440 tdp_table->usTemperatureLimitTedge =
441 le16_to_cpu(power_tune_table_v2->usTemperatureLimitTedge);
442 tdp_table->usTemperatureLimitHotspot =
443 le16_to_cpu(power_tune_table_v2->usTemperatureLimitHotSpot);
444 tdp_table->usTemperatureLimitLiquid1 =
445 le16_to_cpu(power_tune_table_v2->usTemperatureLimitLiquid1);
446 tdp_table->usTemperatureLimitLiquid2 =
447 le16_to_cpu(power_tune_table_v2->usTemperatureLimitLiquid2);
448 tdp_table->usTemperatureLimitHBM =
449 le16_to_cpu(power_tune_table_v2->usTemperatureLimitHBM);
450 tdp_table->usTemperatureLimitVrVddc =
451 le16_to_cpu(power_tune_table_v2->usTemperatureLimitVrSoc);
452 tdp_table->usTemperatureLimitVrMvdd =
453 le16_to_cpu(power_tune_table_v2->usTemperatureLimitVrMem);
454 tdp_table->usTemperatureLimitPlx =
455 le16_to_cpu(power_tune_table_v2->usTemperatureLimitPlx);
456 tdp_table->ucLiquid1_I2C_address = power_tune_table_v2->ucLiquid1_I2C_address;
457 tdp_table->ucLiquid2_I2C_address = power_tune_table_v2->ucLiquid2_I2C_address;
458
459 get_scl_sda_value(power_tune_table_v2->ucLiquid_I2C_Line, &scl, &sda);
460
461 tdp_table->ucLiquid_I2C_Line = scl;
462 tdp_table->ucLiquid_I2C_LineSDA = sda;
463
464 tdp_table->ucVr_I2C_address = power_tune_table_v2->ucVr_I2C_address;
465
466 get_scl_sda_value(power_tune_table_v2->ucVr_I2C_Line, &scl, &sda);
467
468 tdp_table->ucVr_I2C_Line = scl;
469 tdp_table->ucVr_I2C_LineSDA = sda;
470 tdp_table->ucPlx_I2C_address = power_tune_table_v2->ucPlx_I2C_address;
471
472 get_scl_sda_value(power_tune_table_v2->ucPlx_I2C_Line, &scl, &sda);
473
474 tdp_table->ucPlx_I2C_Line = scl;
475 tdp_table->ucPlx_I2C_LineSDA = sda;
476
477 hwmgr->platform_descriptor.LoadLineSlope =
478 le16_to_cpu(power_tune_table_v2->usLoadLineResistance);
479 } else {
480 power_tune_table_v3 = (ATOM_Vega10_PowerTune_Table_V3 *)table;
481 tdp_table->usMaximumPowerDeliveryLimit = power_tune_table_v3->usSocketPowerLimit;
482 tdp_table->usTDC = power_tune_table_v3->usTdcLimit;
483 tdp_table->usEDCLimit = power_tune_table_v3->usEdcLimit;
484 tdp_table->usSoftwareShutdownTemp = power_tune_table_v3->usSoftwareShutdownTemp;
485 tdp_table->usTemperatureLimitTedge = power_tune_table_v3->usTemperatureLimitTedge;
486 tdp_table->usTemperatureLimitHotspot = power_tune_table_v3->usTemperatureLimitHotSpot;
487 tdp_table->usTemperatureLimitLiquid1 = power_tune_table_v3->usTemperatureLimitLiquid1;
488 tdp_table->usTemperatureLimitLiquid2 = power_tune_table_v3->usTemperatureLimitLiquid2;
489 tdp_table->usTemperatureLimitHBM = power_tune_table_v3->usTemperatureLimitHBM;
490 tdp_table->usTemperatureLimitVrVddc = power_tune_table_v3->usTemperatureLimitVrSoc;
491 tdp_table->usTemperatureLimitVrMvdd = power_tune_table_v3->usTemperatureLimitVrMem;
492 tdp_table->usTemperatureLimitPlx = power_tune_table_v3->usTemperatureLimitPlx;
493 tdp_table->ucLiquid1_I2C_address = power_tune_table_v3->ucLiquid1_I2C_address;
494 tdp_table->ucLiquid2_I2C_address = power_tune_table_v3->ucLiquid2_I2C_address;
495 tdp_table->usBoostStartTemperature = power_tune_table_v3->usBoostStartTemperature;
496 tdp_table->usBoostStopTemperature = power_tune_table_v3->usBoostStopTemperature;
497 tdp_table->ulBoostClock = power_tune_table_v3->ulBoostClock;
498
499 get_scl_sda_value(power_tune_table_v3->ucLiquid_I2C_Line, &scl, &sda);
500
501 tdp_table->ucLiquid_I2C_Line = scl;
502 tdp_table->ucLiquid_I2C_LineSDA = sda;
503
504 tdp_table->ucVr_I2C_address = power_tune_table_v3->ucVr_I2C_address;
505
506 get_scl_sda_value(power_tune_table_v3->ucVr_I2C_Line, &scl, &sda);
507
508 tdp_table->ucVr_I2C_Line = scl;
509 tdp_table->ucVr_I2C_LineSDA = sda;
510
511 tdp_table->ucPlx_I2C_address = power_tune_table_v3->ucPlx_I2C_address;
512
513 get_scl_sda_value(power_tune_table_v3->ucPlx_I2C_Line, &scl, &sda);
514
515 tdp_table->ucPlx_I2C_Line = scl;
516 tdp_table->ucPlx_I2C_LineSDA = sda;
517
518 hwmgr->platform_descriptor.LoadLineSlope =
519 le16_to_cpu(power_tune_table_v3->usLoadLineResistance);
520 }
521
522 *info_tdp_table = tdp_table;
523
524 return 0;
525 }
526
get_socclk_voltage_dependency_table(struct pp_hwmgr * hwmgr,phm_ppt_v1_clock_voltage_dependency_table ** pp_vega10_clk_dep_table,const ATOM_Vega10_SOCCLK_Dependency_Table * clk_dep_table)527 static int get_socclk_voltage_dependency_table(
528 struct pp_hwmgr *hwmgr,
529 phm_ppt_v1_clock_voltage_dependency_table **pp_vega10_clk_dep_table,
530 const ATOM_Vega10_SOCCLK_Dependency_Table *clk_dep_table)
531 {
532 uint32_t table_size, i;
533 phm_ppt_v1_clock_voltage_dependency_table *clk_table;
534
535 PP_ASSERT_WITH_CODE(clk_dep_table->ucNumEntries,
536 "Invalid PowerPlay Table!", return -1);
537
538 table_size = sizeof(uint32_t) +
539 sizeof(phm_ppt_v1_clock_voltage_dependency_record) *
540 clk_dep_table->ucNumEntries;
541
542 clk_table = (phm_ppt_v1_clock_voltage_dependency_table *)
543 kzalloc(table_size, GFP_KERNEL);
544
545 if (!clk_table)
546 return -ENOMEM;
547
548 clk_table->count = (uint32_t)clk_dep_table->ucNumEntries;
549
550 for (i = 0; i < clk_dep_table->ucNumEntries; i++) {
551 clk_table->entries[i].vddInd =
552 clk_dep_table->entries[i].ucVddInd;
553 clk_table->entries[i].clk =
554 le32_to_cpu(clk_dep_table->entries[i].ulClk);
555 }
556
557 *pp_vega10_clk_dep_table = clk_table;
558
559 return 0;
560 }
561
get_mclk_voltage_dependency_table(struct pp_hwmgr * hwmgr,phm_ppt_v1_clock_voltage_dependency_table ** pp_vega10_mclk_dep_table,const ATOM_Vega10_MCLK_Dependency_Table * mclk_dep_table)562 static int get_mclk_voltage_dependency_table(
563 struct pp_hwmgr *hwmgr,
564 phm_ppt_v1_clock_voltage_dependency_table **pp_vega10_mclk_dep_table,
565 const ATOM_Vega10_MCLK_Dependency_Table *mclk_dep_table)
566 {
567 uint32_t table_size, i;
568 phm_ppt_v1_clock_voltage_dependency_table *mclk_table;
569
570 PP_ASSERT_WITH_CODE(mclk_dep_table->ucNumEntries,
571 "Invalid PowerPlay Table!", return -1);
572
573 table_size = sizeof(uint32_t) +
574 sizeof(phm_ppt_v1_clock_voltage_dependency_record) *
575 mclk_dep_table->ucNumEntries;
576
577 mclk_table = (phm_ppt_v1_clock_voltage_dependency_table *)
578 kzalloc(table_size, GFP_KERNEL);
579
580 if (!mclk_table)
581 return -ENOMEM;
582
583 mclk_table->count = (uint32_t)mclk_dep_table->ucNumEntries;
584
585 for (i = 0; i < mclk_dep_table->ucNumEntries; i++) {
586 mclk_table->entries[i].vddInd =
587 mclk_dep_table->entries[i].ucVddInd;
588 mclk_table->entries[i].vddciInd =
589 mclk_dep_table->entries[i].ucVddciInd;
590 mclk_table->entries[i].mvddInd =
591 mclk_dep_table->entries[i].ucVddMemInd;
592 mclk_table->entries[i].clk =
593 le32_to_cpu(mclk_dep_table->entries[i].ulMemClk);
594 }
595
596 *pp_vega10_mclk_dep_table = mclk_table;
597
598 return 0;
599 }
600
get_gfxclk_voltage_dependency_table(struct pp_hwmgr * hwmgr,struct phm_ppt_v1_clock_voltage_dependency_table ** pp_vega10_clk_dep_table,const ATOM_Vega10_GFXCLK_Dependency_Table * clk_dep_table)601 static int get_gfxclk_voltage_dependency_table(
602 struct pp_hwmgr *hwmgr,
603 struct phm_ppt_v1_clock_voltage_dependency_table
604 **pp_vega10_clk_dep_table,
605 const ATOM_Vega10_GFXCLK_Dependency_Table *clk_dep_table)
606 {
607 uint32_t table_size, i;
608 struct phm_ppt_v1_clock_voltage_dependency_table
609 *clk_table;
610 ATOM_Vega10_GFXCLK_Dependency_Record_V2 *patom_record_v2;
611
612 PP_ASSERT_WITH_CODE((clk_dep_table->ucNumEntries != 0),
613 "Invalid PowerPlay Table!", return -1);
614
615 table_size = sizeof(uint32_t) +
616 sizeof(phm_ppt_v1_clock_voltage_dependency_record) *
617 clk_dep_table->ucNumEntries;
618
619 clk_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)
620 kzalloc(table_size, GFP_KERNEL);
621
622 if (!clk_table)
623 return -ENOMEM;
624
625 clk_table->count = clk_dep_table->ucNumEntries;
626
627 if (clk_dep_table->ucRevId == 0) {
628 for (i = 0; i < clk_table->count; i++) {
629 clk_table->entries[i].vddInd =
630 clk_dep_table->entries[i].ucVddInd;
631 clk_table->entries[i].clk =
632 le32_to_cpu(clk_dep_table->entries[i].ulClk);
633 clk_table->entries[i].cks_enable =
634 (((le16_to_cpu(clk_dep_table->entries[i].usCKSVOffsetandDisable) & 0x8000)
635 >> 15) == 0) ? 1 : 0;
636 clk_table->entries[i].cks_voffset =
637 le16_to_cpu(clk_dep_table->entries[i].usCKSVOffsetandDisable) & 0x7F;
638 clk_table->entries[i].sclk_offset =
639 le16_to_cpu(clk_dep_table->entries[i].usAVFSOffset);
640 }
641 } else if (clk_dep_table->ucRevId == 1) {
642 patom_record_v2 = (ATOM_Vega10_GFXCLK_Dependency_Record_V2 *)clk_dep_table->entries;
643 for (i = 0; i < clk_table->count; i++) {
644 clk_table->entries[i].vddInd =
645 patom_record_v2->ucVddInd;
646 clk_table->entries[i].clk =
647 le32_to_cpu(patom_record_v2->ulClk);
648 clk_table->entries[i].cks_enable =
649 (((le16_to_cpu(patom_record_v2->usCKSVOffsetandDisable) & 0x8000)
650 >> 15) == 0) ? 1 : 0;
651 clk_table->entries[i].cks_voffset =
652 le16_to_cpu(patom_record_v2->usCKSVOffsetandDisable) & 0x7F;
653 clk_table->entries[i].sclk_offset =
654 le16_to_cpu(patom_record_v2->usAVFSOffset);
655 patom_record_v2++;
656 }
657 } else {
658 kfree(clk_table);
659 PP_ASSERT_WITH_CODE(false,
660 "Unsupported GFXClockDependencyTable Revision!",
661 return -EINVAL);
662 }
663
664 *pp_vega10_clk_dep_table = clk_table;
665
666 return 0;
667 }
668
get_pix_clk_voltage_dependency_table(struct pp_hwmgr * hwmgr,struct phm_ppt_v1_clock_voltage_dependency_table ** pp_vega10_clk_dep_table,const ATOM_Vega10_PIXCLK_Dependency_Table * clk_dep_table)669 static int get_pix_clk_voltage_dependency_table(
670 struct pp_hwmgr *hwmgr,
671 struct phm_ppt_v1_clock_voltage_dependency_table
672 **pp_vega10_clk_dep_table,
673 const ATOM_Vega10_PIXCLK_Dependency_Table *clk_dep_table)
674 {
675 uint32_t table_size, i;
676 struct phm_ppt_v1_clock_voltage_dependency_table
677 *clk_table;
678
679 PP_ASSERT_WITH_CODE((clk_dep_table->ucNumEntries != 0),
680 "Invalid PowerPlay Table!", return -1);
681
682 table_size = sizeof(uint32_t) +
683 sizeof(phm_ppt_v1_clock_voltage_dependency_record) *
684 clk_dep_table->ucNumEntries;
685
686 clk_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)
687 kzalloc(table_size, GFP_KERNEL);
688
689 if (!clk_table)
690 return -ENOMEM;
691
692 clk_table->count = clk_dep_table->ucNumEntries;
693
694 for (i = 0; i < clk_table->count; i++) {
695 clk_table->entries[i].vddInd =
696 clk_dep_table->entries[i].ucVddInd;
697 clk_table->entries[i].clk =
698 le32_to_cpu(clk_dep_table->entries[i].ulClk);
699 }
700
701 *pp_vega10_clk_dep_table = clk_table;
702
703 return 0;
704 }
705
get_dcefclk_voltage_dependency_table(struct pp_hwmgr * hwmgr,struct phm_ppt_v1_clock_voltage_dependency_table ** pp_vega10_clk_dep_table,const ATOM_Vega10_DCEFCLK_Dependency_Table * clk_dep_table)706 static int get_dcefclk_voltage_dependency_table(
707 struct pp_hwmgr *hwmgr,
708 struct phm_ppt_v1_clock_voltage_dependency_table
709 **pp_vega10_clk_dep_table,
710 const ATOM_Vega10_DCEFCLK_Dependency_Table *clk_dep_table)
711 {
712 uint32_t table_size, i;
713 uint8_t num_entries;
714 struct phm_ppt_v1_clock_voltage_dependency_table
715 *clk_table;
716 struct cgs_system_info sys_info = {0};
717 uint32_t dev_id;
718 uint32_t rev_id;
719
720 PP_ASSERT_WITH_CODE((clk_dep_table->ucNumEntries != 0),
721 "Invalid PowerPlay Table!", return -1);
722
723 /*
724 * workaround needed to add another DPM level for pioneer cards
725 * as VBIOS is locked down.
726 * This DPM level was added to support 3DPM monitors @ 4K120Hz
727 *
728 */
729 sys_info.size = sizeof(struct cgs_system_info);
730 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_DEV;
731 cgs_query_system_info(hwmgr->device, &sys_info);
732 dev_id = (uint32_t)sys_info.value;
733
734 sys_info.size = sizeof(struct cgs_system_info);
735 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_REV;
736 cgs_query_system_info(hwmgr->device, &sys_info);
737 rev_id = (uint32_t)sys_info.value;
738
739 if (dev_id == 0x6863 && rev_id == 0 &&
740 clk_dep_table->entries[clk_dep_table->ucNumEntries - 1].ulClk < 90000)
741 num_entries = clk_dep_table->ucNumEntries + 1 > NUM_DSPCLK_LEVELS ?
742 NUM_DSPCLK_LEVELS : clk_dep_table->ucNumEntries + 1;
743 else
744 num_entries = clk_dep_table->ucNumEntries;
745
746
747 table_size = sizeof(uint32_t) +
748 sizeof(phm_ppt_v1_clock_voltage_dependency_record) *
749 num_entries;
750
751 clk_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)
752 kzalloc(table_size, GFP_KERNEL);
753
754 if (!clk_table)
755 return -ENOMEM;
756
757 clk_table->count = (uint32_t)num_entries;
758
759 for (i = 0; i < clk_dep_table->ucNumEntries; i++) {
760 clk_table->entries[i].vddInd =
761 clk_dep_table->entries[i].ucVddInd;
762 clk_table->entries[i].clk =
763 le32_to_cpu(clk_dep_table->entries[i].ulClk);
764 }
765
766 if (i < num_entries) {
767 clk_table->entries[i].vddInd = clk_dep_table->entries[i-1].ucVddInd;
768 clk_table->entries[i].clk = 90000;
769 }
770
771 *pp_vega10_clk_dep_table = clk_table;
772
773 return 0;
774 }
775
get_pcie_table(struct pp_hwmgr * hwmgr,struct phm_ppt_v1_pcie_table ** vega10_pcie_table,const Vega10_PPTable_Generic_SubTable_Header * table)776 static int get_pcie_table(struct pp_hwmgr *hwmgr,
777 struct phm_ppt_v1_pcie_table **vega10_pcie_table,
778 const Vega10_PPTable_Generic_SubTable_Header *table)
779 {
780 uint32_t table_size, i, pcie_count;
781 struct phm_ppt_v1_pcie_table *pcie_table;
782 struct phm_ppt_v2_information *table_info =
783 (struct phm_ppt_v2_information *)(hwmgr->pptable);
784 const ATOM_Vega10_PCIE_Table *atom_pcie_table =
785 (ATOM_Vega10_PCIE_Table *)table;
786
787 PP_ASSERT_WITH_CODE(atom_pcie_table->ucNumEntries,
788 "Invalid PowerPlay Table!",
789 return 0);
790
791 table_size = sizeof(uint32_t) +
792 sizeof(struct phm_ppt_v1_pcie_record) *
793 atom_pcie_table->ucNumEntries;
794
795 pcie_table = (struct phm_ppt_v1_pcie_table *)
796 kzalloc(table_size, GFP_KERNEL);
797
798 if (!pcie_table)
799 return -ENOMEM;
800
801 pcie_count = table_info->vdd_dep_on_sclk->count;
802 if (atom_pcie_table->ucNumEntries <= pcie_count)
803 pcie_count = atom_pcie_table->ucNumEntries;
804 else
805 pr_info("Number of Pcie Entries exceed the number of"
806 " GFXCLK Dpm Levels!"
807 " Disregarding the excess entries...\n");
808
809 pcie_table->count = pcie_count;
810
811 for (i = 0; i < pcie_count; i++) {
812 pcie_table->entries[i].gen_speed =
813 atom_pcie_table->entries[i].ucPCIEGenSpeed;
814 pcie_table->entries[i].lane_width =
815 atom_pcie_table->entries[i].ucPCIELaneWidth;
816 pcie_table->entries[i].pcie_sclk =
817 atom_pcie_table->entries[i].ulLCLK;
818 }
819
820 *vega10_pcie_table = pcie_table;
821
822 return 0;
823 }
824
get_hard_limits(struct pp_hwmgr * hwmgr,struct phm_clock_and_voltage_limits * limits,const ATOM_Vega10_Hard_Limit_Table * limit_table)825 static int get_hard_limits(
826 struct pp_hwmgr *hwmgr,
827 struct phm_clock_and_voltage_limits *limits,
828 const ATOM_Vega10_Hard_Limit_Table *limit_table)
829 {
830 PP_ASSERT_WITH_CODE(limit_table->ucNumEntries,
831 "Invalid PowerPlay Table!", return -1);
832
833 /* currently we always take entries[0] parameters */
834 limits->sclk = le32_to_cpu(limit_table->entries[0].ulSOCCLKLimit);
835 limits->mclk = le32_to_cpu(limit_table->entries[0].ulMCLKLimit);
836 limits->gfxclk = le32_to_cpu(limit_table->entries[0].ulGFXCLKLimit);
837 limits->vddc = le16_to_cpu(limit_table->entries[0].usVddcLimit);
838 limits->vddci = le16_to_cpu(limit_table->entries[0].usVddciLimit);
839 limits->vddmem = le16_to_cpu(limit_table->entries[0].usVddMemLimit);
840
841 return 0;
842 }
843
get_valid_clk(struct pp_hwmgr * hwmgr,struct phm_clock_array ** clk_table,const phm_ppt_v1_clock_voltage_dependency_table * clk_volt_pp_table)844 static int get_valid_clk(
845 struct pp_hwmgr *hwmgr,
846 struct phm_clock_array **clk_table,
847 const phm_ppt_v1_clock_voltage_dependency_table *clk_volt_pp_table)
848 {
849 uint32_t table_size, i;
850 struct phm_clock_array *table;
851
852 PP_ASSERT_WITH_CODE(clk_volt_pp_table->count,
853 "Invalid PowerPlay Table!", return -1);
854
855 table_size = sizeof(uint32_t) +
856 sizeof(uint32_t) * clk_volt_pp_table->count;
857
858 table = kzalloc(table_size, GFP_KERNEL);
859
860 if (!table)
861 return -ENOMEM;
862
863 table->count = (uint32_t)clk_volt_pp_table->count;
864
865 for (i = 0; i < table->count; i++)
866 table->values[i] = (uint32_t)clk_volt_pp_table->entries[i].clk;
867
868 *clk_table = table;
869
870 return 0;
871 }
872
init_powerplay_extended_tables(struct pp_hwmgr * hwmgr,const ATOM_Vega10_POWERPLAYTABLE * powerplay_table)873 static int init_powerplay_extended_tables(
874 struct pp_hwmgr *hwmgr,
875 const ATOM_Vega10_POWERPLAYTABLE *powerplay_table)
876 {
877 int result = 0;
878 struct phm_ppt_v2_information *pp_table_info =
879 (struct phm_ppt_v2_information *)(hwmgr->pptable);
880
881 const ATOM_Vega10_MM_Dependency_Table *mm_dependency_table =
882 (const ATOM_Vega10_MM_Dependency_Table *)
883 (((unsigned long) powerplay_table) +
884 le16_to_cpu(powerplay_table->usMMDependencyTableOffset));
885 const Vega10_PPTable_Generic_SubTable_Header *power_tune_table =
886 (const Vega10_PPTable_Generic_SubTable_Header *)
887 (((unsigned long) powerplay_table) +
888 le16_to_cpu(powerplay_table->usPowerTuneTableOffset));
889 const ATOM_Vega10_SOCCLK_Dependency_Table *socclk_dep_table =
890 (const ATOM_Vega10_SOCCLK_Dependency_Table *)
891 (((unsigned long) powerplay_table) +
892 le16_to_cpu(powerplay_table->usSocclkDependencyTableOffset));
893 const ATOM_Vega10_GFXCLK_Dependency_Table *gfxclk_dep_table =
894 (const ATOM_Vega10_GFXCLK_Dependency_Table *)
895 (((unsigned long) powerplay_table) +
896 le16_to_cpu(powerplay_table->usGfxclkDependencyTableOffset));
897 const ATOM_Vega10_DCEFCLK_Dependency_Table *dcefclk_dep_table =
898 (const ATOM_Vega10_DCEFCLK_Dependency_Table *)
899 (((unsigned long) powerplay_table) +
900 le16_to_cpu(powerplay_table->usDcefclkDependencyTableOffset));
901 const ATOM_Vega10_MCLK_Dependency_Table *mclk_dep_table =
902 (const ATOM_Vega10_MCLK_Dependency_Table *)
903 (((unsigned long) powerplay_table) +
904 le16_to_cpu(powerplay_table->usMclkDependencyTableOffset));
905 const ATOM_Vega10_Hard_Limit_Table *hard_limits =
906 (const ATOM_Vega10_Hard_Limit_Table *)
907 (((unsigned long) powerplay_table) +
908 le16_to_cpu(powerplay_table->usHardLimitTableOffset));
909 const Vega10_PPTable_Generic_SubTable_Header *pcie_table =
910 (const Vega10_PPTable_Generic_SubTable_Header *)
911 (((unsigned long) powerplay_table) +
912 le16_to_cpu(powerplay_table->usPCIETableOffset));
913 const ATOM_Vega10_PIXCLK_Dependency_Table *pixclk_dep_table =
914 (const ATOM_Vega10_PIXCLK_Dependency_Table *)
915 (((unsigned long) powerplay_table) +
916 le16_to_cpu(powerplay_table->usPixclkDependencyTableOffset));
917 const ATOM_Vega10_PHYCLK_Dependency_Table *phyclk_dep_table =
918 (const ATOM_Vega10_PHYCLK_Dependency_Table *)
919 (((unsigned long) powerplay_table) +
920 le16_to_cpu(powerplay_table->usPhyClkDependencyTableOffset));
921 const ATOM_Vega10_DISPCLK_Dependency_Table *dispclk_dep_table =
922 (const ATOM_Vega10_DISPCLK_Dependency_Table *)
923 (((unsigned long) powerplay_table) +
924 le16_to_cpu(powerplay_table->usDispClkDependencyTableOffset));
925
926 pp_table_info->vdd_dep_on_socclk = NULL;
927 pp_table_info->vdd_dep_on_sclk = NULL;
928 pp_table_info->vdd_dep_on_mclk = NULL;
929 pp_table_info->vdd_dep_on_dcefclk = NULL;
930 pp_table_info->mm_dep_table = NULL;
931 pp_table_info->tdp_table = NULL;
932 pp_table_info->vdd_dep_on_pixclk = NULL;
933 pp_table_info->vdd_dep_on_phyclk = NULL;
934 pp_table_info->vdd_dep_on_dispclk = NULL;
935
936 if (powerplay_table->usMMDependencyTableOffset)
937 result = get_mm_clock_voltage_table(hwmgr,
938 &pp_table_info->mm_dep_table,
939 mm_dependency_table);
940
941 if (!result && powerplay_table->usPowerTuneTableOffset)
942 result = get_tdp_table(hwmgr,
943 &pp_table_info->tdp_table,
944 power_tune_table);
945
946 if (!result && powerplay_table->usSocclkDependencyTableOffset)
947 result = get_socclk_voltage_dependency_table(hwmgr,
948 &pp_table_info->vdd_dep_on_socclk,
949 socclk_dep_table);
950
951 if (!result && powerplay_table->usGfxclkDependencyTableOffset)
952 result = get_gfxclk_voltage_dependency_table(hwmgr,
953 &pp_table_info->vdd_dep_on_sclk,
954 gfxclk_dep_table);
955
956 if (!result && powerplay_table->usPixclkDependencyTableOffset)
957 result = get_pix_clk_voltage_dependency_table(hwmgr,
958 &pp_table_info->vdd_dep_on_pixclk,
959 (const ATOM_Vega10_PIXCLK_Dependency_Table*)
960 pixclk_dep_table);
961
962 if (!result && powerplay_table->usPhyClkDependencyTableOffset)
963 result = get_pix_clk_voltage_dependency_table(hwmgr,
964 &pp_table_info->vdd_dep_on_phyclk,
965 (const ATOM_Vega10_PIXCLK_Dependency_Table *)
966 phyclk_dep_table);
967
968 if (!result && powerplay_table->usDispClkDependencyTableOffset)
969 result = get_pix_clk_voltage_dependency_table(hwmgr,
970 &pp_table_info->vdd_dep_on_dispclk,
971 (const ATOM_Vega10_PIXCLK_Dependency_Table *)
972 dispclk_dep_table);
973
974 if (!result && powerplay_table->usDcefclkDependencyTableOffset)
975 result = get_dcefclk_voltage_dependency_table(hwmgr,
976 &pp_table_info->vdd_dep_on_dcefclk,
977 dcefclk_dep_table);
978
979 if (!result && powerplay_table->usMclkDependencyTableOffset)
980 result = get_mclk_voltage_dependency_table(hwmgr,
981 &pp_table_info->vdd_dep_on_mclk,
982 mclk_dep_table);
983
984 if (!result && powerplay_table->usPCIETableOffset)
985 result = get_pcie_table(hwmgr,
986 &pp_table_info->pcie_table,
987 pcie_table);
988
989 if (!result && powerplay_table->usHardLimitTableOffset)
990 result = get_hard_limits(hwmgr,
991 &pp_table_info->max_clock_voltage_on_dc,
992 hard_limits);
993
994 hwmgr->dyn_state.max_clock_voltage_on_dc.sclk =
995 pp_table_info->max_clock_voltage_on_dc.sclk;
996 hwmgr->dyn_state.max_clock_voltage_on_dc.mclk =
997 pp_table_info->max_clock_voltage_on_dc.mclk;
998 hwmgr->dyn_state.max_clock_voltage_on_dc.vddc =
999 pp_table_info->max_clock_voltage_on_dc.vddc;
1000 hwmgr->dyn_state.max_clock_voltage_on_dc.vddci =
1001 pp_table_info->max_clock_voltage_on_dc.vddci;
1002
1003 if (!result &&
1004 pp_table_info->vdd_dep_on_socclk &&
1005 pp_table_info->vdd_dep_on_socclk->count)
1006 result = get_valid_clk(hwmgr,
1007 &pp_table_info->valid_socclk_values,
1008 pp_table_info->vdd_dep_on_socclk);
1009
1010 if (!result &&
1011 pp_table_info->vdd_dep_on_sclk &&
1012 pp_table_info->vdd_dep_on_sclk->count)
1013 result = get_valid_clk(hwmgr,
1014 &pp_table_info->valid_sclk_values,
1015 pp_table_info->vdd_dep_on_sclk);
1016
1017 if (!result &&
1018 pp_table_info->vdd_dep_on_dcefclk &&
1019 pp_table_info->vdd_dep_on_dcefclk->count)
1020 result = get_valid_clk(hwmgr,
1021 &pp_table_info->valid_dcefclk_values,
1022 pp_table_info->vdd_dep_on_dcefclk);
1023
1024 if (!result &&
1025 pp_table_info->vdd_dep_on_mclk &&
1026 pp_table_info->vdd_dep_on_mclk->count)
1027 result = get_valid_clk(hwmgr,
1028 &pp_table_info->valid_mclk_values,
1029 pp_table_info->vdd_dep_on_mclk);
1030
1031 return result;
1032 }
1033
get_vddc_lookup_table(struct pp_hwmgr * hwmgr,phm_ppt_v1_voltage_lookup_table ** lookup_table,const ATOM_Vega10_Voltage_Lookup_Table * vddc_lookup_pp_tables,uint32_t max_levels)1034 static int get_vddc_lookup_table(
1035 struct pp_hwmgr *hwmgr,
1036 phm_ppt_v1_voltage_lookup_table **lookup_table,
1037 const ATOM_Vega10_Voltage_Lookup_Table *vddc_lookup_pp_tables,
1038 uint32_t max_levels)
1039 {
1040 uint32_t table_size, i;
1041 phm_ppt_v1_voltage_lookup_table *table;
1042
1043 PP_ASSERT_WITH_CODE((vddc_lookup_pp_tables->ucNumEntries != 0),
1044 "Invalid SOC_VDDD Lookup Table!", return 1);
1045
1046 table_size = sizeof(uint32_t) +
1047 sizeof(phm_ppt_v1_voltage_lookup_record) * max_levels;
1048
1049 table = (phm_ppt_v1_voltage_lookup_table *)
1050 kzalloc(table_size, GFP_KERNEL);
1051
1052 if (NULL == table)
1053 return -ENOMEM;
1054
1055 table->count = vddc_lookup_pp_tables->ucNumEntries;
1056
1057 for (i = 0; i < vddc_lookup_pp_tables->ucNumEntries; i++)
1058 table->entries[i].us_vdd =
1059 le16_to_cpu(vddc_lookup_pp_tables->entries[i].usVdd);
1060
1061 *lookup_table = table;
1062
1063 return 0;
1064 }
1065
init_dpm_2_parameters(struct pp_hwmgr * hwmgr,const ATOM_Vega10_POWERPLAYTABLE * powerplay_table)1066 static int init_dpm_2_parameters(
1067 struct pp_hwmgr *hwmgr,
1068 const ATOM_Vega10_POWERPLAYTABLE *powerplay_table)
1069 {
1070 int result = 0;
1071 struct phm_ppt_v2_information *pp_table_info =
1072 (struct phm_ppt_v2_information *)(hwmgr->pptable);
1073 uint32_t disable_power_control = 0;
1074
1075 pp_table_info->us_ulv_voltage_offset =
1076 le16_to_cpu(powerplay_table->usUlvVoltageOffset);
1077
1078 pp_table_info->us_ulv_smnclk_did =
1079 le16_to_cpu(powerplay_table->usUlvSmnclkDid);
1080 pp_table_info->us_ulv_mp1clk_did =
1081 le16_to_cpu(powerplay_table->usUlvMp1clkDid);
1082 pp_table_info->us_ulv_gfxclk_bypass =
1083 le16_to_cpu(powerplay_table->usUlvGfxclkBypass);
1084 pp_table_info->us_gfxclk_slew_rate =
1085 le16_to_cpu(powerplay_table->usGfxclkSlewRate);
1086 pp_table_info->uc_gfx_dpm_voltage_mode =
1087 le16_to_cpu(powerplay_table->ucGfxVoltageMode);
1088 pp_table_info->uc_soc_dpm_voltage_mode =
1089 le16_to_cpu(powerplay_table->ucSocVoltageMode);
1090 pp_table_info->uc_uclk_dpm_voltage_mode =
1091 le16_to_cpu(powerplay_table->ucUclkVoltageMode);
1092 pp_table_info->uc_uvd_dpm_voltage_mode =
1093 le16_to_cpu(powerplay_table->ucUvdVoltageMode);
1094 pp_table_info->uc_vce_dpm_voltage_mode =
1095 le16_to_cpu(powerplay_table->ucVceVoltageMode);
1096 pp_table_info->uc_mp0_dpm_voltage_mode =
1097 le16_to_cpu(powerplay_table->ucMp0VoltageMode);
1098 pp_table_info->uc_dcef_dpm_voltage_mode =
1099 le16_to_cpu(powerplay_table->ucDcefVoltageMode);
1100
1101 pp_table_info->ppm_parameter_table = NULL;
1102 pp_table_info->vddc_lookup_table = NULL;
1103 pp_table_info->vddmem_lookup_table = NULL;
1104 pp_table_info->vddci_lookup_table = NULL;
1105
1106 /* TDP limits */
1107 hwmgr->platform_descriptor.TDPODLimit =
1108 le16_to_cpu(powerplay_table->usPowerControlLimit);
1109 hwmgr->platform_descriptor.TDPAdjustment = 0;
1110 hwmgr->platform_descriptor.VidAdjustment = 0;
1111 hwmgr->platform_descriptor.VidAdjustmentPolarity = 0;
1112 hwmgr->platform_descriptor.VidMinLimit = 0;
1113 hwmgr->platform_descriptor.VidMaxLimit = 1500000;
1114 hwmgr->platform_descriptor.VidStep = 6250;
1115
1116 disable_power_control = 0;
1117 if (!disable_power_control) {
1118 /* enable TDP overdrive (PowerControl) feature as well if supported */
1119 if (hwmgr->platform_descriptor.TDPODLimit)
1120 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
1121 PHM_PlatformCaps_PowerControl);
1122 }
1123
1124 if (powerplay_table->usVddcLookupTableOffset) {
1125 const ATOM_Vega10_Voltage_Lookup_Table *vddc_table =
1126 (ATOM_Vega10_Voltage_Lookup_Table *)
1127 (((unsigned long)powerplay_table) +
1128 le16_to_cpu(powerplay_table->usVddcLookupTableOffset));
1129 result = get_vddc_lookup_table(hwmgr,
1130 &pp_table_info->vddc_lookup_table, vddc_table, 8);
1131 }
1132
1133 if (powerplay_table->usVddmemLookupTableOffset) {
1134 const ATOM_Vega10_Voltage_Lookup_Table *vdd_mem_table =
1135 (ATOM_Vega10_Voltage_Lookup_Table *)
1136 (((unsigned long)powerplay_table) +
1137 le16_to_cpu(powerplay_table->usVddmemLookupTableOffset));
1138 result = get_vddc_lookup_table(hwmgr,
1139 &pp_table_info->vddmem_lookup_table, vdd_mem_table, 4);
1140 }
1141
1142 if (powerplay_table->usVddciLookupTableOffset) {
1143 const ATOM_Vega10_Voltage_Lookup_Table *vddci_table =
1144 (ATOM_Vega10_Voltage_Lookup_Table *)
1145 (((unsigned long)powerplay_table) +
1146 le16_to_cpu(powerplay_table->usVddciLookupTableOffset));
1147 result = get_vddc_lookup_table(hwmgr,
1148 &pp_table_info->vddci_lookup_table, vddci_table, 4);
1149 }
1150
1151 return result;
1152 }
1153
vega10_pp_tables_initialize(struct pp_hwmgr * hwmgr)1154 int vega10_pp_tables_initialize(struct pp_hwmgr *hwmgr)
1155 {
1156 int result = 0;
1157 const ATOM_Vega10_POWERPLAYTABLE *powerplay_table;
1158
1159 hwmgr->pptable = kzalloc(sizeof(struct phm_ppt_v2_information), GFP_KERNEL);
1160
1161 PP_ASSERT_WITH_CODE((NULL != hwmgr->pptable),
1162 "Failed to allocate hwmgr->pptable!", return -ENOMEM);
1163
1164 powerplay_table = get_powerplay_table(hwmgr);
1165
1166 PP_ASSERT_WITH_CODE((NULL != powerplay_table),
1167 "Missing PowerPlay Table!", return -1);
1168
1169 result = check_powerplay_tables(hwmgr, powerplay_table);
1170
1171 PP_ASSERT_WITH_CODE((result == 0),
1172 "check_powerplay_tables failed", return result);
1173
1174 result = set_platform_caps(hwmgr,
1175 le32_to_cpu(powerplay_table->ulPlatformCaps));
1176
1177 PP_ASSERT_WITH_CODE((result == 0),
1178 "set_platform_caps failed", return result);
1179
1180 result = init_thermal_controller(hwmgr, powerplay_table);
1181
1182 PP_ASSERT_WITH_CODE((result == 0),
1183 "init_thermal_controller failed", return result);
1184
1185 result = init_over_drive_limits(hwmgr, powerplay_table);
1186
1187 PP_ASSERT_WITH_CODE((result == 0),
1188 "init_over_drive_limits failed", return result);
1189
1190 result = init_powerplay_extended_tables(hwmgr, powerplay_table);
1191
1192 PP_ASSERT_WITH_CODE((result == 0),
1193 "init_powerplay_extended_tables failed", return result);
1194
1195 result = init_dpm_2_parameters(hwmgr, powerplay_table);
1196
1197 PP_ASSERT_WITH_CODE((result == 0),
1198 "init_dpm_2_parameters failed", return result);
1199
1200 return result;
1201 }
1202
vega10_pp_tables_uninitialize(struct pp_hwmgr * hwmgr)1203 static int vega10_pp_tables_uninitialize(struct pp_hwmgr *hwmgr)
1204 {
1205 int result = 0;
1206 struct phm_ppt_v2_information *pp_table_info =
1207 (struct phm_ppt_v2_information *)(hwmgr->pptable);
1208
1209 kfree(pp_table_info->vdd_dep_on_sclk);
1210 pp_table_info->vdd_dep_on_sclk = NULL;
1211
1212 kfree(pp_table_info->vdd_dep_on_mclk);
1213 pp_table_info->vdd_dep_on_mclk = NULL;
1214
1215 kfree(pp_table_info->valid_mclk_values);
1216 pp_table_info->valid_mclk_values = NULL;
1217
1218 kfree(pp_table_info->valid_sclk_values);
1219 pp_table_info->valid_sclk_values = NULL;
1220
1221 kfree(pp_table_info->vddc_lookup_table);
1222 pp_table_info->vddc_lookup_table = NULL;
1223
1224 kfree(pp_table_info->vddmem_lookup_table);
1225 pp_table_info->vddmem_lookup_table = NULL;
1226
1227 kfree(pp_table_info->vddci_lookup_table);
1228 pp_table_info->vddci_lookup_table = NULL;
1229
1230 kfree(pp_table_info->ppm_parameter_table);
1231 pp_table_info->ppm_parameter_table = NULL;
1232
1233 kfree(pp_table_info->mm_dep_table);
1234 pp_table_info->mm_dep_table = NULL;
1235
1236 kfree(pp_table_info->cac_dtp_table);
1237 pp_table_info->cac_dtp_table = NULL;
1238
1239 kfree(hwmgr->dyn_state.cac_dtp_table);
1240 hwmgr->dyn_state.cac_dtp_table = NULL;
1241
1242 kfree(pp_table_info->tdp_table);
1243 pp_table_info->tdp_table = NULL;
1244
1245 kfree(hwmgr->pptable);
1246 hwmgr->pptable = NULL;
1247
1248 return result;
1249 }
1250
1251 const struct pp_table_func vega10_pptable_funcs = {
1252 .pptable_init = vega10_pp_tables_initialize,
1253 .pptable_fini = vega10_pp_tables_uninitialize,
1254 };
1255
vega10_get_number_of_powerplay_table_entries(struct pp_hwmgr * hwmgr)1256 int vega10_get_number_of_powerplay_table_entries(struct pp_hwmgr *hwmgr)
1257 {
1258 const ATOM_Vega10_State_Array *state_arrays;
1259 const ATOM_Vega10_POWERPLAYTABLE *pp_table = get_powerplay_table(hwmgr);
1260
1261 PP_ASSERT_WITH_CODE((NULL != pp_table),
1262 "Missing PowerPlay Table!", return -1);
1263 PP_ASSERT_WITH_CODE((pp_table->sHeader.format_revision >=
1264 ATOM_Vega10_TABLE_REVISION_VEGA10),
1265 "Incorrect PowerPlay table revision!", return -1);
1266
1267 state_arrays = (ATOM_Vega10_State_Array *)(((unsigned long)pp_table) +
1268 le16_to_cpu(pp_table->usStateArrayOffset));
1269
1270 return (uint32_t)(state_arrays->ucNumEntries);
1271 }
1272
make_classification_flags(struct pp_hwmgr * hwmgr,uint16_t classification,uint16_t classification2)1273 static uint32_t make_classification_flags(struct pp_hwmgr *hwmgr,
1274 uint16_t classification, uint16_t classification2)
1275 {
1276 uint32_t result = 0;
1277
1278 if (classification & ATOM_PPLIB_CLASSIFICATION_BOOT)
1279 result |= PP_StateClassificationFlag_Boot;
1280
1281 if (classification & ATOM_PPLIB_CLASSIFICATION_THERMAL)
1282 result |= PP_StateClassificationFlag_Thermal;
1283
1284 if (classification & ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE)
1285 result |= PP_StateClassificationFlag_LimitedPowerSource;
1286
1287 if (classification & ATOM_PPLIB_CLASSIFICATION_REST)
1288 result |= PP_StateClassificationFlag_Rest;
1289
1290 if (classification & ATOM_PPLIB_CLASSIFICATION_FORCED)
1291 result |= PP_StateClassificationFlag_Forced;
1292
1293 if (classification & ATOM_PPLIB_CLASSIFICATION_ACPI)
1294 result |= PP_StateClassificationFlag_ACPI;
1295
1296 if (classification2 & ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2)
1297 result |= PP_StateClassificationFlag_LimitedPowerSource_2;
1298
1299 return result;
1300 }
1301
vega10_get_powerplay_table_entry(struct pp_hwmgr * hwmgr,uint32_t entry_index,struct pp_power_state * power_state,int (* call_back_func)(struct pp_hwmgr *,void *,struct pp_power_state *,void *,uint32_t))1302 int vega10_get_powerplay_table_entry(struct pp_hwmgr *hwmgr,
1303 uint32_t entry_index, struct pp_power_state *power_state,
1304 int (*call_back_func)(struct pp_hwmgr *, void *,
1305 struct pp_power_state *, void *, uint32_t))
1306 {
1307 int result = 0;
1308 const ATOM_Vega10_State_Array *state_arrays;
1309 const ATOM_Vega10_State *state_entry;
1310 const ATOM_Vega10_POWERPLAYTABLE *pp_table =
1311 get_powerplay_table(hwmgr);
1312
1313 PP_ASSERT_WITH_CODE(pp_table, "Missing PowerPlay Table!",
1314 return -1;);
1315 power_state->classification.bios_index = entry_index;
1316
1317 if (pp_table->sHeader.format_revision >=
1318 ATOM_Vega10_TABLE_REVISION_VEGA10) {
1319 state_arrays = (ATOM_Vega10_State_Array *)
1320 (((unsigned long)pp_table) +
1321 le16_to_cpu(pp_table->usStateArrayOffset));
1322
1323 PP_ASSERT_WITH_CODE(pp_table->usStateArrayOffset > 0,
1324 "Invalid PowerPlay Table State Array Offset.",
1325 return -1);
1326 PP_ASSERT_WITH_CODE(state_arrays->ucNumEntries > 0,
1327 "Invalid PowerPlay Table State Array.",
1328 return -1);
1329 PP_ASSERT_WITH_CODE((entry_index <= state_arrays->ucNumEntries),
1330 "Invalid PowerPlay Table State Array Entry.",
1331 return -1);
1332
1333 state_entry = &(state_arrays->states[entry_index]);
1334
1335 result = call_back_func(hwmgr, (void *)state_entry, power_state,
1336 (void *)pp_table,
1337 make_classification_flags(hwmgr,
1338 le16_to_cpu(state_entry->usClassification),
1339 le16_to_cpu(state_entry->usClassification2)));
1340 }
1341
1342 if (!result && (power_state->classification.flags &
1343 PP_StateClassificationFlag_Boot))
1344 result = hwmgr->hwmgr_func->patch_boot_state(hwmgr, &(power_state->hardware));
1345
1346 return result;
1347 }
1348