1 /*
2 * Broadcom NetXtreme-E RoCE driver.
3 *
4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term
5 * Broadcom refers to Broadcom Limited and/or its subsidiaries.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 *
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in
21 * the documentation and/or other materials provided with the
22 * distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 *
36 * Description: RDMA Controller HW interface (header)
37 */
38
39 #ifndef __BNXT_QPLIB_RCFW_H__
40 #define __BNXT_QPLIB_RCFW_H__
41
42 #define RCFW_CMDQ_TRIG_VAL 1
43 #define RCFW_COMM_PCI_BAR_REGION 0
44 #define RCFW_COMM_CONS_PCI_BAR_REGION 2
45 #define RCFW_COMM_BASE_OFFSET 0x600
46 #define RCFW_PF_COMM_PROD_OFFSET 0xc
47 #define RCFW_VF_COMM_PROD_OFFSET 0xc
48 #define RCFW_COMM_TRIG_OFFSET 0x100
49 #define RCFW_COMM_SIZE 0x104
50
51 #define RCFW_DBR_PCI_BAR_REGION 2
52 #define RCFW_DBR_BASE_PAGE_SHIFT 12
53
54 #define RCFW_CMD_PREP(req, CMD, cmd_flags) \
55 do { \
56 memset(&(req), 0, sizeof((req))); \
57 (req).opcode = CMDQ_BASE_OPCODE_##CMD; \
58 (req).cmd_size = (sizeof((req)) + \
59 BNXT_QPLIB_CMDQE_UNITS - 1) / \
60 BNXT_QPLIB_CMDQE_UNITS; \
61 (req).flags = cpu_to_le16(cmd_flags); \
62 } while (0)
63
64 #define RCFW_CMD_WAIT_TIME_MS 20000 /* 20 Seconds timeout */
65
66 /* CMDQ elements */
67 #define BNXT_QPLIB_CMDQE_MAX_CNT 256
68 #define BNXT_QPLIB_CMDQE_UNITS sizeof(struct bnxt_qplib_cmdqe)
69 #define BNXT_QPLIB_CMDQE_CNT_PER_PG (PAGE_SIZE / BNXT_QPLIB_CMDQE_UNITS)
70
71 #define MAX_CMDQ_IDX (BNXT_QPLIB_CMDQE_MAX_CNT - 1)
72 #define MAX_CMDQ_IDX_PER_PG (BNXT_QPLIB_CMDQE_CNT_PER_PG - 1)
73
74 #define RCFW_MAX_OUTSTANDING_CMD BNXT_QPLIB_CMDQE_MAX_CNT
75 #define RCFW_MAX_COOKIE_VALUE 0x7FFF
76 #define RCFW_CMD_IS_BLOCKING 0x8000
77 #define RCFW_BLOCKED_CMD_WAIT_COUNT 0x4E20
78
79 /* Cmdq contains a fix number of a 16-Byte slots */
80 struct bnxt_qplib_cmdqe {
81 u8 data[16];
82 };
83
get_cmdq_pg(u32 val)84 static inline u32 get_cmdq_pg(u32 val)
85 {
86 return (val & ~MAX_CMDQ_IDX_PER_PG) / BNXT_QPLIB_CMDQE_CNT_PER_PG;
87 }
88
get_cmdq_idx(u32 val)89 static inline u32 get_cmdq_idx(u32 val)
90 {
91 return val & MAX_CMDQ_IDX_PER_PG;
92 }
93
94 /* Crsq buf is 1024-Byte */
95 struct bnxt_qplib_crsbe {
96 u8 data[1024];
97 };
98
99 /* CREQ */
100 /* Allocate 1 per QP for async error notification for now */
101 #define BNXT_QPLIB_CREQE_MAX_CNT (64 * 1024)
102 #define BNXT_QPLIB_CREQE_UNITS 16 /* 16-Bytes per prod unit */
103 #define BNXT_QPLIB_CREQE_CNT_PER_PG (PAGE_SIZE / BNXT_QPLIB_CREQE_UNITS)
104
105 #define MAX_CREQ_IDX (BNXT_QPLIB_CREQE_MAX_CNT - 1)
106 #define MAX_CREQ_IDX_PER_PG (BNXT_QPLIB_CREQE_CNT_PER_PG - 1)
107
get_creq_pg(u32 val)108 static inline u32 get_creq_pg(u32 val)
109 {
110 return (val & ~MAX_CREQ_IDX_PER_PG) / BNXT_QPLIB_CREQE_CNT_PER_PG;
111 }
112
get_creq_idx(u32 val)113 static inline u32 get_creq_idx(u32 val)
114 {
115 return val & MAX_CREQ_IDX_PER_PG;
116 }
117
118 #define BNXT_QPLIB_CREQE_PER_PG (PAGE_SIZE / sizeof(struct creq_base))
119
120 #define CREQ_CMP_VALID(hdr, raw_cons, cp_bit) \
121 (!!((hdr)->v & CREQ_BASE_V) == \
122 !((raw_cons) & (cp_bit)))
123
124 #define CREQ_DB_KEY_CP (0x2 << CMPL_DOORBELL_KEY_SFT)
125 #define CREQ_DB_IDX_VALID CMPL_DOORBELL_IDX_VALID
126 #define CREQ_DB_IRQ_DIS CMPL_DOORBELL_MASK
127 #define CREQ_DB_CP_FLAGS_REARM (CREQ_DB_KEY_CP | \
128 CREQ_DB_IDX_VALID)
129 #define CREQ_DB_CP_FLAGS (CREQ_DB_KEY_CP | \
130 CREQ_DB_IDX_VALID | \
131 CREQ_DB_IRQ_DIS)
132 #define CREQ_DB_REARM(db, raw_cons, cp_bit) \
133 writel(CREQ_DB_CP_FLAGS_REARM | ((raw_cons) & ((cp_bit) - 1)), db)
134 #define CREQ_DB(db, raw_cons, cp_bit) \
135 writel(CREQ_DB_CP_FLAGS | ((raw_cons) & ((cp_bit) - 1)), db)
136
137 #define CREQ_ENTRY_POLL_BUDGET 0x100
138
139 /* HWQ */
140
141 struct bnxt_qplib_crsq {
142 struct creq_qp_event *resp;
143 u32 req_size;
144 };
145
146 struct bnxt_qplib_rcfw_sbuf {
147 void *sb;
148 dma_addr_t dma_addr;
149 u32 size;
150 };
151
152 struct bnxt_qplib_qp_node {
153 u32 qp_id; /* QP id */
154 void *qp_handle; /* ptr to qplib_qp */
155 };
156
157 /* RCFW Communication Channels */
158 struct bnxt_qplib_rcfw {
159 struct pci_dev *pdev;
160 int vector;
161 struct tasklet_struct worker;
162 bool requested;
163 unsigned long *cmdq_bitmap;
164 u32 bmap_size;
165 unsigned long flags;
166 #define FIRMWARE_INITIALIZED_FLAG BIT(0)
167 #define FIRMWARE_FIRST_FLAG BIT(31)
168 #define FIRMWARE_TIMED_OUT BIT(3)
169 wait_queue_head_t waitq;
170 int (*aeq_handler)(struct bnxt_qplib_rcfw *,
171 struct creq_func_event *);
172 u32 seq_num;
173
174 /* Bar region info */
175 void __iomem *cmdq_bar_reg_iomem;
176 u16 cmdq_bar_reg;
177 u16 cmdq_bar_reg_prod_off;
178 u16 cmdq_bar_reg_trig_off;
179 u16 creq_ring_id;
180 u16 creq_bar_reg;
181 void __iomem *creq_bar_reg_iomem;
182
183 /* Cmd-Resp and Async Event notification queue */
184 struct bnxt_qplib_hwq creq;
185 u64 creq_qp_event_processed;
186 u64 creq_func_event_processed;
187
188 /* Actual Cmd and Resp Queues */
189 struct bnxt_qplib_hwq cmdq;
190 struct bnxt_qplib_crsq *crsqe_tbl;
191 int qp_tbl_size;
192 struct bnxt_qplib_qp_node *qp_tbl;
193 };
194
195 void bnxt_qplib_free_rcfw_channel(struct bnxt_qplib_rcfw *rcfw);
196 int bnxt_qplib_alloc_rcfw_channel(struct pci_dev *pdev,
197 struct bnxt_qplib_rcfw *rcfw, int qp_tbl_sz);
198 void bnxt_qplib_disable_rcfw_channel(struct bnxt_qplib_rcfw *rcfw);
199 int bnxt_qplib_enable_rcfw_channel(struct pci_dev *pdev,
200 struct bnxt_qplib_rcfw *rcfw,
201 int msix_vector,
202 int cp_bar_reg_off, int virt_fn,
203 int (*aeq_handler)
204 (struct bnxt_qplib_rcfw *,
205 struct creq_func_event *));
206
207 struct bnxt_qplib_rcfw_sbuf *bnxt_qplib_rcfw_alloc_sbuf(
208 struct bnxt_qplib_rcfw *rcfw,
209 u32 size);
210 void bnxt_qplib_rcfw_free_sbuf(struct bnxt_qplib_rcfw *rcfw,
211 struct bnxt_qplib_rcfw_sbuf *sbuf);
212 int bnxt_qplib_rcfw_send_message(struct bnxt_qplib_rcfw *rcfw,
213 struct cmdq_base *req, struct creq_base *resp,
214 void *sbuf, u8 is_block);
215
216 int bnxt_qplib_deinit_rcfw(struct bnxt_qplib_rcfw *rcfw);
217 int bnxt_qplib_init_rcfw(struct bnxt_qplib_rcfw *rcfw,
218 struct bnxt_qplib_ctx *ctx, int is_virtfn);
219 void bnxt_qplib_mark_qp_error(void *qp_handle);
220 #endif /* __BNXT_QPLIB_RCFW_H__ */
221