1 /* 2 * Copyright (C) 2006-2010 Texas Instruments Inc 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation version 2. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 #ifndef _VPBE_OSD_REGS_H 14 #define _VPBE_OSD_REGS_H 15 16 /* VPBE Global Registers */ 17 #define VPBE_PID 0x0 18 #define VPBE_PCR 0x4 19 20 /* VPSS CLock Registers */ 21 #define VPSSCLK_PID 0x00 22 #define VPSSCLK_CLKCTRL 0x04 23 24 /* VPSS Buffer Logic Registers */ 25 #define VPSSBL_PID 0x00 26 #define VPSSBL_PCR 0x04 27 #define VPSSBL_BCR 0x08 28 #define VPSSBL_INTSTAT 0x0C 29 #define VPSSBL_INTSEL 0x10 30 #define VPSSBL_EVTSEL 0x14 31 #define VPSSBL_MEMCTRL 0x18 32 #define VPSSBL_CCDCMUX 0x1C 33 34 /* DM365 ISP5 system configuration */ 35 #define ISP5_PID 0x0 36 #define ISP5_PCCR 0x4 37 #define ISP5_BCR 0x8 38 #define ISP5_INTSTAT 0xC 39 #define ISP5_INTSEL1 0x10 40 #define ISP5_INTSEL2 0x14 41 #define ISP5_INTSEL3 0x18 42 #define ISP5_EVTSEL 0x1c 43 #define ISP5_CCDCMUX 0x20 44 45 /* VPBE On-Screen Display Subsystem Registers (OSD) */ 46 #define OSD_MODE 0x00 47 #define OSD_VIDWINMD 0x04 48 #define OSD_OSDWIN0MD 0x08 49 #define OSD_OSDWIN1MD 0x0C 50 #define OSD_OSDATRMD 0x0C 51 #define OSD_RECTCUR 0x10 52 #define OSD_VIDWIN0OFST 0x18 53 #define OSD_VIDWIN1OFST 0x1C 54 #define OSD_OSDWIN0OFST 0x20 55 #define OSD_OSDWIN1OFST 0x24 56 #define OSD_VIDWINADH 0x28 57 #define OSD_VIDWIN0ADL 0x2C 58 #define OSD_VIDWIN0ADR 0x2C 59 #define OSD_VIDWIN1ADL 0x30 60 #define OSD_VIDWIN1ADR 0x30 61 #define OSD_OSDWINADH 0x34 62 #define OSD_OSDWIN0ADL 0x38 63 #define OSD_OSDWIN0ADR 0x38 64 #define OSD_OSDWIN1ADL 0x3C 65 #define OSD_OSDWIN1ADR 0x3C 66 #define OSD_BASEPX 0x40 67 #define OSD_BASEPY 0x44 68 #define OSD_VIDWIN0XP 0x48 69 #define OSD_VIDWIN0YP 0x4C 70 #define OSD_VIDWIN0XL 0x50 71 #define OSD_VIDWIN0YL 0x54 72 #define OSD_VIDWIN1XP 0x58 73 #define OSD_VIDWIN1YP 0x5C 74 #define OSD_VIDWIN1XL 0x60 75 #define OSD_VIDWIN1YL 0x64 76 #define OSD_OSDWIN0XP 0x68 77 #define OSD_OSDWIN0YP 0x6C 78 #define OSD_OSDWIN0XL 0x70 79 #define OSD_OSDWIN0YL 0x74 80 #define OSD_OSDWIN1XP 0x78 81 #define OSD_OSDWIN1YP 0x7C 82 #define OSD_OSDWIN1XL 0x80 83 #define OSD_OSDWIN1YL 0x84 84 #define OSD_CURXP 0x88 85 #define OSD_CURYP 0x8C 86 #define OSD_CURXL 0x90 87 #define OSD_CURYL 0x94 88 #define OSD_W0BMP01 0xA0 89 #define OSD_W0BMP23 0xA4 90 #define OSD_W0BMP45 0xA8 91 #define OSD_W0BMP67 0xAC 92 #define OSD_W0BMP89 0xB0 93 #define OSD_W0BMPAB 0xB4 94 #define OSD_W0BMPCD 0xB8 95 #define OSD_W0BMPEF 0xBC 96 #define OSD_W1BMP01 0xC0 97 #define OSD_W1BMP23 0xC4 98 #define OSD_W1BMP45 0xC8 99 #define OSD_W1BMP67 0xCC 100 #define OSD_W1BMP89 0xD0 101 #define OSD_W1BMPAB 0xD4 102 #define OSD_W1BMPCD 0xD8 103 #define OSD_W1BMPEF 0xDC 104 #define OSD_VBNDRY 0xE0 105 #define OSD_EXTMODE 0xE4 106 #define OSD_MISCCTL 0xE8 107 #define OSD_CLUTRAMYCB 0xEC 108 #define OSD_CLUTRAMCR 0xF0 109 #define OSD_TRANSPVAL 0xF4 110 #define OSD_TRANSPVALL 0xF4 111 #define OSD_TRANSPVALU 0xF8 112 #define OSD_TRANSPBMPIDX 0xFC 113 #define OSD_PPVWIN0ADR 0xFC 114 115 /* bit definitions */ 116 #define VPBE_PCR_VENC_DIV (1 << 1) 117 #define VPBE_PCR_CLK_OFF (1 << 0) 118 119 #define VPSSBL_INTSTAT_HSSIINT (1 << 14) 120 #define VPSSBL_INTSTAT_CFALDINT (1 << 13) 121 #define VPSSBL_INTSTAT_IPIPE_INT5 (1 << 12) 122 #define VPSSBL_INTSTAT_IPIPE_INT4 (1 << 11) 123 #define VPSSBL_INTSTAT_IPIPE_INT3 (1 << 10) 124 #define VPSSBL_INTSTAT_IPIPE_INT2 (1 << 9) 125 #define VPSSBL_INTSTAT_IPIPE_INT1 (1 << 8) 126 #define VPSSBL_INTSTAT_IPIPE_INT0 (1 << 7) 127 #define VPSSBL_INTSTAT_IPIPEIFINT (1 << 6) 128 #define VPSSBL_INTSTAT_OSDINT (1 << 5) 129 #define VPSSBL_INTSTAT_VENCINT (1 << 4) 130 #define VPSSBL_INTSTAT_H3AINT (1 << 3) 131 #define VPSSBL_INTSTAT_CCDC_VDINT2 (1 << 2) 132 #define VPSSBL_INTSTAT_CCDC_VDINT1 (1 << 1) 133 #define VPSSBL_INTSTAT_CCDC_VDINT0 (1 << 0) 134 135 /* DM365 ISP5 bit definitions */ 136 #define ISP5_INTSTAT_VENCINT (1 << 21) 137 #define ISP5_INTSTAT_OSDINT (1 << 20) 138 139 /* VMOD TVTYP options for HDMD=0 */ 140 #define SDTV_NTSC 0 141 #define SDTV_PAL 1 142 /* VMOD TVTYP options for HDMD=1 */ 143 #define HDTV_525P 0 144 #define HDTV_625P 1 145 #define HDTV_1080I 2 146 #define HDTV_720P 3 147 148 #define OSD_MODE_CS (1 << 15) 149 #define OSD_MODE_OVRSZ (1 << 14) 150 #define OSD_MODE_OHRSZ (1 << 13) 151 #define OSD_MODE_EF (1 << 12) 152 #define OSD_MODE_VVRSZ (1 << 11) 153 #define OSD_MODE_VHRSZ (1 << 10) 154 #define OSD_MODE_FSINV (1 << 9) 155 #define OSD_MODE_BCLUT (1 << 8) 156 #define OSD_MODE_CABG_SHIFT 0 157 #define OSD_MODE_CABG (0xff << 0) 158 159 #define OSD_VIDWINMD_VFINV (1 << 15) 160 #define OSD_VIDWINMD_V1EFC (1 << 14) 161 #define OSD_VIDWINMD_VHZ1_SHIFT 12 162 #define OSD_VIDWINMD_VHZ1 (3 << 12) 163 #define OSD_VIDWINMD_VVZ1_SHIFT 10 164 #define OSD_VIDWINMD_VVZ1 (3 << 10) 165 #define OSD_VIDWINMD_VFF1 (1 << 9) 166 #define OSD_VIDWINMD_ACT1 (1 << 8) 167 #define OSD_VIDWINMD_V0EFC (1 << 6) 168 #define OSD_VIDWINMD_VHZ0_SHIFT 4 169 #define OSD_VIDWINMD_VHZ0 (3 << 4) 170 #define OSD_VIDWINMD_VVZ0_SHIFT 2 171 #define OSD_VIDWINMD_VVZ0 (3 << 2) 172 #define OSD_VIDWINMD_VFF0 (1 << 1) 173 #define OSD_VIDWINMD_ACT0 (1 << 0) 174 175 #define OSD_OSDWIN0MD_ATN0E (1 << 14) 176 #define OSD_OSDWIN0MD_RGB0E (1 << 13) 177 #define OSD_OSDWIN0MD_BMP0MD_SHIFT 13 178 #define OSD_OSDWIN0MD_BMP0MD (3 << 13) 179 #define OSD_OSDWIN0MD_CLUTS0 (1 << 12) 180 #define OSD_OSDWIN0MD_OHZ0_SHIFT 10 181 #define OSD_OSDWIN0MD_OHZ0 (3 << 10) 182 #define OSD_OSDWIN0MD_OVZ0_SHIFT 8 183 #define OSD_OSDWIN0MD_OVZ0 (3 << 8) 184 #define OSD_OSDWIN0MD_BMW0_SHIFT 6 185 #define OSD_OSDWIN0MD_BMW0 (3 << 6) 186 #define OSD_OSDWIN0MD_BLND0_SHIFT 3 187 #define OSD_OSDWIN0MD_BLND0 (7 << 3) 188 #define OSD_OSDWIN0MD_TE0 (1 << 2) 189 #define OSD_OSDWIN0MD_OFF0 (1 << 1) 190 #define OSD_OSDWIN0MD_OACT0 (1 << 0) 191 192 #define OSD_OSDWIN1MD_OASW (1 << 15) 193 #define OSD_OSDWIN1MD_ATN1E (1 << 14) 194 #define OSD_OSDWIN1MD_RGB1E (1 << 13) 195 #define OSD_OSDWIN1MD_BMP1MD_SHIFT 13 196 #define OSD_OSDWIN1MD_BMP1MD (3 << 13) 197 #define OSD_OSDWIN1MD_CLUTS1 (1 << 12) 198 #define OSD_OSDWIN1MD_OHZ1_SHIFT 10 199 #define OSD_OSDWIN1MD_OHZ1 (3 << 10) 200 #define OSD_OSDWIN1MD_OVZ1_SHIFT 8 201 #define OSD_OSDWIN1MD_OVZ1 (3 << 8) 202 #define OSD_OSDWIN1MD_BMW1_SHIFT 6 203 #define OSD_OSDWIN1MD_BMW1 (3 << 6) 204 #define OSD_OSDWIN1MD_BLND1_SHIFT 3 205 #define OSD_OSDWIN1MD_BLND1 (7 << 3) 206 #define OSD_OSDWIN1MD_TE1 (1 << 2) 207 #define OSD_OSDWIN1MD_OFF1 (1 << 1) 208 #define OSD_OSDWIN1MD_OACT1 (1 << 0) 209 210 #define OSD_OSDATRMD_OASW (1 << 15) 211 #define OSD_OSDATRMD_OHZA_SHIFT 10 212 #define OSD_OSDATRMD_OHZA (3 << 10) 213 #define OSD_OSDATRMD_OVZA_SHIFT 8 214 #define OSD_OSDATRMD_OVZA (3 << 8) 215 #define OSD_OSDATRMD_BLNKINT_SHIFT 6 216 #define OSD_OSDATRMD_BLNKINT (3 << 6) 217 #define OSD_OSDATRMD_OFFA (1 << 1) 218 #define OSD_OSDATRMD_BLNK (1 << 0) 219 220 #define OSD_RECTCUR_RCAD_SHIFT 8 221 #define OSD_RECTCUR_RCAD (0xff << 8) 222 #define OSD_RECTCUR_CLUTSR (1 << 7) 223 #define OSD_RECTCUR_RCHW_SHIFT 4 224 #define OSD_RECTCUR_RCHW (7 << 4) 225 #define OSD_RECTCUR_RCVW_SHIFT 1 226 #define OSD_RECTCUR_RCVW (7 << 1) 227 #define OSD_RECTCUR_RCACT (1 << 0) 228 229 #define OSD_VIDWIN0OFST_V0LO (0x1ff << 0) 230 231 #define OSD_VIDWIN1OFST_V1LO (0x1ff << 0) 232 233 #define OSD_OSDWIN0OFST_O0LO (0x1ff << 0) 234 235 #define OSD_OSDWIN1OFST_O1LO (0x1ff << 0) 236 237 #define OSD_WINOFST_AH_SHIFT 9 238 239 #define OSD_VIDWIN0OFST_V0AH (0xf << 9) 240 #define OSD_VIDWIN1OFST_V1AH (0xf << 9) 241 #define OSD_OSDWIN0OFST_O0AH (0xf << 9) 242 #define OSD_OSDWIN1OFST_O1AH (0xf << 9) 243 244 #define OSD_VIDWINADH_V1AH_SHIFT 8 245 #define OSD_VIDWINADH_V1AH (0x7f << 8) 246 #define OSD_VIDWINADH_V0AH_SHIFT 0 247 #define OSD_VIDWINADH_V0AH (0x7f << 0) 248 249 #define OSD_VIDWIN0ADL_V0AL (0xffff << 0) 250 251 #define OSD_VIDWIN1ADL_V1AL (0xffff << 0) 252 253 #define OSD_OSDWINADH_O1AH_SHIFT 8 254 #define OSD_OSDWINADH_O1AH (0x7f << 8) 255 #define OSD_OSDWINADH_O0AH_SHIFT 0 256 #define OSD_OSDWINADH_O0AH (0x7f << 0) 257 258 #define OSD_OSDWIN0ADL_O0AL (0xffff << 0) 259 260 #define OSD_OSDWIN1ADL_O1AL (0xffff << 0) 261 262 #define OSD_BASEPX_BPX (0x3ff << 0) 263 264 #define OSD_BASEPY_BPY (0x1ff << 0) 265 266 #define OSD_VIDWIN0XP_V0X (0x7ff << 0) 267 268 #define OSD_VIDWIN0YP_V0Y (0x7ff << 0) 269 270 #define OSD_VIDWIN0XL_V0W (0x7ff << 0) 271 272 #define OSD_VIDWIN0YL_V0H (0x7ff << 0) 273 274 #define OSD_VIDWIN1XP_V1X (0x7ff << 0) 275 276 #define OSD_VIDWIN1YP_V1Y (0x7ff << 0) 277 278 #define OSD_VIDWIN1XL_V1W (0x7ff << 0) 279 280 #define OSD_VIDWIN1YL_V1H (0x7ff << 0) 281 282 #define OSD_OSDWIN0XP_W0X (0x7ff << 0) 283 284 #define OSD_OSDWIN0YP_W0Y (0x7ff << 0) 285 286 #define OSD_OSDWIN0XL_W0W (0x7ff << 0) 287 288 #define OSD_OSDWIN0YL_W0H (0x7ff << 0) 289 290 #define OSD_OSDWIN1XP_W1X (0x7ff << 0) 291 292 #define OSD_OSDWIN1YP_W1Y (0x7ff << 0) 293 294 #define OSD_OSDWIN1XL_W1W (0x7ff << 0) 295 296 #define OSD_OSDWIN1YL_W1H (0x7ff << 0) 297 298 #define OSD_CURXP_RCSX (0x7ff << 0) 299 300 #define OSD_CURYP_RCSY (0x7ff << 0) 301 302 #define OSD_CURXL_RCSW (0x7ff << 0) 303 304 #define OSD_CURYL_RCSH (0x7ff << 0) 305 306 #define OSD_EXTMODE_EXPMDSEL (1 << 15) 307 #define OSD_EXTMODE_SCRNHEXP_SHIFT 13 308 #define OSD_EXTMODE_SCRNHEXP (3 << 13) 309 #define OSD_EXTMODE_SCRNVEXP (1 << 12) 310 #define OSD_EXTMODE_OSD1BLDCHR (1 << 11) 311 #define OSD_EXTMODE_OSD0BLDCHR (1 << 10) 312 #define OSD_EXTMODE_ATNOSD1EN (1 << 9) 313 #define OSD_EXTMODE_ATNOSD0EN (1 << 8) 314 #define OSD_EXTMODE_OSDHRSZ15 (1 << 7) 315 #define OSD_EXTMODE_VIDHRSZ15 (1 << 6) 316 #define OSD_EXTMODE_ZMFILV1HEN (1 << 5) 317 #define OSD_EXTMODE_ZMFILV1VEN (1 << 4) 318 #define OSD_EXTMODE_ZMFILV0HEN (1 << 3) 319 #define OSD_EXTMODE_ZMFILV0VEN (1 << 2) 320 #define OSD_EXTMODE_EXPFILHEN (1 << 1) 321 #define OSD_EXTMODE_EXPFILVEN (1 << 0) 322 323 #define OSD_MISCCTL_BLDSEL (1 << 15) 324 #define OSD_MISCCTL_S420D (1 << 14) 325 #define OSD_MISCCTL_BMAPT (1 << 13) 326 #define OSD_MISCCTL_DM365M (1 << 12) 327 #define OSD_MISCCTL_RGBEN (1 << 7) 328 #define OSD_MISCCTL_RGBWIN (1 << 6) 329 #define OSD_MISCCTL_DMANG (1 << 6) 330 #define OSD_MISCCTL_TMON (1 << 5) 331 #define OSD_MISCCTL_RSEL (1 << 4) 332 #define OSD_MISCCTL_CPBSY (1 << 3) 333 #define OSD_MISCCTL_PPSW (1 << 2) 334 #define OSD_MISCCTL_PPRV (1 << 1) 335 336 #define OSD_CLUTRAMYCB_Y_SHIFT 8 337 #define OSD_CLUTRAMYCB_Y (0xff << 8) 338 #define OSD_CLUTRAMYCB_CB_SHIFT 0 339 #define OSD_CLUTRAMYCB_CB (0xff << 0) 340 341 #define OSD_CLUTRAMCR_CR_SHIFT 8 342 #define OSD_CLUTRAMCR_CR (0xff << 8) 343 #define OSD_CLUTRAMCR_CADDR_SHIFT 0 344 #define OSD_CLUTRAMCR_CADDR (0xff << 0) 345 346 #define OSD_TRANSPVAL_RGBTRANS (0xffff << 0) 347 348 #define OSD_TRANSPVALL_RGBL (0xffff << 0) 349 350 #define OSD_TRANSPVALU_Y_SHIFT 8 351 #define OSD_TRANSPVALU_Y (0xff << 8) 352 #define OSD_TRANSPVALU_RGBU_SHIFT 0 353 #define OSD_TRANSPVALU_RGBU (0xff << 0) 354 355 #define OSD_TRANSPBMPIDX_BMP1_SHIFT 8 356 #define OSD_TRANSPBMPIDX_BMP1 (0xff << 8) 357 #define OSD_TRANSPBMPIDX_BMP0_SHIFT 0 358 #define OSD_TRANSPBMPIDX_BMP0 0xff 359 360 #endif /* _DAVINCI_VPBE_H_ */ 361