1 /*
2 * Common Flash Interface support:
3 * AMD & Fujitsu Standard Vendor Command Set (ID 0x0002)
4 *
5 * Copyright (C) 2000 Crossnet Co. <info@crossnet.co.jp>
6 * Copyright (C) 2004 Arcom Control Systems Ltd <linux@arcom.com>
7 * Copyright (C) 2005 MontaVista Software Inc. <source@mvista.com>
8 *
9 * 2_by_8 routines added by Simon Munton
10 *
11 * 4_by_16 work by Carolyn J. Smith
12 *
13 * XIP support hooks by Vitaly Wool (based on code for Intel flash
14 * by Nicolas Pitre)
15 *
16 * 25/09/2008 Christopher Moore: TopBottom fixup for many Macronix with CFI V1.0
17 *
18 * Occasionally maintained by Thayne Harbaugh tharbaugh at lnxi dot com
19 *
20 * This code is GPL
21 */
22
23 #include <linux/module.h>
24 #include <linux/types.h>
25 #include <linux/kernel.h>
26 #include <linux/sched.h>
27 #include <asm/io.h>
28 #include <asm/byteorder.h>
29
30 #include <linux/errno.h>
31 #include <linux/slab.h>
32 #include <linux/delay.h>
33 #include <linux/interrupt.h>
34 #include <linux/reboot.h>
35 #include <linux/of.h>
36 #include <linux/of_platform.h>
37 #include <linux/mtd/map.h>
38 #include <linux/mtd/mtd.h>
39 #include <linux/mtd/cfi.h>
40 #include <linux/mtd/xip.h>
41
42 #define AMD_BOOTLOC_BUG
43 #define FORCE_WORD_WRITE 0
44
45 #define MAX_RETRIES 3
46
47 #define SST49LF004B 0x0060
48 #define SST49LF040B 0x0050
49 #define SST49LF008A 0x005a
50 #define AT49BV6416 0x00d6
51
52 static int cfi_amdstd_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
53 static int cfi_amdstd_write_words(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
54 static int cfi_amdstd_write_buffers(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
55 static int cfi_amdstd_erase_chip(struct mtd_info *, struct erase_info *);
56 static int cfi_amdstd_erase_varsize(struct mtd_info *, struct erase_info *);
57 static void cfi_amdstd_sync (struct mtd_info *);
58 static int cfi_amdstd_suspend (struct mtd_info *);
59 static void cfi_amdstd_resume (struct mtd_info *);
60 static int cfi_amdstd_reboot(struct notifier_block *, unsigned long, void *);
61 static int cfi_amdstd_get_fact_prot_info(struct mtd_info *, size_t,
62 size_t *, struct otp_info *);
63 static int cfi_amdstd_get_user_prot_info(struct mtd_info *, size_t,
64 size_t *, struct otp_info *);
65 static int cfi_amdstd_secsi_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
66 static int cfi_amdstd_read_fact_prot_reg(struct mtd_info *, loff_t, size_t,
67 size_t *, u_char *);
68 static int cfi_amdstd_read_user_prot_reg(struct mtd_info *, loff_t, size_t,
69 size_t *, u_char *);
70 static int cfi_amdstd_write_user_prot_reg(struct mtd_info *, loff_t, size_t,
71 size_t *, u_char *);
72 static int cfi_amdstd_lock_user_prot_reg(struct mtd_info *, loff_t, size_t);
73
74 static int cfi_amdstd_panic_write(struct mtd_info *mtd, loff_t to, size_t len,
75 size_t *retlen, const u_char *buf);
76
77 static void cfi_amdstd_destroy(struct mtd_info *);
78
79 struct mtd_info *cfi_cmdset_0002(struct map_info *, int);
80 static struct mtd_info *cfi_amdstd_setup (struct mtd_info *);
81
82 static int get_chip(struct map_info *map, struct flchip *chip, unsigned long adr, int mode);
83 static void put_chip(struct map_info *map, struct flchip *chip, unsigned long adr);
84 #include "fwh_lock.h"
85
86 static int cfi_atmel_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
87 static int cfi_atmel_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
88
89 static int cfi_ppb_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
90 static int cfi_ppb_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
91 static int cfi_ppb_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len);
92
93 static struct mtd_chip_driver cfi_amdstd_chipdrv = {
94 .probe = NULL, /* Not usable directly */
95 .destroy = cfi_amdstd_destroy,
96 .name = "cfi_cmdset_0002",
97 .module = THIS_MODULE
98 };
99
100
101 /* #define DEBUG_CFI_FEATURES */
102
103
104 #ifdef DEBUG_CFI_FEATURES
cfi_tell_features(struct cfi_pri_amdstd * extp)105 static void cfi_tell_features(struct cfi_pri_amdstd *extp)
106 {
107 const char* erase_suspend[3] = {
108 "Not supported", "Read only", "Read/write"
109 };
110 const char* top_bottom[6] = {
111 "No WP", "8x8KiB sectors at top & bottom, no WP",
112 "Bottom boot", "Top boot",
113 "Uniform, Bottom WP", "Uniform, Top WP"
114 };
115
116 printk(" Silicon revision: %d\n", extp->SiliconRevision >> 1);
117 printk(" Address sensitive unlock: %s\n",
118 (extp->SiliconRevision & 1) ? "Not required" : "Required");
119
120 if (extp->EraseSuspend < ARRAY_SIZE(erase_suspend))
121 printk(" Erase Suspend: %s\n", erase_suspend[extp->EraseSuspend]);
122 else
123 printk(" Erase Suspend: Unknown value %d\n", extp->EraseSuspend);
124
125 if (extp->BlkProt == 0)
126 printk(" Block protection: Not supported\n");
127 else
128 printk(" Block protection: %d sectors per group\n", extp->BlkProt);
129
130
131 printk(" Temporary block unprotect: %s\n",
132 extp->TmpBlkUnprotect ? "Supported" : "Not supported");
133 printk(" Block protect/unprotect scheme: %d\n", extp->BlkProtUnprot);
134 printk(" Number of simultaneous operations: %d\n", extp->SimultaneousOps);
135 printk(" Burst mode: %s\n",
136 extp->BurstMode ? "Supported" : "Not supported");
137 if (extp->PageMode == 0)
138 printk(" Page mode: Not supported\n");
139 else
140 printk(" Page mode: %d word page\n", extp->PageMode << 2);
141
142 printk(" Vpp Supply Minimum Program/Erase Voltage: %d.%d V\n",
143 extp->VppMin >> 4, extp->VppMin & 0xf);
144 printk(" Vpp Supply Maximum Program/Erase Voltage: %d.%d V\n",
145 extp->VppMax >> 4, extp->VppMax & 0xf);
146
147 if (extp->TopBottom < ARRAY_SIZE(top_bottom))
148 printk(" Top/Bottom Boot Block: %s\n", top_bottom[extp->TopBottom]);
149 else
150 printk(" Top/Bottom Boot Block: Unknown value %d\n", extp->TopBottom);
151 }
152 #endif
153
154 #ifdef AMD_BOOTLOC_BUG
155 /* Wheee. Bring me the head of someone at AMD. */
fixup_amd_bootblock(struct mtd_info * mtd)156 static void fixup_amd_bootblock(struct mtd_info *mtd)
157 {
158 struct map_info *map = mtd->priv;
159 struct cfi_private *cfi = map->fldrv_priv;
160 struct cfi_pri_amdstd *extp = cfi->cmdset_priv;
161 __u8 major = extp->MajorVersion;
162 __u8 minor = extp->MinorVersion;
163
164 if (((major << 8) | minor) < 0x3131) {
165 /* CFI version 1.0 => don't trust bootloc */
166
167 pr_debug("%s: JEDEC Vendor ID is 0x%02X Device ID is 0x%02X\n",
168 map->name, cfi->mfr, cfi->id);
169
170 /* AFAICS all 29LV400 with a bottom boot block have a device ID
171 * of 0x22BA in 16-bit mode and 0xBA in 8-bit mode.
172 * These were badly detected as they have the 0x80 bit set
173 * so treat them as a special case.
174 */
175 if (((cfi->id == 0xBA) || (cfi->id == 0x22BA)) &&
176
177 /* Macronix added CFI to their 2nd generation
178 * MX29LV400C B/T but AFAICS no other 29LV400 (AMD,
179 * Fujitsu, Spansion, EON, ESI and older Macronix)
180 * has CFI.
181 *
182 * Therefore also check the manufacturer.
183 * This reduces the risk of false detection due to
184 * the 8-bit device ID.
185 */
186 (cfi->mfr == CFI_MFR_MACRONIX)) {
187 pr_debug("%s: Macronix MX29LV400C with bottom boot block"
188 " detected\n", map->name);
189 extp->TopBottom = 2; /* bottom boot */
190 } else
191 if (cfi->id & 0x80) {
192 printk(KERN_WARNING "%s: JEDEC Device ID is 0x%02X. Assuming broken CFI table.\n", map->name, cfi->id);
193 extp->TopBottom = 3; /* top boot */
194 } else {
195 extp->TopBottom = 2; /* bottom boot */
196 }
197
198 pr_debug("%s: AMD CFI PRI V%c.%c has no boot block field;"
199 " deduced %s from Device ID\n", map->name, major, minor,
200 extp->TopBottom == 2 ? "bottom" : "top");
201 }
202 }
203 #endif
204
fixup_use_write_buffers(struct mtd_info * mtd)205 static void fixup_use_write_buffers(struct mtd_info *mtd)
206 {
207 struct map_info *map = mtd->priv;
208 struct cfi_private *cfi = map->fldrv_priv;
209 if (cfi->cfiq->BufWriteTimeoutTyp) {
210 pr_debug("Using buffer write method\n" );
211 mtd->_write = cfi_amdstd_write_buffers;
212 }
213 }
214
215 /* Atmel chips don't use the same PRI format as AMD chips */
fixup_convert_atmel_pri(struct mtd_info * mtd)216 static void fixup_convert_atmel_pri(struct mtd_info *mtd)
217 {
218 struct map_info *map = mtd->priv;
219 struct cfi_private *cfi = map->fldrv_priv;
220 struct cfi_pri_amdstd *extp = cfi->cmdset_priv;
221 struct cfi_pri_atmel atmel_pri;
222
223 memcpy(&atmel_pri, extp, sizeof(atmel_pri));
224 memset((char *)extp + 5, 0, sizeof(*extp) - 5);
225
226 if (atmel_pri.Features & 0x02)
227 extp->EraseSuspend = 2;
228
229 /* Some chips got it backwards... */
230 if (cfi->id == AT49BV6416) {
231 if (atmel_pri.BottomBoot)
232 extp->TopBottom = 3;
233 else
234 extp->TopBottom = 2;
235 } else {
236 if (atmel_pri.BottomBoot)
237 extp->TopBottom = 2;
238 else
239 extp->TopBottom = 3;
240 }
241
242 /* burst write mode not supported */
243 cfi->cfiq->BufWriteTimeoutTyp = 0;
244 cfi->cfiq->BufWriteTimeoutMax = 0;
245 }
246
fixup_use_secsi(struct mtd_info * mtd)247 static void fixup_use_secsi(struct mtd_info *mtd)
248 {
249 /* Setup for chips with a secsi area */
250 mtd->_read_user_prot_reg = cfi_amdstd_secsi_read;
251 mtd->_read_fact_prot_reg = cfi_amdstd_secsi_read;
252 }
253
fixup_use_erase_chip(struct mtd_info * mtd)254 static void fixup_use_erase_chip(struct mtd_info *mtd)
255 {
256 struct map_info *map = mtd->priv;
257 struct cfi_private *cfi = map->fldrv_priv;
258 if ((cfi->cfiq->NumEraseRegions == 1) &&
259 ((cfi->cfiq->EraseRegionInfo[0] & 0xffff) == 0)) {
260 mtd->_erase = cfi_amdstd_erase_chip;
261 }
262
263 }
264
265 /*
266 * Some Atmel chips (e.g. the AT49BV6416) power-up with all sectors
267 * locked by default.
268 */
fixup_use_atmel_lock(struct mtd_info * mtd)269 static void fixup_use_atmel_lock(struct mtd_info *mtd)
270 {
271 mtd->_lock = cfi_atmel_lock;
272 mtd->_unlock = cfi_atmel_unlock;
273 mtd->flags |= MTD_POWERUP_LOCK;
274 }
275
fixup_old_sst_eraseregion(struct mtd_info * mtd)276 static void fixup_old_sst_eraseregion(struct mtd_info *mtd)
277 {
278 struct map_info *map = mtd->priv;
279 struct cfi_private *cfi = map->fldrv_priv;
280
281 /*
282 * These flashes report two separate eraseblock regions based on the
283 * sector_erase-size and block_erase-size, although they both operate on the
284 * same memory. This is not allowed according to CFI, so we just pick the
285 * sector_erase-size.
286 */
287 cfi->cfiq->NumEraseRegions = 1;
288 }
289
fixup_sst39vf(struct mtd_info * mtd)290 static void fixup_sst39vf(struct mtd_info *mtd)
291 {
292 struct map_info *map = mtd->priv;
293 struct cfi_private *cfi = map->fldrv_priv;
294
295 fixup_old_sst_eraseregion(mtd);
296
297 cfi->addr_unlock1 = 0x5555;
298 cfi->addr_unlock2 = 0x2AAA;
299 }
300
fixup_sst39vf_rev_b(struct mtd_info * mtd)301 static void fixup_sst39vf_rev_b(struct mtd_info *mtd)
302 {
303 struct map_info *map = mtd->priv;
304 struct cfi_private *cfi = map->fldrv_priv;
305
306 fixup_old_sst_eraseregion(mtd);
307
308 cfi->addr_unlock1 = 0x555;
309 cfi->addr_unlock2 = 0x2AA;
310
311 cfi->sector_erase_cmd = CMD(0x50);
312 }
313
fixup_sst38vf640x_sectorsize(struct mtd_info * mtd)314 static void fixup_sst38vf640x_sectorsize(struct mtd_info *mtd)
315 {
316 struct map_info *map = mtd->priv;
317 struct cfi_private *cfi = map->fldrv_priv;
318
319 fixup_sst39vf_rev_b(mtd);
320
321 /*
322 * CFI reports 1024 sectors (0x03ff+1) of 64KBytes (0x0100*256) where
323 * it should report a size of 8KBytes (0x0020*256).
324 */
325 cfi->cfiq->EraseRegionInfo[0] = 0x002003ff;
326 pr_warn("%s: Bad 38VF640x CFI data; adjusting sector size from 64 to 8KiB\n",
327 mtd->name);
328 }
329
fixup_s29gl064n_sectors(struct mtd_info * mtd)330 static void fixup_s29gl064n_sectors(struct mtd_info *mtd)
331 {
332 struct map_info *map = mtd->priv;
333 struct cfi_private *cfi = map->fldrv_priv;
334
335 if ((cfi->cfiq->EraseRegionInfo[0] & 0xffff) == 0x003f) {
336 cfi->cfiq->EraseRegionInfo[0] |= 0x0040;
337 pr_warn("%s: Bad S29GL064N CFI data; adjust from 64 to 128 sectors\n",
338 mtd->name);
339 }
340 }
341
fixup_s29gl032n_sectors(struct mtd_info * mtd)342 static void fixup_s29gl032n_sectors(struct mtd_info *mtd)
343 {
344 struct map_info *map = mtd->priv;
345 struct cfi_private *cfi = map->fldrv_priv;
346
347 if ((cfi->cfiq->EraseRegionInfo[1] & 0xffff) == 0x007e) {
348 cfi->cfiq->EraseRegionInfo[1] &= ~0x0040;
349 pr_warn("%s: Bad S29GL032N CFI data; adjust from 127 to 63 sectors\n",
350 mtd->name);
351 }
352 }
353
fixup_s29ns512p_sectors(struct mtd_info * mtd)354 static void fixup_s29ns512p_sectors(struct mtd_info *mtd)
355 {
356 struct map_info *map = mtd->priv;
357 struct cfi_private *cfi = map->fldrv_priv;
358
359 /*
360 * S29NS512P flash uses more than 8bits to report number of sectors,
361 * which is not permitted by CFI.
362 */
363 cfi->cfiq->EraseRegionInfo[0] = 0x020001ff;
364 pr_warn("%s: Bad S29NS512P CFI data; adjust to 512 sectors\n",
365 mtd->name);
366 }
367
368 /* Used to fix CFI-Tables of chips without Extended Query Tables */
369 static struct cfi_fixup cfi_nopri_fixup_table[] = {
370 { CFI_MFR_SST, 0x234a, fixup_sst39vf }, /* SST39VF1602 */
371 { CFI_MFR_SST, 0x234b, fixup_sst39vf }, /* SST39VF1601 */
372 { CFI_MFR_SST, 0x235a, fixup_sst39vf }, /* SST39VF3202 */
373 { CFI_MFR_SST, 0x235b, fixup_sst39vf }, /* SST39VF3201 */
374 { CFI_MFR_SST, 0x235c, fixup_sst39vf_rev_b }, /* SST39VF3202B */
375 { CFI_MFR_SST, 0x235d, fixup_sst39vf_rev_b }, /* SST39VF3201B */
376 { CFI_MFR_SST, 0x236c, fixup_sst39vf_rev_b }, /* SST39VF6402B */
377 { CFI_MFR_SST, 0x236d, fixup_sst39vf_rev_b }, /* SST39VF6401B */
378 { 0, 0, NULL }
379 };
380
381 static struct cfi_fixup cfi_fixup_table[] = {
382 { CFI_MFR_ATMEL, CFI_ID_ANY, fixup_convert_atmel_pri },
383 #ifdef AMD_BOOTLOC_BUG
384 { CFI_MFR_AMD, CFI_ID_ANY, fixup_amd_bootblock },
385 { CFI_MFR_AMIC, CFI_ID_ANY, fixup_amd_bootblock },
386 { CFI_MFR_MACRONIX, CFI_ID_ANY, fixup_amd_bootblock },
387 #endif
388 { CFI_MFR_AMD, 0x0050, fixup_use_secsi },
389 { CFI_MFR_AMD, 0x0053, fixup_use_secsi },
390 { CFI_MFR_AMD, 0x0055, fixup_use_secsi },
391 { CFI_MFR_AMD, 0x0056, fixup_use_secsi },
392 { CFI_MFR_AMD, 0x005C, fixup_use_secsi },
393 { CFI_MFR_AMD, 0x005F, fixup_use_secsi },
394 { CFI_MFR_AMD, 0x0c01, fixup_s29gl064n_sectors },
395 { CFI_MFR_AMD, 0x1301, fixup_s29gl064n_sectors },
396 { CFI_MFR_AMD, 0x1a00, fixup_s29gl032n_sectors },
397 { CFI_MFR_AMD, 0x1a01, fixup_s29gl032n_sectors },
398 { CFI_MFR_AMD, 0x3f00, fixup_s29ns512p_sectors },
399 { CFI_MFR_SST, 0x536a, fixup_sst38vf640x_sectorsize }, /* SST38VF6402 */
400 { CFI_MFR_SST, 0x536b, fixup_sst38vf640x_sectorsize }, /* SST38VF6401 */
401 { CFI_MFR_SST, 0x536c, fixup_sst38vf640x_sectorsize }, /* SST38VF6404 */
402 { CFI_MFR_SST, 0x536d, fixup_sst38vf640x_sectorsize }, /* SST38VF6403 */
403 #if !FORCE_WORD_WRITE
404 { CFI_MFR_ANY, CFI_ID_ANY, fixup_use_write_buffers },
405 #endif
406 { 0, 0, NULL }
407 };
408 static struct cfi_fixup jedec_fixup_table[] = {
409 { CFI_MFR_SST, SST49LF004B, fixup_use_fwh_lock },
410 { CFI_MFR_SST, SST49LF040B, fixup_use_fwh_lock },
411 { CFI_MFR_SST, SST49LF008A, fixup_use_fwh_lock },
412 { 0, 0, NULL }
413 };
414
415 static struct cfi_fixup fixup_table[] = {
416 /* The CFI vendor ids and the JEDEC vendor IDs appear
417 * to be common. It is like the devices id's are as
418 * well. This table is to pick all cases where
419 * we know that is the case.
420 */
421 { CFI_MFR_ANY, CFI_ID_ANY, fixup_use_erase_chip },
422 { CFI_MFR_ATMEL, AT49BV6416, fixup_use_atmel_lock },
423 { 0, 0, NULL }
424 };
425
426
cfi_fixup_major_minor(struct cfi_private * cfi,struct cfi_pri_amdstd * extp)427 static void cfi_fixup_major_minor(struct cfi_private *cfi,
428 struct cfi_pri_amdstd *extp)
429 {
430 if (cfi->mfr == CFI_MFR_SAMSUNG) {
431 if ((extp->MajorVersion == '0' && extp->MinorVersion == '0') ||
432 (extp->MajorVersion == '3' && extp->MinorVersion == '3')) {
433 /*
434 * Samsung K8P2815UQB and K8D6x16UxM chips
435 * report major=0 / minor=0.
436 * K8D3x16UxC chips report major=3 / minor=3.
437 */
438 printk(KERN_NOTICE " Fixing Samsung's Amd/Fujitsu"
439 " Extended Query version to 1.%c\n",
440 extp->MinorVersion);
441 extp->MajorVersion = '1';
442 }
443 }
444
445 /*
446 * SST 38VF640x chips report major=0xFF / minor=0xFF.
447 */
448 if (cfi->mfr == CFI_MFR_SST && (cfi->id >> 4) == 0x0536) {
449 extp->MajorVersion = '1';
450 extp->MinorVersion = '0';
451 }
452 }
453
is_m29ew(struct cfi_private * cfi)454 static int is_m29ew(struct cfi_private *cfi)
455 {
456 if (cfi->mfr == CFI_MFR_INTEL &&
457 ((cfi->device_type == CFI_DEVICETYPE_X8 && (cfi->id & 0xff) == 0x7e) ||
458 (cfi->device_type == CFI_DEVICETYPE_X16 && cfi->id == 0x227e)))
459 return 1;
460 return 0;
461 }
462
463 /*
464 * From TN-13-07: Patching the Linux Kernel and U-Boot for M29 Flash, page 20:
465 * Some revisions of the M29EW suffer from erase suspend hang ups. In
466 * particular, it can occur when the sequence
467 * Erase Confirm -> Suspend -> Program -> Resume
468 * causes a lockup due to internal timing issues. The consequence is that the
469 * erase cannot be resumed without inserting a dummy command after programming
470 * and prior to resuming. [...] The work-around is to issue a dummy write cycle
471 * that writes an F0 command code before the RESUME command.
472 */
cfi_fixup_m29ew_erase_suspend(struct map_info * map,unsigned long adr)473 static void cfi_fixup_m29ew_erase_suspend(struct map_info *map,
474 unsigned long adr)
475 {
476 struct cfi_private *cfi = map->fldrv_priv;
477 /* before resume, insert a dummy 0xF0 cycle for Micron M29EW devices */
478 if (is_m29ew(cfi))
479 map_write(map, CMD(0xF0), adr);
480 }
481
482 /*
483 * From TN-13-07: Patching the Linux Kernel and U-Boot for M29 Flash, page 22:
484 *
485 * Some revisions of the M29EW (for example, A1 and A2 step revisions)
486 * are affected by a problem that could cause a hang up when an ERASE SUSPEND
487 * command is issued after an ERASE RESUME operation without waiting for a
488 * minimum delay. The result is that once the ERASE seems to be completed
489 * (no bits are toggling), the contents of the Flash memory block on which
490 * the erase was ongoing could be inconsistent with the expected values
491 * (typically, the array value is stuck to the 0xC0, 0xC4, 0x80, or 0x84
492 * values), causing a consequent failure of the ERASE operation.
493 * The occurrence of this issue could be high, especially when file system
494 * operations on the Flash are intensive. As a result, it is recommended
495 * that a patch be applied. Intensive file system operations can cause many
496 * calls to the garbage routine to free Flash space (also by erasing physical
497 * Flash blocks) and as a result, many consecutive SUSPEND and RESUME
498 * commands can occur. The problem disappears when a delay is inserted after
499 * the RESUME command by using the udelay() function available in Linux.
500 * The DELAY value must be tuned based on the customer's platform.
501 * The maximum value that fixes the problem in all cases is 500us.
502 * But, in our experience, a delay of 30 µs to 50 µs is sufficient
503 * in most cases.
504 * We have chosen 500µs because this latency is acceptable.
505 */
cfi_fixup_m29ew_delay_after_resume(struct cfi_private * cfi)506 static void cfi_fixup_m29ew_delay_after_resume(struct cfi_private *cfi)
507 {
508 /*
509 * Resolving the Delay After Resume Issue see Micron TN-13-07
510 * Worst case delay must be 500µs but 30-50µs should be ok as well
511 */
512 if (is_m29ew(cfi))
513 cfi_udelay(500);
514 }
515
cfi_cmdset_0002(struct map_info * map,int primary)516 struct mtd_info *cfi_cmdset_0002(struct map_info *map, int primary)
517 {
518 struct cfi_private *cfi = map->fldrv_priv;
519 struct device_node __maybe_unused *np = map->device_node;
520 struct mtd_info *mtd;
521 int i;
522
523 mtd = kzalloc(sizeof(*mtd), GFP_KERNEL);
524 if (!mtd)
525 return NULL;
526 mtd->priv = map;
527 mtd->type = MTD_NORFLASH;
528
529 /* Fill in the default mtd operations */
530 mtd->_erase = cfi_amdstd_erase_varsize;
531 mtd->_write = cfi_amdstd_write_words;
532 mtd->_read = cfi_amdstd_read;
533 mtd->_sync = cfi_amdstd_sync;
534 mtd->_suspend = cfi_amdstd_suspend;
535 mtd->_resume = cfi_amdstd_resume;
536 mtd->_read_user_prot_reg = cfi_amdstd_read_user_prot_reg;
537 mtd->_read_fact_prot_reg = cfi_amdstd_read_fact_prot_reg;
538 mtd->_get_fact_prot_info = cfi_amdstd_get_fact_prot_info;
539 mtd->_get_user_prot_info = cfi_amdstd_get_user_prot_info;
540 mtd->_write_user_prot_reg = cfi_amdstd_write_user_prot_reg;
541 mtd->_lock_user_prot_reg = cfi_amdstd_lock_user_prot_reg;
542 mtd->flags = MTD_CAP_NORFLASH;
543 mtd->name = map->name;
544 mtd->writesize = 1;
545 mtd->writebufsize = cfi_interleave(cfi) << cfi->cfiq->MaxBufWriteSize;
546
547 pr_debug("MTD %s(): write buffer size %d\n", __func__,
548 mtd->writebufsize);
549
550 mtd->_panic_write = cfi_amdstd_panic_write;
551 mtd->reboot_notifier.notifier_call = cfi_amdstd_reboot;
552
553 if (cfi->cfi_mode==CFI_MODE_CFI){
554 unsigned char bootloc;
555 __u16 adr = primary?cfi->cfiq->P_ADR:cfi->cfiq->A_ADR;
556 struct cfi_pri_amdstd *extp;
557
558 extp = (struct cfi_pri_amdstd*)cfi_read_pri(map, adr, sizeof(*extp), "Amd/Fujitsu");
559 if (extp) {
560 /*
561 * It's a real CFI chip, not one for which the probe
562 * routine faked a CFI structure.
563 */
564 cfi_fixup_major_minor(cfi, extp);
565
566 /*
567 * Valid primary extension versions are: 1.0, 1.1, 1.2, 1.3, 1.4, 1.5
568 * see: http://cs.ozerki.net/zap/pub/axim-x5/docs/cfi_r20.pdf, page 19
569 * http://www.spansion.com/Support/AppNotes/cfi_100_20011201.pdf
570 * http://www.spansion.com/Support/Datasheets/s29ws-p_00_a12_e.pdf
571 * http://www.spansion.com/Support/Datasheets/S29GL_128S_01GS_00_02_e.pdf
572 */
573 if (extp->MajorVersion != '1' ||
574 (extp->MajorVersion == '1' && (extp->MinorVersion < '0' || extp->MinorVersion > '5'))) {
575 printk(KERN_ERR " Unknown Amd/Fujitsu Extended Query "
576 "version %c.%c (%#02x/%#02x).\n",
577 extp->MajorVersion, extp->MinorVersion,
578 extp->MajorVersion, extp->MinorVersion);
579 kfree(extp);
580 kfree(mtd);
581 return NULL;
582 }
583
584 printk(KERN_INFO " Amd/Fujitsu Extended Query version %c.%c.\n",
585 extp->MajorVersion, extp->MinorVersion);
586
587 /* Install our own private info structure */
588 cfi->cmdset_priv = extp;
589
590 /* Apply cfi device specific fixups */
591 cfi_fixup(mtd, cfi_fixup_table);
592
593 #ifdef DEBUG_CFI_FEATURES
594 /* Tell the user about it in lots of lovely detail */
595 cfi_tell_features(extp);
596 #endif
597
598 #ifdef CONFIG_OF
599 if (np && of_property_read_bool(
600 np, "use-advanced-sector-protection")
601 && extp->BlkProtUnprot == 8) {
602 printk(KERN_INFO " Advanced Sector Protection (PPB Locking) supported\n");
603 mtd->_lock = cfi_ppb_lock;
604 mtd->_unlock = cfi_ppb_unlock;
605 mtd->_is_locked = cfi_ppb_is_locked;
606 }
607 #endif
608
609 bootloc = extp->TopBottom;
610 if ((bootloc < 2) || (bootloc > 5)) {
611 printk(KERN_WARNING "%s: CFI contains unrecognised boot "
612 "bank location (%d). Assuming bottom.\n",
613 map->name, bootloc);
614 bootloc = 2;
615 }
616
617 if (bootloc == 3 && cfi->cfiq->NumEraseRegions > 1) {
618 printk(KERN_WARNING "%s: Swapping erase regions for top-boot CFI table.\n", map->name);
619
620 for (i=0; i<cfi->cfiq->NumEraseRegions / 2; i++) {
621 int j = (cfi->cfiq->NumEraseRegions-1)-i;
622
623 swap(cfi->cfiq->EraseRegionInfo[i],
624 cfi->cfiq->EraseRegionInfo[j]);
625 }
626 }
627 /* Set the default CFI lock/unlock addresses */
628 cfi->addr_unlock1 = 0x555;
629 cfi->addr_unlock2 = 0x2aa;
630 }
631 cfi_fixup(mtd, cfi_nopri_fixup_table);
632
633 if (!cfi->addr_unlock1 || !cfi->addr_unlock2) {
634 kfree(mtd);
635 return NULL;
636 }
637
638 } /* CFI mode */
639 else if (cfi->cfi_mode == CFI_MODE_JEDEC) {
640 /* Apply jedec specific fixups */
641 cfi_fixup(mtd, jedec_fixup_table);
642 }
643 /* Apply generic fixups */
644 cfi_fixup(mtd, fixup_table);
645
646 for (i=0; i< cfi->numchips; i++) {
647 cfi->chips[i].word_write_time = 1<<cfi->cfiq->WordWriteTimeoutTyp;
648 cfi->chips[i].buffer_write_time = 1<<cfi->cfiq->BufWriteTimeoutTyp;
649 cfi->chips[i].erase_time = 1<<cfi->cfiq->BlockEraseTimeoutTyp;
650 /*
651 * First calculate the timeout max according to timeout field
652 * of struct cfi_ident that probed from chip's CFI aera, if
653 * available. Specify a minimum of 2000us, in case the CFI data
654 * is wrong.
655 */
656 if (cfi->cfiq->BufWriteTimeoutTyp &&
657 cfi->cfiq->BufWriteTimeoutMax)
658 cfi->chips[i].buffer_write_time_max =
659 1 << (cfi->cfiq->BufWriteTimeoutTyp +
660 cfi->cfiq->BufWriteTimeoutMax);
661 else
662 cfi->chips[i].buffer_write_time_max = 0;
663
664 cfi->chips[i].buffer_write_time_max =
665 max(cfi->chips[i].buffer_write_time_max, 2000);
666
667 cfi->chips[i].ref_point_counter = 0;
668 init_waitqueue_head(&(cfi->chips[i].wq));
669 }
670
671 map->fldrv = &cfi_amdstd_chipdrv;
672
673 return cfi_amdstd_setup(mtd);
674 }
675 struct mtd_info *cfi_cmdset_0006(struct map_info *map, int primary) __attribute__((alias("cfi_cmdset_0002")));
676 struct mtd_info *cfi_cmdset_0701(struct map_info *map, int primary) __attribute__((alias("cfi_cmdset_0002")));
677 EXPORT_SYMBOL_GPL(cfi_cmdset_0002);
678 EXPORT_SYMBOL_GPL(cfi_cmdset_0006);
679 EXPORT_SYMBOL_GPL(cfi_cmdset_0701);
680
cfi_amdstd_setup(struct mtd_info * mtd)681 static struct mtd_info *cfi_amdstd_setup(struct mtd_info *mtd)
682 {
683 struct map_info *map = mtd->priv;
684 struct cfi_private *cfi = map->fldrv_priv;
685 unsigned long devsize = (1<<cfi->cfiq->DevSize) * cfi->interleave;
686 unsigned long offset = 0;
687 int i,j;
688
689 printk(KERN_NOTICE "number of %s chips: %d\n",
690 (cfi->cfi_mode == CFI_MODE_CFI)?"CFI":"JEDEC",cfi->numchips);
691 /* Select the correct geometry setup */
692 mtd->size = devsize * cfi->numchips;
693
694 mtd->numeraseregions = cfi->cfiq->NumEraseRegions * cfi->numchips;
695 mtd->eraseregions = kmalloc(sizeof(struct mtd_erase_region_info)
696 * mtd->numeraseregions, GFP_KERNEL);
697 if (!mtd->eraseregions)
698 goto setup_err;
699
700 for (i=0; i<cfi->cfiq->NumEraseRegions; i++) {
701 unsigned long ernum, ersize;
702 ersize = ((cfi->cfiq->EraseRegionInfo[i] >> 8) & ~0xff) * cfi->interleave;
703 ernum = (cfi->cfiq->EraseRegionInfo[i] & 0xffff) + 1;
704
705 if (mtd->erasesize < ersize) {
706 mtd->erasesize = ersize;
707 }
708 for (j=0; j<cfi->numchips; j++) {
709 mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].offset = (j*devsize)+offset;
710 mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].erasesize = ersize;
711 mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].numblocks = ernum;
712 }
713 offset += (ersize * ernum);
714 }
715 if (offset != devsize) {
716 /* Argh */
717 printk(KERN_WARNING "Sum of regions (%lx) != total size of set of interleaved chips (%lx)\n", offset, devsize);
718 goto setup_err;
719 }
720
721 __module_get(THIS_MODULE);
722 register_reboot_notifier(&mtd->reboot_notifier);
723 return mtd;
724
725 setup_err:
726 kfree(mtd->eraseregions);
727 kfree(mtd);
728 kfree(cfi->cmdset_priv);
729 kfree(cfi->cfiq);
730 return NULL;
731 }
732
733 /*
734 * Return true if the chip is ready.
735 *
736 * Ready is one of: read mode, query mode, erase-suspend-read mode (in any
737 * non-suspended sector) and is indicated by no toggle bits toggling.
738 *
739 * Note that anything more complicated than checking if no bits are toggling
740 * (including checking DQ5 for an error status) is tricky to get working
741 * correctly and is therefore not done (particularly with interleaved chips
742 * as each chip must be checked independently of the others).
743 */
chip_ready(struct map_info * map,unsigned long addr)744 static int __xipram chip_ready(struct map_info *map, unsigned long addr)
745 {
746 map_word d, t;
747
748 d = map_read(map, addr);
749 t = map_read(map, addr);
750
751 return map_word_equal(map, d, t);
752 }
753
754 /*
755 * Return true if the chip is ready and has the correct value.
756 *
757 * Ready is one of: read mode, query mode, erase-suspend-read mode (in any
758 * non-suspended sector) and it is indicated by no bits toggling.
759 *
760 * Error are indicated by toggling bits or bits held with the wrong value,
761 * or with bits toggling.
762 *
763 * Note that anything more complicated than checking if no bits are toggling
764 * (including checking DQ5 for an error status) is tricky to get working
765 * correctly and is therefore not done (particularly with interleaved chips
766 * as each chip must be checked independently of the others).
767 *
768 */
chip_good(struct map_info * map,unsigned long addr,map_word expected)769 static int __xipram chip_good(struct map_info *map, unsigned long addr, map_word expected)
770 {
771 map_word oldd, curd;
772
773 oldd = map_read(map, addr);
774 curd = map_read(map, addr);
775
776 return map_word_equal(map, oldd, curd) &&
777 map_word_equal(map, curd, expected);
778 }
779
get_chip(struct map_info * map,struct flchip * chip,unsigned long adr,int mode)780 static int get_chip(struct map_info *map, struct flchip *chip, unsigned long adr, int mode)
781 {
782 DECLARE_WAITQUEUE(wait, current);
783 struct cfi_private *cfi = map->fldrv_priv;
784 unsigned long timeo;
785 struct cfi_pri_amdstd *cfip = (struct cfi_pri_amdstd *)cfi->cmdset_priv;
786
787 resettime:
788 timeo = jiffies + HZ;
789 retry:
790 switch (chip->state) {
791
792 case FL_STATUS:
793 for (;;) {
794 if (chip_ready(map, adr))
795 break;
796
797 if (time_after(jiffies, timeo)) {
798 printk(KERN_ERR "Waiting for chip to be ready timed out.\n");
799 return -EIO;
800 }
801 mutex_unlock(&chip->mutex);
802 cfi_udelay(1);
803 mutex_lock(&chip->mutex);
804 /* Someone else might have been playing with it. */
805 goto retry;
806 }
807
808 case FL_READY:
809 case FL_CFI_QUERY:
810 case FL_JEDEC_QUERY:
811 return 0;
812
813 case FL_ERASING:
814 if (!cfip || !(cfip->EraseSuspend & (0x1|0x2)) ||
815 !(mode == FL_READY || mode == FL_POINT ||
816 (mode == FL_WRITING && (cfip->EraseSuspend & 0x2))))
817 goto sleep;
818
819 /* Do not allow suspend iff read/write to EB address */
820 if ((adr & chip->in_progress_block_mask) ==
821 chip->in_progress_block_addr)
822 goto sleep;
823
824 /* Erase suspend */
825 /* It's harmless to issue the Erase-Suspend and Erase-Resume
826 * commands when the erase algorithm isn't in progress. */
827 map_write(map, CMD(0xB0), chip->in_progress_block_addr);
828 chip->oldstate = FL_ERASING;
829 chip->state = FL_ERASE_SUSPENDING;
830 chip->erase_suspended = 1;
831 for (;;) {
832 if (chip_ready(map, adr))
833 break;
834
835 if (time_after(jiffies, timeo)) {
836 /* Should have suspended the erase by now.
837 * Send an Erase-Resume command as either
838 * there was an error (so leave the erase
839 * routine to recover from it) or we trying to
840 * use the erase-in-progress sector. */
841 put_chip(map, chip, adr);
842 printk(KERN_ERR "MTD %s(): chip not ready after erase suspend\n", __func__);
843 return -EIO;
844 }
845
846 mutex_unlock(&chip->mutex);
847 cfi_udelay(1);
848 mutex_lock(&chip->mutex);
849 /* Nobody will touch it while it's in state FL_ERASE_SUSPENDING.
850 So we can just loop here. */
851 }
852 chip->state = FL_READY;
853 return 0;
854
855 case FL_XIP_WHILE_ERASING:
856 if (mode != FL_READY && mode != FL_POINT &&
857 (!cfip || !(cfip->EraseSuspend&2)))
858 goto sleep;
859 chip->oldstate = chip->state;
860 chip->state = FL_READY;
861 return 0;
862
863 case FL_SHUTDOWN:
864 /* The machine is rebooting */
865 return -EIO;
866
867 case FL_POINT:
868 /* Only if there's no operation suspended... */
869 if (mode == FL_READY && chip->oldstate == FL_READY)
870 return 0;
871
872 default:
873 sleep:
874 set_current_state(TASK_UNINTERRUPTIBLE);
875 add_wait_queue(&chip->wq, &wait);
876 mutex_unlock(&chip->mutex);
877 schedule();
878 remove_wait_queue(&chip->wq, &wait);
879 mutex_lock(&chip->mutex);
880 goto resettime;
881 }
882 }
883
884
put_chip(struct map_info * map,struct flchip * chip,unsigned long adr)885 static void put_chip(struct map_info *map, struct flchip *chip, unsigned long adr)
886 {
887 struct cfi_private *cfi = map->fldrv_priv;
888
889 switch(chip->oldstate) {
890 case FL_ERASING:
891 cfi_fixup_m29ew_erase_suspend(map,
892 chip->in_progress_block_addr);
893 map_write(map, cfi->sector_erase_cmd, chip->in_progress_block_addr);
894 cfi_fixup_m29ew_delay_after_resume(cfi);
895 chip->oldstate = FL_READY;
896 chip->state = FL_ERASING;
897 break;
898
899 case FL_XIP_WHILE_ERASING:
900 chip->state = chip->oldstate;
901 chip->oldstate = FL_READY;
902 break;
903
904 case FL_READY:
905 case FL_STATUS:
906 break;
907 default:
908 printk(KERN_ERR "MTD: put_chip() called with oldstate %d!!\n", chip->oldstate);
909 }
910 wake_up(&chip->wq);
911 }
912
913 #ifdef CONFIG_MTD_XIP
914
915 /*
916 * No interrupt what so ever can be serviced while the flash isn't in array
917 * mode. This is ensured by the xip_disable() and xip_enable() functions
918 * enclosing any code path where the flash is known not to be in array mode.
919 * And within a XIP disabled code path, only functions marked with __xipram
920 * may be called and nothing else (it's a good thing to inspect generated
921 * assembly to make sure inline functions were actually inlined and that gcc
922 * didn't emit calls to its own support functions). Also configuring MTD CFI
923 * support to a single buswidth and a single interleave is also recommended.
924 */
925
xip_disable(struct map_info * map,struct flchip * chip,unsigned long adr)926 static void xip_disable(struct map_info *map, struct flchip *chip,
927 unsigned long adr)
928 {
929 /* TODO: chips with no XIP use should ignore and return */
930 (void) map_read(map, adr); /* ensure mmu mapping is up to date */
931 local_irq_disable();
932 }
933
xip_enable(struct map_info * map,struct flchip * chip,unsigned long adr)934 static void __xipram xip_enable(struct map_info *map, struct flchip *chip,
935 unsigned long adr)
936 {
937 struct cfi_private *cfi = map->fldrv_priv;
938
939 if (chip->state != FL_POINT && chip->state != FL_READY) {
940 map_write(map, CMD(0xf0), adr);
941 chip->state = FL_READY;
942 }
943 (void) map_read(map, adr);
944 xip_iprefetch();
945 local_irq_enable();
946 }
947
948 /*
949 * When a delay is required for the flash operation to complete, the
950 * xip_udelay() function is polling for both the given timeout and pending
951 * (but still masked) hardware interrupts. Whenever there is an interrupt
952 * pending then the flash erase operation is suspended, array mode restored
953 * and interrupts unmasked. Task scheduling might also happen at that
954 * point. The CPU eventually returns from the interrupt or the call to
955 * schedule() and the suspended flash operation is resumed for the remaining
956 * of the delay period.
957 *
958 * Warning: this function _will_ fool interrupt latency tracing tools.
959 */
960
xip_udelay(struct map_info * map,struct flchip * chip,unsigned long adr,int usec)961 static void __xipram xip_udelay(struct map_info *map, struct flchip *chip,
962 unsigned long adr, int usec)
963 {
964 struct cfi_private *cfi = map->fldrv_priv;
965 struct cfi_pri_amdstd *extp = cfi->cmdset_priv;
966 map_word status, OK = CMD(0x80);
967 unsigned long suspended, start = xip_currtime();
968 flstate_t oldstate;
969
970 do {
971 cpu_relax();
972 if (xip_irqpending() && extp &&
973 ((chip->state == FL_ERASING && (extp->EraseSuspend & 2))) &&
974 (cfi_interleave_is_1(cfi) || chip->oldstate == FL_READY)) {
975 /*
976 * Let's suspend the erase operation when supported.
977 * Note that we currently don't try to suspend
978 * interleaved chips if there is already another
979 * operation suspended (imagine what happens
980 * when one chip was already done with the current
981 * operation while another chip suspended it, then
982 * we resume the whole thing at once). Yes, it
983 * can happen!
984 */
985 map_write(map, CMD(0xb0), adr);
986 usec -= xip_elapsed_since(start);
987 suspended = xip_currtime();
988 do {
989 if (xip_elapsed_since(suspended) > 100000) {
990 /*
991 * The chip doesn't want to suspend
992 * after waiting for 100 msecs.
993 * This is a critical error but there
994 * is not much we can do here.
995 */
996 return;
997 }
998 status = map_read(map, adr);
999 } while (!map_word_andequal(map, status, OK, OK));
1000
1001 /* Suspend succeeded */
1002 oldstate = chip->state;
1003 if (!map_word_bitsset(map, status, CMD(0x40)))
1004 break;
1005 chip->state = FL_XIP_WHILE_ERASING;
1006 chip->erase_suspended = 1;
1007 map_write(map, CMD(0xf0), adr);
1008 (void) map_read(map, adr);
1009 xip_iprefetch();
1010 local_irq_enable();
1011 mutex_unlock(&chip->mutex);
1012 xip_iprefetch();
1013 cond_resched();
1014
1015 /*
1016 * We're back. However someone else might have
1017 * decided to go write to the chip if we are in
1018 * a suspended erase state. If so let's wait
1019 * until it's done.
1020 */
1021 mutex_lock(&chip->mutex);
1022 while (chip->state != FL_XIP_WHILE_ERASING) {
1023 DECLARE_WAITQUEUE(wait, current);
1024 set_current_state(TASK_UNINTERRUPTIBLE);
1025 add_wait_queue(&chip->wq, &wait);
1026 mutex_unlock(&chip->mutex);
1027 schedule();
1028 remove_wait_queue(&chip->wq, &wait);
1029 mutex_lock(&chip->mutex);
1030 }
1031 /* Disallow XIP again */
1032 local_irq_disable();
1033
1034 /* Correct Erase Suspend Hangups for M29EW */
1035 cfi_fixup_m29ew_erase_suspend(map, adr);
1036 /* Resume the write or erase operation */
1037 map_write(map, cfi->sector_erase_cmd, adr);
1038 chip->state = oldstate;
1039 start = xip_currtime();
1040 } else if (usec >= 1000000/HZ) {
1041 /*
1042 * Try to save on CPU power when waiting delay
1043 * is at least a system timer tick period.
1044 * No need to be extremely accurate here.
1045 */
1046 xip_cpu_idle();
1047 }
1048 status = map_read(map, adr);
1049 } while (!map_word_andequal(map, status, OK, OK)
1050 && xip_elapsed_since(start) < usec);
1051 }
1052
1053 #define UDELAY(map, chip, adr, usec) xip_udelay(map, chip, adr, usec)
1054
1055 /*
1056 * The INVALIDATE_CACHED_RANGE() macro is normally used in parallel while
1057 * the flash is actively programming or erasing since we have to poll for
1058 * the operation to complete anyway. We can't do that in a generic way with
1059 * a XIP setup so do it before the actual flash operation in this case
1060 * and stub it out from INVALIDATE_CACHE_UDELAY.
1061 */
1062 #define XIP_INVAL_CACHED_RANGE(map, from, size) \
1063 INVALIDATE_CACHED_RANGE(map, from, size)
1064
1065 #define INVALIDATE_CACHE_UDELAY(map, chip, adr, len, usec) \
1066 UDELAY(map, chip, adr, usec)
1067
1068 /*
1069 * Extra notes:
1070 *
1071 * Activating this XIP support changes the way the code works a bit. For
1072 * example the code to suspend the current process when concurrent access
1073 * happens is never executed because xip_udelay() will always return with the
1074 * same chip state as it was entered with. This is why there is no care for
1075 * the presence of add_wait_queue() or schedule() calls from within a couple
1076 * xip_disable()'d areas of code, like in do_erase_oneblock for example.
1077 * The queueing and scheduling are always happening within xip_udelay().
1078 *
1079 * Similarly, get_chip() and put_chip() just happen to always be executed
1080 * with chip->state set to FL_READY (or FL_XIP_WHILE_*) where flash state
1081 * is in array mode, therefore never executing many cases therein and not
1082 * causing any problem with XIP.
1083 */
1084
1085 #else
1086
1087 #define xip_disable(map, chip, adr)
1088 #define xip_enable(map, chip, adr)
1089 #define XIP_INVAL_CACHED_RANGE(x...)
1090
1091 #define UDELAY(map, chip, adr, usec) \
1092 do { \
1093 mutex_unlock(&chip->mutex); \
1094 cfi_udelay(usec); \
1095 mutex_lock(&chip->mutex); \
1096 } while (0)
1097
1098 #define INVALIDATE_CACHE_UDELAY(map, chip, adr, len, usec) \
1099 do { \
1100 mutex_unlock(&chip->mutex); \
1101 INVALIDATE_CACHED_RANGE(map, adr, len); \
1102 cfi_udelay(usec); \
1103 mutex_lock(&chip->mutex); \
1104 } while (0)
1105
1106 #endif
1107
do_read_onechip(struct map_info * map,struct flchip * chip,loff_t adr,size_t len,u_char * buf)1108 static inline int do_read_onechip(struct map_info *map, struct flchip *chip, loff_t adr, size_t len, u_char *buf)
1109 {
1110 unsigned long cmd_addr;
1111 struct cfi_private *cfi = map->fldrv_priv;
1112 int ret;
1113
1114 adr += chip->start;
1115
1116 /* Ensure cmd read/writes are aligned. */
1117 cmd_addr = adr & ~(map_bankwidth(map)-1);
1118
1119 mutex_lock(&chip->mutex);
1120 ret = get_chip(map, chip, cmd_addr, FL_READY);
1121 if (ret) {
1122 mutex_unlock(&chip->mutex);
1123 return ret;
1124 }
1125
1126 if (chip->state != FL_POINT && chip->state != FL_READY) {
1127 map_write(map, CMD(0xf0), cmd_addr);
1128 chip->state = FL_READY;
1129 }
1130
1131 map_copy_from(map, buf, adr, len);
1132
1133 put_chip(map, chip, cmd_addr);
1134
1135 mutex_unlock(&chip->mutex);
1136 return 0;
1137 }
1138
1139
cfi_amdstd_read(struct mtd_info * mtd,loff_t from,size_t len,size_t * retlen,u_char * buf)1140 static int cfi_amdstd_read (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf)
1141 {
1142 struct map_info *map = mtd->priv;
1143 struct cfi_private *cfi = map->fldrv_priv;
1144 unsigned long ofs;
1145 int chipnum;
1146 int ret = 0;
1147
1148 /* ofs: offset within the first chip that the first read should start */
1149 chipnum = (from >> cfi->chipshift);
1150 ofs = from - (chipnum << cfi->chipshift);
1151
1152 while (len) {
1153 unsigned long thislen;
1154
1155 if (chipnum >= cfi->numchips)
1156 break;
1157
1158 if ((len + ofs -1) >> cfi->chipshift)
1159 thislen = (1<<cfi->chipshift) - ofs;
1160 else
1161 thislen = len;
1162
1163 ret = do_read_onechip(map, &cfi->chips[chipnum], ofs, thislen, buf);
1164 if (ret)
1165 break;
1166
1167 *retlen += thislen;
1168 len -= thislen;
1169 buf += thislen;
1170
1171 ofs = 0;
1172 chipnum++;
1173 }
1174 return ret;
1175 }
1176
1177 typedef int (*otp_op_t)(struct map_info *map, struct flchip *chip,
1178 loff_t adr, size_t len, u_char *buf, size_t grouplen);
1179
otp_enter(struct map_info * map,struct flchip * chip,loff_t adr,size_t len)1180 static inline void otp_enter(struct map_info *map, struct flchip *chip,
1181 loff_t adr, size_t len)
1182 {
1183 struct cfi_private *cfi = map->fldrv_priv;
1184
1185 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
1186 cfi->device_type, NULL);
1187 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
1188 cfi->device_type, NULL);
1189 cfi_send_gen_cmd(0x88, cfi->addr_unlock1, chip->start, map, cfi,
1190 cfi->device_type, NULL);
1191
1192 INVALIDATE_CACHED_RANGE(map, chip->start + adr, len);
1193 }
1194
otp_exit(struct map_info * map,struct flchip * chip,loff_t adr,size_t len)1195 static inline void otp_exit(struct map_info *map, struct flchip *chip,
1196 loff_t adr, size_t len)
1197 {
1198 struct cfi_private *cfi = map->fldrv_priv;
1199
1200 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
1201 cfi->device_type, NULL);
1202 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
1203 cfi->device_type, NULL);
1204 cfi_send_gen_cmd(0x90, cfi->addr_unlock1, chip->start, map, cfi,
1205 cfi->device_type, NULL);
1206 cfi_send_gen_cmd(0x00, cfi->addr_unlock1, chip->start, map, cfi,
1207 cfi->device_type, NULL);
1208
1209 INVALIDATE_CACHED_RANGE(map, chip->start + adr, len);
1210 }
1211
do_read_secsi_onechip(struct map_info * map,struct flchip * chip,loff_t adr,size_t len,u_char * buf,size_t grouplen)1212 static inline int do_read_secsi_onechip(struct map_info *map,
1213 struct flchip *chip, loff_t adr,
1214 size_t len, u_char *buf,
1215 size_t grouplen)
1216 {
1217 DECLARE_WAITQUEUE(wait, current);
1218 unsigned long timeo = jiffies + HZ;
1219
1220 retry:
1221 mutex_lock(&chip->mutex);
1222
1223 if (chip->state != FL_READY){
1224 set_current_state(TASK_UNINTERRUPTIBLE);
1225 add_wait_queue(&chip->wq, &wait);
1226
1227 mutex_unlock(&chip->mutex);
1228
1229 schedule();
1230 remove_wait_queue(&chip->wq, &wait);
1231 timeo = jiffies + HZ;
1232
1233 goto retry;
1234 }
1235
1236 adr += chip->start;
1237
1238 chip->state = FL_READY;
1239
1240 otp_enter(map, chip, adr, len);
1241 map_copy_from(map, buf, adr, len);
1242 otp_exit(map, chip, adr, len);
1243
1244 wake_up(&chip->wq);
1245 mutex_unlock(&chip->mutex);
1246
1247 return 0;
1248 }
1249
cfi_amdstd_secsi_read(struct mtd_info * mtd,loff_t from,size_t len,size_t * retlen,u_char * buf)1250 static int cfi_amdstd_secsi_read (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf)
1251 {
1252 struct map_info *map = mtd->priv;
1253 struct cfi_private *cfi = map->fldrv_priv;
1254 unsigned long ofs;
1255 int chipnum;
1256 int ret = 0;
1257
1258 /* ofs: offset within the first chip that the first read should start */
1259 /* 8 secsi bytes per chip */
1260 chipnum=from>>3;
1261 ofs=from & 7;
1262
1263 while (len) {
1264 unsigned long thislen;
1265
1266 if (chipnum >= cfi->numchips)
1267 break;
1268
1269 if ((len + ofs -1) >> 3)
1270 thislen = (1<<3) - ofs;
1271 else
1272 thislen = len;
1273
1274 ret = do_read_secsi_onechip(map, &cfi->chips[chipnum], ofs,
1275 thislen, buf, 0);
1276 if (ret)
1277 break;
1278
1279 *retlen += thislen;
1280 len -= thislen;
1281 buf += thislen;
1282
1283 ofs = 0;
1284 chipnum++;
1285 }
1286 return ret;
1287 }
1288
1289 static int __xipram do_write_oneword(struct map_info *map, struct flchip *chip,
1290 unsigned long adr, map_word datum,
1291 int mode);
1292
do_otp_write(struct map_info * map,struct flchip * chip,loff_t adr,size_t len,u_char * buf,size_t grouplen)1293 static int do_otp_write(struct map_info *map, struct flchip *chip, loff_t adr,
1294 size_t len, u_char *buf, size_t grouplen)
1295 {
1296 int ret;
1297 while (len) {
1298 unsigned long bus_ofs = adr & ~(map_bankwidth(map)-1);
1299 int gap = adr - bus_ofs;
1300 int n = min_t(int, len, map_bankwidth(map) - gap);
1301 map_word datum = map_word_ff(map);
1302
1303 if (n != map_bankwidth(map)) {
1304 /* partial write of a word, load old contents */
1305 otp_enter(map, chip, bus_ofs, map_bankwidth(map));
1306 datum = map_read(map, bus_ofs);
1307 otp_exit(map, chip, bus_ofs, map_bankwidth(map));
1308 }
1309
1310 datum = map_word_load_partial(map, datum, buf, gap, n);
1311 ret = do_write_oneword(map, chip, bus_ofs, datum, FL_OTP_WRITE);
1312 if (ret)
1313 return ret;
1314
1315 adr += n;
1316 buf += n;
1317 len -= n;
1318 }
1319
1320 return 0;
1321 }
1322
do_otp_lock(struct map_info * map,struct flchip * chip,loff_t adr,size_t len,u_char * buf,size_t grouplen)1323 static int do_otp_lock(struct map_info *map, struct flchip *chip, loff_t adr,
1324 size_t len, u_char *buf, size_t grouplen)
1325 {
1326 struct cfi_private *cfi = map->fldrv_priv;
1327 uint8_t lockreg;
1328 unsigned long timeo;
1329 int ret;
1330
1331 /* make sure area matches group boundaries */
1332 if ((adr != 0) || (len != grouplen))
1333 return -EINVAL;
1334
1335 mutex_lock(&chip->mutex);
1336 ret = get_chip(map, chip, chip->start, FL_LOCKING);
1337 if (ret) {
1338 mutex_unlock(&chip->mutex);
1339 return ret;
1340 }
1341 chip->state = FL_LOCKING;
1342
1343 /* Enter lock register command */
1344 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
1345 cfi->device_type, NULL);
1346 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
1347 cfi->device_type, NULL);
1348 cfi_send_gen_cmd(0x40, cfi->addr_unlock1, chip->start, map, cfi,
1349 cfi->device_type, NULL);
1350
1351 /* read lock register */
1352 lockreg = cfi_read_query(map, 0);
1353
1354 /* set bit 0 to protect extended memory block */
1355 lockreg &= ~0x01;
1356
1357 /* set bit 0 to protect extended memory block */
1358 /* write lock register */
1359 map_write(map, CMD(0xA0), chip->start);
1360 map_write(map, CMD(lockreg), chip->start);
1361
1362 /* wait for chip to become ready */
1363 timeo = jiffies + msecs_to_jiffies(2);
1364 for (;;) {
1365 if (chip_ready(map, adr))
1366 break;
1367
1368 if (time_after(jiffies, timeo)) {
1369 pr_err("Waiting for chip to be ready timed out.\n");
1370 ret = -EIO;
1371 break;
1372 }
1373 UDELAY(map, chip, 0, 1);
1374 }
1375
1376 /* exit protection commands */
1377 map_write(map, CMD(0x90), chip->start);
1378 map_write(map, CMD(0x00), chip->start);
1379
1380 chip->state = FL_READY;
1381 put_chip(map, chip, chip->start);
1382 mutex_unlock(&chip->mutex);
1383
1384 return ret;
1385 }
1386
cfi_amdstd_otp_walk(struct mtd_info * mtd,loff_t from,size_t len,size_t * retlen,u_char * buf,otp_op_t action,int user_regs)1387 static int cfi_amdstd_otp_walk(struct mtd_info *mtd, loff_t from, size_t len,
1388 size_t *retlen, u_char *buf,
1389 otp_op_t action, int user_regs)
1390 {
1391 struct map_info *map = mtd->priv;
1392 struct cfi_private *cfi = map->fldrv_priv;
1393 int ofs_factor = cfi->interleave * cfi->device_type;
1394 unsigned long base;
1395 int chipnum;
1396 struct flchip *chip;
1397 uint8_t otp, lockreg;
1398 int ret;
1399
1400 size_t user_size, factory_size, otpsize;
1401 loff_t user_offset, factory_offset, otpoffset;
1402 int user_locked = 0, otplocked;
1403
1404 *retlen = 0;
1405
1406 for (chipnum = 0; chipnum < cfi->numchips; chipnum++) {
1407 chip = &cfi->chips[chipnum];
1408 factory_size = 0;
1409 user_size = 0;
1410
1411 /* Micron M29EW family */
1412 if (is_m29ew(cfi)) {
1413 base = chip->start;
1414
1415 /* check whether secsi area is factory locked
1416 or user lockable */
1417 mutex_lock(&chip->mutex);
1418 ret = get_chip(map, chip, base, FL_CFI_QUERY);
1419 if (ret) {
1420 mutex_unlock(&chip->mutex);
1421 return ret;
1422 }
1423 cfi_qry_mode_on(base, map, cfi);
1424 otp = cfi_read_query(map, base + 0x3 * ofs_factor);
1425 cfi_qry_mode_off(base, map, cfi);
1426 put_chip(map, chip, base);
1427 mutex_unlock(&chip->mutex);
1428
1429 if (otp & 0x80) {
1430 /* factory locked */
1431 factory_offset = 0;
1432 factory_size = 0x100;
1433 } else {
1434 /* customer lockable */
1435 user_offset = 0;
1436 user_size = 0x100;
1437
1438 mutex_lock(&chip->mutex);
1439 ret = get_chip(map, chip, base, FL_LOCKING);
1440 if (ret) {
1441 mutex_unlock(&chip->mutex);
1442 return ret;
1443 }
1444
1445 /* Enter lock register command */
1446 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1,
1447 chip->start, map, cfi,
1448 cfi->device_type, NULL);
1449 cfi_send_gen_cmd(0x55, cfi->addr_unlock2,
1450 chip->start, map, cfi,
1451 cfi->device_type, NULL);
1452 cfi_send_gen_cmd(0x40, cfi->addr_unlock1,
1453 chip->start, map, cfi,
1454 cfi->device_type, NULL);
1455 /* read lock register */
1456 lockreg = cfi_read_query(map, 0);
1457 /* exit protection commands */
1458 map_write(map, CMD(0x90), chip->start);
1459 map_write(map, CMD(0x00), chip->start);
1460 put_chip(map, chip, chip->start);
1461 mutex_unlock(&chip->mutex);
1462
1463 user_locked = ((lockreg & 0x01) == 0x00);
1464 }
1465 }
1466
1467 otpsize = user_regs ? user_size : factory_size;
1468 if (!otpsize)
1469 continue;
1470 otpoffset = user_regs ? user_offset : factory_offset;
1471 otplocked = user_regs ? user_locked : 1;
1472
1473 if (!action) {
1474 /* return otpinfo */
1475 struct otp_info *otpinfo;
1476 len -= sizeof(*otpinfo);
1477 if (len <= 0)
1478 return -ENOSPC;
1479 otpinfo = (struct otp_info *)buf;
1480 otpinfo->start = from;
1481 otpinfo->length = otpsize;
1482 otpinfo->locked = otplocked;
1483 buf += sizeof(*otpinfo);
1484 *retlen += sizeof(*otpinfo);
1485 from += otpsize;
1486 } else if ((from < otpsize) && (len > 0)) {
1487 size_t size;
1488 size = (len < otpsize - from) ? len : otpsize - from;
1489 ret = action(map, chip, otpoffset + from, size, buf,
1490 otpsize);
1491 if (ret < 0)
1492 return ret;
1493
1494 buf += size;
1495 len -= size;
1496 *retlen += size;
1497 from = 0;
1498 } else {
1499 from -= otpsize;
1500 }
1501 }
1502 return 0;
1503 }
1504
cfi_amdstd_get_fact_prot_info(struct mtd_info * mtd,size_t len,size_t * retlen,struct otp_info * buf)1505 static int cfi_amdstd_get_fact_prot_info(struct mtd_info *mtd, size_t len,
1506 size_t *retlen, struct otp_info *buf)
1507 {
1508 return cfi_amdstd_otp_walk(mtd, 0, len, retlen, (u_char *)buf,
1509 NULL, 0);
1510 }
1511
cfi_amdstd_get_user_prot_info(struct mtd_info * mtd,size_t len,size_t * retlen,struct otp_info * buf)1512 static int cfi_amdstd_get_user_prot_info(struct mtd_info *mtd, size_t len,
1513 size_t *retlen, struct otp_info *buf)
1514 {
1515 return cfi_amdstd_otp_walk(mtd, 0, len, retlen, (u_char *)buf,
1516 NULL, 1);
1517 }
1518
cfi_amdstd_read_fact_prot_reg(struct mtd_info * mtd,loff_t from,size_t len,size_t * retlen,u_char * buf)1519 static int cfi_amdstd_read_fact_prot_reg(struct mtd_info *mtd, loff_t from,
1520 size_t len, size_t *retlen,
1521 u_char *buf)
1522 {
1523 return cfi_amdstd_otp_walk(mtd, from, len, retlen,
1524 buf, do_read_secsi_onechip, 0);
1525 }
1526
cfi_amdstd_read_user_prot_reg(struct mtd_info * mtd,loff_t from,size_t len,size_t * retlen,u_char * buf)1527 static int cfi_amdstd_read_user_prot_reg(struct mtd_info *mtd, loff_t from,
1528 size_t len, size_t *retlen,
1529 u_char *buf)
1530 {
1531 return cfi_amdstd_otp_walk(mtd, from, len, retlen,
1532 buf, do_read_secsi_onechip, 1);
1533 }
1534
cfi_amdstd_write_user_prot_reg(struct mtd_info * mtd,loff_t from,size_t len,size_t * retlen,u_char * buf)1535 static int cfi_amdstd_write_user_prot_reg(struct mtd_info *mtd, loff_t from,
1536 size_t len, size_t *retlen,
1537 u_char *buf)
1538 {
1539 return cfi_amdstd_otp_walk(mtd, from, len, retlen, buf,
1540 do_otp_write, 1);
1541 }
1542
cfi_amdstd_lock_user_prot_reg(struct mtd_info * mtd,loff_t from,size_t len)1543 static int cfi_amdstd_lock_user_prot_reg(struct mtd_info *mtd, loff_t from,
1544 size_t len)
1545 {
1546 size_t retlen;
1547 return cfi_amdstd_otp_walk(mtd, from, len, &retlen, NULL,
1548 do_otp_lock, 1);
1549 }
1550
do_write_oneword(struct map_info * map,struct flchip * chip,unsigned long adr,map_word datum,int mode)1551 static int __xipram do_write_oneword(struct map_info *map, struct flchip *chip,
1552 unsigned long adr, map_word datum,
1553 int mode)
1554 {
1555 struct cfi_private *cfi = map->fldrv_priv;
1556 unsigned long timeo = jiffies + HZ;
1557 /*
1558 * We use a 1ms + 1 jiffies generic timeout for writes (most devices
1559 * have a max write time of a few hundreds usec). However, we should
1560 * use the maximum timeout value given by the chip at probe time
1561 * instead. Unfortunately, struct flchip does have a field for
1562 * maximum timeout, only for typical which can be far too short
1563 * depending of the conditions. The ' + 1' is to avoid having a
1564 * timeout of 0 jiffies if HZ is smaller than 1000.
1565 */
1566 unsigned long uWriteTimeout = ( HZ / 1000 ) + 1;
1567 int ret = 0;
1568 map_word oldd;
1569 int retry_cnt = 0;
1570
1571 adr += chip->start;
1572
1573 mutex_lock(&chip->mutex);
1574 ret = get_chip(map, chip, adr, mode);
1575 if (ret) {
1576 mutex_unlock(&chip->mutex);
1577 return ret;
1578 }
1579
1580 pr_debug("MTD %s(): WRITE 0x%.8lx(0x%.8lx)\n",
1581 __func__, adr, datum.x[0] );
1582
1583 if (mode == FL_OTP_WRITE)
1584 otp_enter(map, chip, adr, map_bankwidth(map));
1585
1586 /*
1587 * Check for a NOP for the case when the datum to write is already
1588 * present - it saves time and works around buggy chips that corrupt
1589 * data at other locations when 0xff is written to a location that
1590 * already contains 0xff.
1591 */
1592 oldd = map_read(map, adr);
1593 if (map_word_equal(map, oldd, datum)) {
1594 pr_debug("MTD %s(): NOP\n",
1595 __func__);
1596 goto op_done;
1597 }
1598
1599 XIP_INVAL_CACHED_RANGE(map, adr, map_bankwidth(map));
1600 ENABLE_VPP(map);
1601 xip_disable(map, chip, adr);
1602
1603 retry:
1604 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1605 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1606 cfi_send_gen_cmd(0xA0, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1607 map_write(map, datum, adr);
1608 chip->state = mode;
1609
1610 INVALIDATE_CACHE_UDELAY(map, chip,
1611 adr, map_bankwidth(map),
1612 chip->word_write_time);
1613
1614 /* See comment above for timeout value. */
1615 timeo = jiffies + uWriteTimeout;
1616 for (;;) {
1617 if (chip->state != mode) {
1618 /* Someone's suspended the write. Sleep */
1619 DECLARE_WAITQUEUE(wait, current);
1620
1621 set_current_state(TASK_UNINTERRUPTIBLE);
1622 add_wait_queue(&chip->wq, &wait);
1623 mutex_unlock(&chip->mutex);
1624 schedule();
1625 remove_wait_queue(&chip->wq, &wait);
1626 timeo = jiffies + (HZ / 2); /* FIXME */
1627 mutex_lock(&chip->mutex);
1628 continue;
1629 }
1630
1631 /*
1632 * We check "time_after" and "!chip_good" before checking
1633 * "chip_good" to avoid the failure due to scheduling.
1634 */
1635 if (time_after(jiffies, timeo) && !chip_good(map, adr, datum)) {
1636 xip_enable(map, chip, adr);
1637 printk(KERN_WARNING "MTD %s(): software timeout\n", __func__);
1638 xip_disable(map, chip, adr);
1639 ret = -EIO;
1640 break;
1641 }
1642
1643 if (chip_good(map, adr, datum))
1644 break;
1645
1646 /* Latency issues. Drop the lock, wait a while and retry */
1647 UDELAY(map, chip, adr, 1);
1648 }
1649
1650 /* Did we succeed? */
1651 if (ret) {
1652 /* reset on all failures. */
1653 map_write( map, CMD(0xF0), chip->start );
1654 /* FIXME - should have reset delay before continuing */
1655
1656 if (++retry_cnt <= MAX_RETRIES) {
1657 ret = 0;
1658 goto retry;
1659 }
1660 }
1661 xip_enable(map, chip, adr);
1662 op_done:
1663 if (mode == FL_OTP_WRITE)
1664 otp_exit(map, chip, adr, map_bankwidth(map));
1665 chip->state = FL_READY;
1666 DISABLE_VPP(map);
1667 put_chip(map, chip, adr);
1668 mutex_unlock(&chip->mutex);
1669
1670 return ret;
1671 }
1672
1673
cfi_amdstd_write_words(struct mtd_info * mtd,loff_t to,size_t len,size_t * retlen,const u_char * buf)1674 static int cfi_amdstd_write_words(struct mtd_info *mtd, loff_t to, size_t len,
1675 size_t *retlen, const u_char *buf)
1676 {
1677 struct map_info *map = mtd->priv;
1678 struct cfi_private *cfi = map->fldrv_priv;
1679 int ret = 0;
1680 int chipnum;
1681 unsigned long ofs, chipstart;
1682 DECLARE_WAITQUEUE(wait, current);
1683
1684 chipnum = to >> cfi->chipshift;
1685 ofs = to - (chipnum << cfi->chipshift);
1686 chipstart = cfi->chips[chipnum].start;
1687
1688 /* If it's not bus-aligned, do the first byte write */
1689 if (ofs & (map_bankwidth(map)-1)) {
1690 unsigned long bus_ofs = ofs & ~(map_bankwidth(map)-1);
1691 int i = ofs - bus_ofs;
1692 int n = 0;
1693 map_word tmp_buf;
1694
1695 retry:
1696 mutex_lock(&cfi->chips[chipnum].mutex);
1697
1698 if (cfi->chips[chipnum].state != FL_READY) {
1699 set_current_state(TASK_UNINTERRUPTIBLE);
1700 add_wait_queue(&cfi->chips[chipnum].wq, &wait);
1701
1702 mutex_unlock(&cfi->chips[chipnum].mutex);
1703
1704 schedule();
1705 remove_wait_queue(&cfi->chips[chipnum].wq, &wait);
1706 goto retry;
1707 }
1708
1709 /* Load 'tmp_buf' with old contents of flash */
1710 tmp_buf = map_read(map, bus_ofs+chipstart);
1711
1712 mutex_unlock(&cfi->chips[chipnum].mutex);
1713
1714 /* Number of bytes to copy from buffer */
1715 n = min_t(int, len, map_bankwidth(map)-i);
1716
1717 tmp_buf = map_word_load_partial(map, tmp_buf, buf, i, n);
1718
1719 ret = do_write_oneword(map, &cfi->chips[chipnum],
1720 bus_ofs, tmp_buf, FL_WRITING);
1721 if (ret)
1722 return ret;
1723
1724 ofs += n;
1725 buf += n;
1726 (*retlen) += n;
1727 len -= n;
1728
1729 if (ofs >> cfi->chipshift) {
1730 chipnum ++;
1731 ofs = 0;
1732 if (chipnum == cfi->numchips)
1733 return 0;
1734 }
1735 }
1736
1737 /* We are now aligned, write as much as possible */
1738 while(len >= map_bankwidth(map)) {
1739 map_word datum;
1740
1741 datum = map_word_load(map, buf);
1742
1743 ret = do_write_oneword(map, &cfi->chips[chipnum],
1744 ofs, datum, FL_WRITING);
1745 if (ret)
1746 return ret;
1747
1748 ofs += map_bankwidth(map);
1749 buf += map_bankwidth(map);
1750 (*retlen) += map_bankwidth(map);
1751 len -= map_bankwidth(map);
1752
1753 if (ofs >> cfi->chipshift) {
1754 chipnum ++;
1755 ofs = 0;
1756 if (chipnum == cfi->numchips)
1757 return 0;
1758 chipstart = cfi->chips[chipnum].start;
1759 }
1760 }
1761
1762 /* Write the trailing bytes if any */
1763 if (len & (map_bankwidth(map)-1)) {
1764 map_word tmp_buf;
1765
1766 retry1:
1767 mutex_lock(&cfi->chips[chipnum].mutex);
1768
1769 if (cfi->chips[chipnum].state != FL_READY) {
1770 set_current_state(TASK_UNINTERRUPTIBLE);
1771 add_wait_queue(&cfi->chips[chipnum].wq, &wait);
1772
1773 mutex_unlock(&cfi->chips[chipnum].mutex);
1774
1775 schedule();
1776 remove_wait_queue(&cfi->chips[chipnum].wq, &wait);
1777 goto retry1;
1778 }
1779
1780 tmp_buf = map_read(map, ofs + chipstart);
1781
1782 mutex_unlock(&cfi->chips[chipnum].mutex);
1783
1784 tmp_buf = map_word_load_partial(map, tmp_buf, buf, 0, len);
1785
1786 ret = do_write_oneword(map, &cfi->chips[chipnum],
1787 ofs, tmp_buf, FL_WRITING);
1788 if (ret)
1789 return ret;
1790
1791 (*retlen) += len;
1792 }
1793
1794 return 0;
1795 }
1796
1797
1798 /*
1799 * FIXME: interleaved mode not tested, and probably not supported!
1800 */
do_write_buffer(struct map_info * map,struct flchip * chip,unsigned long adr,const u_char * buf,int len)1801 static int __xipram do_write_buffer(struct map_info *map, struct flchip *chip,
1802 unsigned long adr, const u_char *buf,
1803 int len)
1804 {
1805 struct cfi_private *cfi = map->fldrv_priv;
1806 unsigned long timeo = jiffies + HZ;
1807 /*
1808 * Timeout is calculated according to CFI data, if available.
1809 * See more comments in cfi_cmdset_0002().
1810 */
1811 unsigned long uWriteTimeout =
1812 usecs_to_jiffies(chip->buffer_write_time_max);
1813 int ret = -EIO;
1814 unsigned long cmd_adr;
1815 int z, words;
1816 map_word datum;
1817
1818 adr += chip->start;
1819 cmd_adr = adr;
1820
1821 mutex_lock(&chip->mutex);
1822 ret = get_chip(map, chip, adr, FL_WRITING);
1823 if (ret) {
1824 mutex_unlock(&chip->mutex);
1825 return ret;
1826 }
1827
1828 datum = map_word_load(map, buf);
1829
1830 pr_debug("MTD %s(): WRITE 0x%.8lx(0x%.8lx)\n",
1831 __func__, adr, datum.x[0] );
1832
1833 XIP_INVAL_CACHED_RANGE(map, adr, len);
1834 ENABLE_VPP(map);
1835 xip_disable(map, chip, cmd_adr);
1836
1837 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1838 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1839
1840 /* Write Buffer Load */
1841 map_write(map, CMD(0x25), cmd_adr);
1842
1843 chip->state = FL_WRITING_TO_BUFFER;
1844
1845 /* Write length of data to come */
1846 words = len / map_bankwidth(map);
1847 map_write(map, CMD(words - 1), cmd_adr);
1848 /* Write data */
1849 z = 0;
1850 while(z < words * map_bankwidth(map)) {
1851 datum = map_word_load(map, buf);
1852 map_write(map, datum, adr + z);
1853
1854 z += map_bankwidth(map);
1855 buf += map_bankwidth(map);
1856 }
1857 z -= map_bankwidth(map);
1858
1859 adr += z;
1860
1861 /* Write Buffer Program Confirm: GO GO GO */
1862 map_write(map, CMD(0x29), cmd_adr);
1863 chip->state = FL_WRITING;
1864
1865 INVALIDATE_CACHE_UDELAY(map, chip,
1866 adr, map_bankwidth(map),
1867 chip->word_write_time);
1868
1869 timeo = jiffies + uWriteTimeout;
1870
1871 for (;;) {
1872 if (chip->state != FL_WRITING) {
1873 /* Someone's suspended the write. Sleep */
1874 DECLARE_WAITQUEUE(wait, current);
1875
1876 set_current_state(TASK_UNINTERRUPTIBLE);
1877 add_wait_queue(&chip->wq, &wait);
1878 mutex_unlock(&chip->mutex);
1879 schedule();
1880 remove_wait_queue(&chip->wq, &wait);
1881 timeo = jiffies + (HZ / 2); /* FIXME */
1882 mutex_lock(&chip->mutex);
1883 continue;
1884 }
1885
1886 if (time_after(jiffies, timeo) && !chip_ready(map, adr))
1887 break;
1888
1889 if (chip_good(map, adr, datum)) {
1890 xip_enable(map, chip, adr);
1891 goto op_done;
1892 }
1893
1894 /* Latency issues. Drop the lock, wait a while and retry */
1895 UDELAY(map, chip, adr, 1);
1896 }
1897
1898 /*
1899 * Recovery from write-buffer programming failures requires
1900 * the write-to-buffer-reset sequence. Since the last part
1901 * of the sequence also works as a normal reset, we can run
1902 * the same commands regardless of why we are here.
1903 * See e.g.
1904 * http://www.spansion.com/Support/Application%20Notes/MirrorBit_Write_Buffer_Prog_Page_Buffer_Read_AN.pdf
1905 */
1906 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
1907 cfi->device_type, NULL);
1908 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
1909 cfi->device_type, NULL);
1910 cfi_send_gen_cmd(0xF0, cfi->addr_unlock1, chip->start, map, cfi,
1911 cfi->device_type, NULL);
1912 xip_enable(map, chip, adr);
1913 /* FIXME - should have reset delay before continuing */
1914
1915 printk(KERN_WARNING "MTD %s(): software timeout, address:0x%.8lx.\n",
1916 __func__, adr);
1917
1918 ret = -EIO;
1919 op_done:
1920 chip->state = FL_READY;
1921 DISABLE_VPP(map);
1922 put_chip(map, chip, adr);
1923 mutex_unlock(&chip->mutex);
1924
1925 return ret;
1926 }
1927
1928
cfi_amdstd_write_buffers(struct mtd_info * mtd,loff_t to,size_t len,size_t * retlen,const u_char * buf)1929 static int cfi_amdstd_write_buffers(struct mtd_info *mtd, loff_t to, size_t len,
1930 size_t *retlen, const u_char *buf)
1931 {
1932 struct map_info *map = mtd->priv;
1933 struct cfi_private *cfi = map->fldrv_priv;
1934 int wbufsize = cfi_interleave(cfi) << cfi->cfiq->MaxBufWriteSize;
1935 int ret = 0;
1936 int chipnum;
1937 unsigned long ofs;
1938
1939 chipnum = to >> cfi->chipshift;
1940 ofs = to - (chipnum << cfi->chipshift);
1941
1942 /* If it's not bus-aligned, do the first word write */
1943 if (ofs & (map_bankwidth(map)-1)) {
1944 size_t local_len = (-ofs)&(map_bankwidth(map)-1);
1945 if (local_len > len)
1946 local_len = len;
1947 ret = cfi_amdstd_write_words(mtd, ofs + (chipnum<<cfi->chipshift),
1948 local_len, retlen, buf);
1949 if (ret)
1950 return ret;
1951 ofs += local_len;
1952 buf += local_len;
1953 len -= local_len;
1954
1955 if (ofs >> cfi->chipshift) {
1956 chipnum ++;
1957 ofs = 0;
1958 if (chipnum == cfi->numchips)
1959 return 0;
1960 }
1961 }
1962
1963 /* Write buffer is worth it only if more than one word to write... */
1964 while (len >= map_bankwidth(map) * 2) {
1965 /* We must not cross write block boundaries */
1966 int size = wbufsize - (ofs & (wbufsize-1));
1967
1968 if (size > len)
1969 size = len;
1970 if (size % map_bankwidth(map))
1971 size -= size % map_bankwidth(map);
1972
1973 ret = do_write_buffer(map, &cfi->chips[chipnum],
1974 ofs, buf, size);
1975 if (ret)
1976 return ret;
1977
1978 ofs += size;
1979 buf += size;
1980 (*retlen) += size;
1981 len -= size;
1982
1983 if (ofs >> cfi->chipshift) {
1984 chipnum ++;
1985 ofs = 0;
1986 if (chipnum == cfi->numchips)
1987 return 0;
1988 }
1989 }
1990
1991 if (len) {
1992 size_t retlen_dregs = 0;
1993
1994 ret = cfi_amdstd_write_words(mtd, ofs + (chipnum<<cfi->chipshift),
1995 len, &retlen_dregs, buf);
1996
1997 *retlen += retlen_dregs;
1998 return ret;
1999 }
2000
2001 return 0;
2002 }
2003
2004 /*
2005 * Wait for the flash chip to become ready to write data
2006 *
2007 * This is only called during the panic_write() path. When panic_write()
2008 * is called, the kernel is in the process of a panic, and will soon be
2009 * dead. Therefore we don't take any locks, and attempt to get access
2010 * to the chip as soon as possible.
2011 */
cfi_amdstd_panic_wait(struct map_info * map,struct flchip * chip,unsigned long adr)2012 static int cfi_amdstd_panic_wait(struct map_info *map, struct flchip *chip,
2013 unsigned long adr)
2014 {
2015 struct cfi_private *cfi = map->fldrv_priv;
2016 int retries = 10;
2017 int i;
2018
2019 /*
2020 * If the driver thinks the chip is idle, and no toggle bits
2021 * are changing, then the chip is actually idle for sure.
2022 */
2023 if (chip->state == FL_READY && chip_ready(map, adr))
2024 return 0;
2025
2026 /*
2027 * Try several times to reset the chip and then wait for it
2028 * to become idle. The upper limit of a few milliseconds of
2029 * delay isn't a big problem: the kernel is dying anyway. It
2030 * is more important to save the messages.
2031 */
2032 while (retries > 0) {
2033 const unsigned long timeo = (HZ / 1000) + 1;
2034
2035 /* send the reset command */
2036 map_write(map, CMD(0xF0), chip->start);
2037
2038 /* wait for the chip to become ready */
2039 for (i = 0; i < jiffies_to_usecs(timeo); i++) {
2040 if (chip_ready(map, adr))
2041 return 0;
2042
2043 udelay(1);
2044 }
2045
2046 retries--;
2047 }
2048
2049 /* the chip never became ready */
2050 return -EBUSY;
2051 }
2052
2053 /*
2054 * Write out one word of data to a single flash chip during a kernel panic
2055 *
2056 * This is only called during the panic_write() path. When panic_write()
2057 * is called, the kernel is in the process of a panic, and will soon be
2058 * dead. Therefore we don't take any locks, and attempt to get access
2059 * to the chip as soon as possible.
2060 *
2061 * The implementation of this routine is intentionally similar to
2062 * do_write_oneword(), in order to ease code maintenance.
2063 */
do_panic_write_oneword(struct map_info * map,struct flchip * chip,unsigned long adr,map_word datum)2064 static int do_panic_write_oneword(struct map_info *map, struct flchip *chip,
2065 unsigned long adr, map_word datum)
2066 {
2067 const unsigned long uWriteTimeout = (HZ / 1000) + 1;
2068 struct cfi_private *cfi = map->fldrv_priv;
2069 int retry_cnt = 0;
2070 map_word oldd;
2071 int ret = 0;
2072 int i;
2073
2074 adr += chip->start;
2075
2076 ret = cfi_amdstd_panic_wait(map, chip, adr);
2077 if (ret)
2078 return ret;
2079
2080 pr_debug("MTD %s(): PANIC WRITE 0x%.8lx(0x%.8lx)\n",
2081 __func__, adr, datum.x[0]);
2082
2083 /*
2084 * Check for a NOP for the case when the datum to write is already
2085 * present - it saves time and works around buggy chips that corrupt
2086 * data at other locations when 0xff is written to a location that
2087 * already contains 0xff.
2088 */
2089 oldd = map_read(map, adr);
2090 if (map_word_equal(map, oldd, datum)) {
2091 pr_debug("MTD %s(): NOP\n", __func__);
2092 goto op_done;
2093 }
2094
2095 ENABLE_VPP(map);
2096
2097 retry:
2098 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2099 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
2100 cfi_send_gen_cmd(0xA0, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2101 map_write(map, datum, adr);
2102
2103 for (i = 0; i < jiffies_to_usecs(uWriteTimeout); i++) {
2104 if (chip_ready(map, adr))
2105 break;
2106
2107 udelay(1);
2108 }
2109
2110 if (!chip_good(map, adr, datum)) {
2111 /* reset on all failures. */
2112 map_write(map, CMD(0xF0), chip->start);
2113 /* FIXME - should have reset delay before continuing */
2114
2115 if (++retry_cnt <= MAX_RETRIES)
2116 goto retry;
2117
2118 ret = -EIO;
2119 }
2120
2121 op_done:
2122 DISABLE_VPP(map);
2123 return ret;
2124 }
2125
2126 /*
2127 * Write out some data during a kernel panic
2128 *
2129 * This is used by the mtdoops driver to save the dying messages from a
2130 * kernel which has panic'd.
2131 *
2132 * This routine ignores all of the locking used throughout the rest of the
2133 * driver, in order to ensure that the data gets written out no matter what
2134 * state this driver (and the flash chip itself) was in when the kernel crashed.
2135 *
2136 * The implementation of this routine is intentionally similar to
2137 * cfi_amdstd_write_words(), in order to ease code maintenance.
2138 */
cfi_amdstd_panic_write(struct mtd_info * mtd,loff_t to,size_t len,size_t * retlen,const u_char * buf)2139 static int cfi_amdstd_panic_write(struct mtd_info *mtd, loff_t to, size_t len,
2140 size_t *retlen, const u_char *buf)
2141 {
2142 struct map_info *map = mtd->priv;
2143 struct cfi_private *cfi = map->fldrv_priv;
2144 unsigned long ofs, chipstart;
2145 int ret = 0;
2146 int chipnum;
2147
2148 chipnum = to >> cfi->chipshift;
2149 ofs = to - (chipnum << cfi->chipshift);
2150 chipstart = cfi->chips[chipnum].start;
2151
2152 /* If it's not bus aligned, do the first byte write */
2153 if (ofs & (map_bankwidth(map) - 1)) {
2154 unsigned long bus_ofs = ofs & ~(map_bankwidth(map) - 1);
2155 int i = ofs - bus_ofs;
2156 int n = 0;
2157 map_word tmp_buf;
2158
2159 ret = cfi_amdstd_panic_wait(map, &cfi->chips[chipnum], bus_ofs);
2160 if (ret)
2161 return ret;
2162
2163 /* Load 'tmp_buf' with old contents of flash */
2164 tmp_buf = map_read(map, bus_ofs + chipstart);
2165
2166 /* Number of bytes to copy from buffer */
2167 n = min_t(int, len, map_bankwidth(map) - i);
2168
2169 tmp_buf = map_word_load_partial(map, tmp_buf, buf, i, n);
2170
2171 ret = do_panic_write_oneword(map, &cfi->chips[chipnum],
2172 bus_ofs, tmp_buf);
2173 if (ret)
2174 return ret;
2175
2176 ofs += n;
2177 buf += n;
2178 (*retlen) += n;
2179 len -= n;
2180
2181 if (ofs >> cfi->chipshift) {
2182 chipnum++;
2183 ofs = 0;
2184 if (chipnum == cfi->numchips)
2185 return 0;
2186 }
2187 }
2188
2189 /* We are now aligned, write as much as possible */
2190 while (len >= map_bankwidth(map)) {
2191 map_word datum;
2192
2193 datum = map_word_load(map, buf);
2194
2195 ret = do_panic_write_oneword(map, &cfi->chips[chipnum],
2196 ofs, datum);
2197 if (ret)
2198 return ret;
2199
2200 ofs += map_bankwidth(map);
2201 buf += map_bankwidth(map);
2202 (*retlen) += map_bankwidth(map);
2203 len -= map_bankwidth(map);
2204
2205 if (ofs >> cfi->chipshift) {
2206 chipnum++;
2207 ofs = 0;
2208 if (chipnum == cfi->numchips)
2209 return 0;
2210
2211 chipstart = cfi->chips[chipnum].start;
2212 }
2213 }
2214
2215 /* Write the trailing bytes if any */
2216 if (len & (map_bankwidth(map) - 1)) {
2217 map_word tmp_buf;
2218
2219 ret = cfi_amdstd_panic_wait(map, &cfi->chips[chipnum], ofs);
2220 if (ret)
2221 return ret;
2222
2223 tmp_buf = map_read(map, ofs + chipstart);
2224
2225 tmp_buf = map_word_load_partial(map, tmp_buf, buf, 0, len);
2226
2227 ret = do_panic_write_oneword(map, &cfi->chips[chipnum],
2228 ofs, tmp_buf);
2229 if (ret)
2230 return ret;
2231
2232 (*retlen) += len;
2233 }
2234
2235 return 0;
2236 }
2237
2238
2239 /*
2240 * Handle devices with one erase region, that only implement
2241 * the chip erase command.
2242 */
do_erase_chip(struct map_info * map,struct flchip * chip)2243 static int __xipram do_erase_chip(struct map_info *map, struct flchip *chip)
2244 {
2245 struct cfi_private *cfi = map->fldrv_priv;
2246 unsigned long timeo = jiffies + HZ;
2247 unsigned long int adr;
2248 DECLARE_WAITQUEUE(wait, current);
2249 int ret = 0;
2250 int retry_cnt = 0;
2251
2252 adr = cfi->addr_unlock1;
2253
2254 mutex_lock(&chip->mutex);
2255 ret = get_chip(map, chip, adr, FL_WRITING);
2256 if (ret) {
2257 mutex_unlock(&chip->mutex);
2258 return ret;
2259 }
2260
2261 pr_debug("MTD %s(): ERASE 0x%.8lx\n",
2262 __func__, chip->start );
2263
2264 XIP_INVAL_CACHED_RANGE(map, adr, map->size);
2265 ENABLE_VPP(map);
2266 xip_disable(map, chip, adr);
2267
2268 retry:
2269 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2270 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
2271 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2272 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2273 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
2274 cfi_send_gen_cmd(0x10, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2275
2276 chip->state = FL_ERASING;
2277 chip->erase_suspended = 0;
2278 chip->in_progress_block_addr = adr;
2279 chip->in_progress_block_mask = ~(map->size - 1);
2280
2281 INVALIDATE_CACHE_UDELAY(map, chip,
2282 adr, map->size,
2283 chip->erase_time*500);
2284
2285 timeo = jiffies + (HZ*20);
2286
2287 for (;;) {
2288 if (chip->state != FL_ERASING) {
2289 /* Someone's suspended the erase. Sleep */
2290 set_current_state(TASK_UNINTERRUPTIBLE);
2291 add_wait_queue(&chip->wq, &wait);
2292 mutex_unlock(&chip->mutex);
2293 schedule();
2294 remove_wait_queue(&chip->wq, &wait);
2295 mutex_lock(&chip->mutex);
2296 continue;
2297 }
2298 if (chip->erase_suspended) {
2299 /* This erase was suspended and resumed.
2300 Adjust the timeout */
2301 timeo = jiffies + (HZ*20); /* FIXME */
2302 chip->erase_suspended = 0;
2303 }
2304
2305 if (chip_good(map, adr, map_word_ff(map)))
2306 break;
2307
2308 if (time_after(jiffies, timeo)) {
2309 printk(KERN_WARNING "MTD %s(): software timeout\n",
2310 __func__ );
2311 ret = -EIO;
2312 break;
2313 }
2314
2315 /* Latency issues. Drop the lock, wait a while and retry */
2316 UDELAY(map, chip, adr, 1000000/HZ);
2317 }
2318 /* Did we succeed? */
2319 if (ret) {
2320 /* reset on all failures. */
2321 map_write( map, CMD(0xF0), chip->start );
2322 /* FIXME - should have reset delay before continuing */
2323
2324 if (++retry_cnt <= MAX_RETRIES) {
2325 ret = 0;
2326 goto retry;
2327 }
2328 }
2329
2330 chip->state = FL_READY;
2331 xip_enable(map, chip, adr);
2332 DISABLE_VPP(map);
2333 put_chip(map, chip, adr);
2334 mutex_unlock(&chip->mutex);
2335
2336 return ret;
2337 }
2338
2339
do_erase_oneblock(struct map_info * map,struct flchip * chip,unsigned long adr,int len,void * thunk)2340 static int __xipram do_erase_oneblock(struct map_info *map, struct flchip *chip, unsigned long adr, int len, void *thunk)
2341 {
2342 struct cfi_private *cfi = map->fldrv_priv;
2343 unsigned long timeo = jiffies + HZ;
2344 DECLARE_WAITQUEUE(wait, current);
2345 int ret = 0;
2346 int retry_cnt = 0;
2347
2348 adr += chip->start;
2349
2350 mutex_lock(&chip->mutex);
2351 ret = get_chip(map, chip, adr, FL_ERASING);
2352 if (ret) {
2353 mutex_unlock(&chip->mutex);
2354 return ret;
2355 }
2356
2357 pr_debug("MTD %s(): ERASE 0x%.8lx\n",
2358 __func__, adr );
2359
2360 XIP_INVAL_CACHED_RANGE(map, adr, len);
2361 ENABLE_VPP(map);
2362 xip_disable(map, chip, adr);
2363
2364 retry:
2365 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2366 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
2367 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2368 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2369 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
2370 map_write(map, cfi->sector_erase_cmd, adr);
2371
2372 chip->state = FL_ERASING;
2373 chip->erase_suspended = 0;
2374 chip->in_progress_block_addr = adr;
2375 chip->in_progress_block_mask = ~(len - 1);
2376
2377 INVALIDATE_CACHE_UDELAY(map, chip,
2378 adr, len,
2379 chip->erase_time*500);
2380
2381 timeo = jiffies + (HZ*20);
2382
2383 for (;;) {
2384 if (chip->state != FL_ERASING) {
2385 /* Someone's suspended the erase. Sleep */
2386 set_current_state(TASK_UNINTERRUPTIBLE);
2387 add_wait_queue(&chip->wq, &wait);
2388 mutex_unlock(&chip->mutex);
2389 schedule();
2390 remove_wait_queue(&chip->wq, &wait);
2391 mutex_lock(&chip->mutex);
2392 continue;
2393 }
2394 if (chip->erase_suspended) {
2395 /* This erase was suspended and resumed.
2396 Adjust the timeout */
2397 timeo = jiffies + (HZ*20); /* FIXME */
2398 chip->erase_suspended = 0;
2399 }
2400
2401 if (chip_good(map, adr, map_word_ff(map))) {
2402 xip_enable(map, chip, adr);
2403 break;
2404 }
2405
2406 if (time_after(jiffies, timeo)) {
2407 xip_enable(map, chip, adr);
2408 printk(KERN_WARNING "MTD %s(): software timeout\n",
2409 __func__ );
2410 ret = -EIO;
2411 break;
2412 }
2413
2414 /* Latency issues. Drop the lock, wait a while and retry */
2415 UDELAY(map, chip, adr, 1000000/HZ);
2416 }
2417 /* Did we succeed? */
2418 if (ret) {
2419 /* reset on all failures. */
2420 map_write( map, CMD(0xF0), chip->start );
2421 /* FIXME - should have reset delay before continuing */
2422
2423 if (++retry_cnt <= MAX_RETRIES) {
2424 ret = 0;
2425 goto retry;
2426 }
2427 }
2428
2429 chip->state = FL_READY;
2430 DISABLE_VPP(map);
2431 put_chip(map, chip, adr);
2432 mutex_unlock(&chip->mutex);
2433 return ret;
2434 }
2435
2436
cfi_amdstd_erase_varsize(struct mtd_info * mtd,struct erase_info * instr)2437 static int cfi_amdstd_erase_varsize(struct mtd_info *mtd, struct erase_info *instr)
2438 {
2439 unsigned long ofs, len;
2440 int ret;
2441
2442 ofs = instr->addr;
2443 len = instr->len;
2444
2445 ret = cfi_varsize_frob(mtd, do_erase_oneblock, ofs, len, NULL);
2446 if (ret)
2447 return ret;
2448
2449 instr->state = MTD_ERASE_DONE;
2450 mtd_erase_callback(instr);
2451
2452 return 0;
2453 }
2454
2455
cfi_amdstd_erase_chip(struct mtd_info * mtd,struct erase_info * instr)2456 static int cfi_amdstd_erase_chip(struct mtd_info *mtd, struct erase_info *instr)
2457 {
2458 struct map_info *map = mtd->priv;
2459 struct cfi_private *cfi = map->fldrv_priv;
2460 int ret = 0;
2461
2462 if (instr->addr != 0)
2463 return -EINVAL;
2464
2465 if (instr->len != mtd->size)
2466 return -EINVAL;
2467
2468 ret = do_erase_chip(map, &cfi->chips[0]);
2469 if (ret)
2470 return ret;
2471
2472 instr->state = MTD_ERASE_DONE;
2473 mtd_erase_callback(instr);
2474
2475 return 0;
2476 }
2477
do_atmel_lock(struct map_info * map,struct flchip * chip,unsigned long adr,int len,void * thunk)2478 static int do_atmel_lock(struct map_info *map, struct flchip *chip,
2479 unsigned long adr, int len, void *thunk)
2480 {
2481 struct cfi_private *cfi = map->fldrv_priv;
2482 int ret;
2483
2484 mutex_lock(&chip->mutex);
2485 ret = get_chip(map, chip, adr + chip->start, FL_LOCKING);
2486 if (ret)
2487 goto out_unlock;
2488 chip->state = FL_LOCKING;
2489
2490 pr_debug("MTD %s(): LOCK 0x%08lx len %d\n", __func__, adr, len);
2491
2492 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
2493 cfi->device_type, NULL);
2494 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
2495 cfi->device_type, NULL);
2496 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi,
2497 cfi->device_type, NULL);
2498 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
2499 cfi->device_type, NULL);
2500 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
2501 cfi->device_type, NULL);
2502 map_write(map, CMD(0x40), chip->start + adr);
2503
2504 chip->state = FL_READY;
2505 put_chip(map, chip, adr + chip->start);
2506 ret = 0;
2507
2508 out_unlock:
2509 mutex_unlock(&chip->mutex);
2510 return ret;
2511 }
2512
do_atmel_unlock(struct map_info * map,struct flchip * chip,unsigned long adr,int len,void * thunk)2513 static int do_atmel_unlock(struct map_info *map, struct flchip *chip,
2514 unsigned long adr, int len, void *thunk)
2515 {
2516 struct cfi_private *cfi = map->fldrv_priv;
2517 int ret;
2518
2519 mutex_lock(&chip->mutex);
2520 ret = get_chip(map, chip, adr + chip->start, FL_UNLOCKING);
2521 if (ret)
2522 goto out_unlock;
2523 chip->state = FL_UNLOCKING;
2524
2525 pr_debug("MTD %s(): LOCK 0x%08lx len %d\n", __func__, adr, len);
2526
2527 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
2528 cfi->device_type, NULL);
2529 map_write(map, CMD(0x70), adr);
2530
2531 chip->state = FL_READY;
2532 put_chip(map, chip, adr + chip->start);
2533 ret = 0;
2534
2535 out_unlock:
2536 mutex_unlock(&chip->mutex);
2537 return ret;
2538 }
2539
cfi_atmel_lock(struct mtd_info * mtd,loff_t ofs,uint64_t len)2540 static int cfi_atmel_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
2541 {
2542 return cfi_varsize_frob(mtd, do_atmel_lock, ofs, len, NULL);
2543 }
2544
cfi_atmel_unlock(struct mtd_info * mtd,loff_t ofs,uint64_t len)2545 static int cfi_atmel_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
2546 {
2547 return cfi_varsize_frob(mtd, do_atmel_unlock, ofs, len, NULL);
2548 }
2549
2550 /*
2551 * Advanced Sector Protection - PPB (Persistent Protection Bit) locking
2552 */
2553
2554 struct ppb_lock {
2555 struct flchip *chip;
2556 unsigned long adr;
2557 int locked;
2558 };
2559
2560 #define MAX_SECTORS 512
2561
2562 #define DO_XXLOCK_ONEBLOCK_LOCK ((void *)1)
2563 #define DO_XXLOCK_ONEBLOCK_UNLOCK ((void *)2)
2564 #define DO_XXLOCK_ONEBLOCK_GETLOCK ((void *)3)
2565
do_ppb_xxlock(struct map_info * map,struct flchip * chip,unsigned long adr,int len,void * thunk)2566 static int __maybe_unused do_ppb_xxlock(struct map_info *map,
2567 struct flchip *chip,
2568 unsigned long adr, int len, void *thunk)
2569 {
2570 struct cfi_private *cfi = map->fldrv_priv;
2571 unsigned long timeo;
2572 int ret;
2573
2574 adr += chip->start;
2575 mutex_lock(&chip->mutex);
2576 ret = get_chip(map, chip, adr, FL_LOCKING);
2577 if (ret) {
2578 mutex_unlock(&chip->mutex);
2579 return ret;
2580 }
2581
2582 pr_debug("MTD %s(): XXLOCK 0x%08lx len %d\n", __func__, adr, len);
2583
2584 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
2585 cfi->device_type, NULL);
2586 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
2587 cfi->device_type, NULL);
2588 /* PPB entry command */
2589 cfi_send_gen_cmd(0xC0, cfi->addr_unlock1, chip->start, map, cfi,
2590 cfi->device_type, NULL);
2591
2592 if (thunk == DO_XXLOCK_ONEBLOCK_LOCK) {
2593 chip->state = FL_LOCKING;
2594 map_write(map, CMD(0xA0), adr);
2595 map_write(map, CMD(0x00), adr);
2596 } else if (thunk == DO_XXLOCK_ONEBLOCK_UNLOCK) {
2597 /*
2598 * Unlocking of one specific sector is not supported, so we
2599 * have to unlock all sectors of this device instead
2600 */
2601 chip->state = FL_UNLOCKING;
2602 map_write(map, CMD(0x80), chip->start);
2603 map_write(map, CMD(0x30), chip->start);
2604 } else if (thunk == DO_XXLOCK_ONEBLOCK_GETLOCK) {
2605 chip->state = FL_JEDEC_QUERY;
2606 /* Return locked status: 0->locked, 1->unlocked */
2607 ret = !cfi_read_query(map, adr);
2608 } else
2609 BUG();
2610
2611 /*
2612 * Wait for some time as unlocking of all sectors takes quite long
2613 */
2614 timeo = jiffies + msecs_to_jiffies(2000); /* 2s max (un)locking */
2615 for (;;) {
2616 if (chip_ready(map, adr))
2617 break;
2618
2619 if (time_after(jiffies, timeo)) {
2620 printk(KERN_ERR "Waiting for chip to be ready timed out.\n");
2621 ret = -EIO;
2622 break;
2623 }
2624
2625 UDELAY(map, chip, adr, 1);
2626 }
2627
2628 /* Exit BC commands */
2629 map_write(map, CMD(0x90), chip->start);
2630 map_write(map, CMD(0x00), chip->start);
2631
2632 chip->state = FL_READY;
2633 put_chip(map, chip, adr);
2634 mutex_unlock(&chip->mutex);
2635
2636 return ret;
2637 }
2638
cfi_ppb_lock(struct mtd_info * mtd,loff_t ofs,uint64_t len)2639 static int __maybe_unused cfi_ppb_lock(struct mtd_info *mtd, loff_t ofs,
2640 uint64_t len)
2641 {
2642 return cfi_varsize_frob(mtd, do_ppb_xxlock, ofs, len,
2643 DO_XXLOCK_ONEBLOCK_LOCK);
2644 }
2645
cfi_ppb_unlock(struct mtd_info * mtd,loff_t ofs,uint64_t len)2646 static int __maybe_unused cfi_ppb_unlock(struct mtd_info *mtd, loff_t ofs,
2647 uint64_t len)
2648 {
2649 struct mtd_erase_region_info *regions = mtd->eraseregions;
2650 struct map_info *map = mtd->priv;
2651 struct cfi_private *cfi = map->fldrv_priv;
2652 struct ppb_lock *sect;
2653 unsigned long adr;
2654 loff_t offset;
2655 uint64_t length;
2656 int chipnum;
2657 int i;
2658 int sectors;
2659 int ret;
2660
2661 /*
2662 * PPB unlocking always unlocks all sectors of the flash chip.
2663 * We need to re-lock all previously locked sectors. So lets
2664 * first check the locking status of all sectors and save
2665 * it for future use.
2666 */
2667 sect = kzalloc(MAX_SECTORS * sizeof(struct ppb_lock), GFP_KERNEL);
2668 if (!sect)
2669 return -ENOMEM;
2670
2671 /*
2672 * This code to walk all sectors is a slightly modified version
2673 * of the cfi_varsize_frob() code.
2674 */
2675 i = 0;
2676 chipnum = 0;
2677 adr = 0;
2678 sectors = 0;
2679 offset = 0;
2680 length = mtd->size;
2681
2682 while (length) {
2683 int size = regions[i].erasesize;
2684
2685 /*
2686 * Only test sectors that shall not be unlocked. The other
2687 * sectors shall be unlocked, so lets keep their locking
2688 * status at "unlocked" (locked=0) for the final re-locking.
2689 */
2690 if ((offset < ofs) || (offset >= (ofs + len))) {
2691 sect[sectors].chip = &cfi->chips[chipnum];
2692 sect[sectors].adr = adr;
2693 sect[sectors].locked = do_ppb_xxlock(
2694 map, &cfi->chips[chipnum], adr, 0,
2695 DO_XXLOCK_ONEBLOCK_GETLOCK);
2696 }
2697
2698 adr += size;
2699 offset += size;
2700 length -= size;
2701
2702 if (offset == regions[i].offset + size * regions[i].numblocks)
2703 i++;
2704
2705 if (adr >> cfi->chipshift) {
2706 if (offset >= (ofs + len))
2707 break;
2708 adr = 0;
2709 chipnum++;
2710
2711 if (chipnum >= cfi->numchips)
2712 break;
2713 }
2714
2715 sectors++;
2716 if (sectors >= MAX_SECTORS) {
2717 printk(KERN_ERR "Only %d sectors for PPB locking supported!\n",
2718 MAX_SECTORS);
2719 kfree(sect);
2720 return -EINVAL;
2721 }
2722 }
2723
2724 /* Now unlock the whole chip */
2725 ret = cfi_varsize_frob(mtd, do_ppb_xxlock, ofs, len,
2726 DO_XXLOCK_ONEBLOCK_UNLOCK);
2727 if (ret) {
2728 kfree(sect);
2729 return ret;
2730 }
2731
2732 /*
2733 * PPB unlocking always unlocks all sectors of the flash chip.
2734 * We need to re-lock all previously locked sectors.
2735 */
2736 for (i = 0; i < sectors; i++) {
2737 if (sect[i].locked)
2738 do_ppb_xxlock(map, sect[i].chip, sect[i].adr, 0,
2739 DO_XXLOCK_ONEBLOCK_LOCK);
2740 }
2741
2742 kfree(sect);
2743 return ret;
2744 }
2745
cfi_ppb_is_locked(struct mtd_info * mtd,loff_t ofs,uint64_t len)2746 static int __maybe_unused cfi_ppb_is_locked(struct mtd_info *mtd, loff_t ofs,
2747 uint64_t len)
2748 {
2749 return cfi_varsize_frob(mtd, do_ppb_xxlock, ofs, len,
2750 DO_XXLOCK_ONEBLOCK_GETLOCK) ? 1 : 0;
2751 }
2752
cfi_amdstd_sync(struct mtd_info * mtd)2753 static void cfi_amdstd_sync (struct mtd_info *mtd)
2754 {
2755 struct map_info *map = mtd->priv;
2756 struct cfi_private *cfi = map->fldrv_priv;
2757 int i;
2758 struct flchip *chip;
2759 int ret = 0;
2760 DECLARE_WAITQUEUE(wait, current);
2761
2762 for (i=0; !ret && i<cfi->numchips; i++) {
2763 chip = &cfi->chips[i];
2764
2765 retry:
2766 mutex_lock(&chip->mutex);
2767
2768 switch(chip->state) {
2769 case FL_READY:
2770 case FL_STATUS:
2771 case FL_CFI_QUERY:
2772 case FL_JEDEC_QUERY:
2773 chip->oldstate = chip->state;
2774 chip->state = FL_SYNCING;
2775 /* No need to wake_up() on this state change -
2776 * as the whole point is that nobody can do anything
2777 * with the chip now anyway.
2778 */
2779 case FL_SYNCING:
2780 mutex_unlock(&chip->mutex);
2781 break;
2782
2783 default:
2784 /* Not an idle state */
2785 set_current_state(TASK_UNINTERRUPTIBLE);
2786 add_wait_queue(&chip->wq, &wait);
2787
2788 mutex_unlock(&chip->mutex);
2789
2790 schedule();
2791
2792 remove_wait_queue(&chip->wq, &wait);
2793
2794 goto retry;
2795 }
2796 }
2797
2798 /* Unlock the chips again */
2799
2800 for (i--; i >=0; i--) {
2801 chip = &cfi->chips[i];
2802
2803 mutex_lock(&chip->mutex);
2804
2805 if (chip->state == FL_SYNCING) {
2806 chip->state = chip->oldstate;
2807 wake_up(&chip->wq);
2808 }
2809 mutex_unlock(&chip->mutex);
2810 }
2811 }
2812
2813
cfi_amdstd_suspend(struct mtd_info * mtd)2814 static int cfi_amdstd_suspend(struct mtd_info *mtd)
2815 {
2816 struct map_info *map = mtd->priv;
2817 struct cfi_private *cfi = map->fldrv_priv;
2818 int i;
2819 struct flchip *chip;
2820 int ret = 0;
2821
2822 for (i=0; !ret && i<cfi->numchips; i++) {
2823 chip = &cfi->chips[i];
2824
2825 mutex_lock(&chip->mutex);
2826
2827 switch(chip->state) {
2828 case FL_READY:
2829 case FL_STATUS:
2830 case FL_CFI_QUERY:
2831 case FL_JEDEC_QUERY:
2832 chip->oldstate = chip->state;
2833 chip->state = FL_PM_SUSPENDED;
2834 /* No need to wake_up() on this state change -
2835 * as the whole point is that nobody can do anything
2836 * with the chip now anyway.
2837 */
2838 case FL_PM_SUSPENDED:
2839 break;
2840
2841 default:
2842 ret = -EAGAIN;
2843 break;
2844 }
2845 mutex_unlock(&chip->mutex);
2846 }
2847
2848 /* Unlock the chips again */
2849
2850 if (ret) {
2851 for (i--; i >=0; i--) {
2852 chip = &cfi->chips[i];
2853
2854 mutex_lock(&chip->mutex);
2855
2856 if (chip->state == FL_PM_SUSPENDED) {
2857 chip->state = chip->oldstate;
2858 wake_up(&chip->wq);
2859 }
2860 mutex_unlock(&chip->mutex);
2861 }
2862 }
2863
2864 return ret;
2865 }
2866
2867
cfi_amdstd_resume(struct mtd_info * mtd)2868 static void cfi_amdstd_resume(struct mtd_info *mtd)
2869 {
2870 struct map_info *map = mtd->priv;
2871 struct cfi_private *cfi = map->fldrv_priv;
2872 int i;
2873 struct flchip *chip;
2874
2875 for (i=0; i<cfi->numchips; i++) {
2876
2877 chip = &cfi->chips[i];
2878
2879 mutex_lock(&chip->mutex);
2880
2881 if (chip->state == FL_PM_SUSPENDED) {
2882 chip->state = FL_READY;
2883 map_write(map, CMD(0xF0), chip->start);
2884 wake_up(&chip->wq);
2885 }
2886 else
2887 printk(KERN_ERR "Argh. Chip not in PM_SUSPENDED state upon resume()\n");
2888
2889 mutex_unlock(&chip->mutex);
2890 }
2891 }
2892
2893
2894 /*
2895 * Ensure that the flash device is put back into read array mode before
2896 * unloading the driver or rebooting. On some systems, rebooting while
2897 * the flash is in query/program/erase mode will prevent the CPU from
2898 * fetching the bootloader code, requiring a hard reset or power cycle.
2899 */
cfi_amdstd_reset(struct mtd_info * mtd)2900 static int cfi_amdstd_reset(struct mtd_info *mtd)
2901 {
2902 struct map_info *map = mtd->priv;
2903 struct cfi_private *cfi = map->fldrv_priv;
2904 int i, ret;
2905 struct flchip *chip;
2906
2907 for (i = 0; i < cfi->numchips; i++) {
2908
2909 chip = &cfi->chips[i];
2910
2911 mutex_lock(&chip->mutex);
2912
2913 ret = get_chip(map, chip, chip->start, FL_SHUTDOWN);
2914 if (!ret) {
2915 map_write(map, CMD(0xF0), chip->start);
2916 chip->state = FL_SHUTDOWN;
2917 put_chip(map, chip, chip->start);
2918 }
2919
2920 mutex_unlock(&chip->mutex);
2921 }
2922
2923 return 0;
2924 }
2925
2926
cfi_amdstd_reboot(struct notifier_block * nb,unsigned long val,void * v)2927 static int cfi_amdstd_reboot(struct notifier_block *nb, unsigned long val,
2928 void *v)
2929 {
2930 struct mtd_info *mtd;
2931
2932 mtd = container_of(nb, struct mtd_info, reboot_notifier);
2933 cfi_amdstd_reset(mtd);
2934 return NOTIFY_DONE;
2935 }
2936
2937
cfi_amdstd_destroy(struct mtd_info * mtd)2938 static void cfi_amdstd_destroy(struct mtd_info *mtd)
2939 {
2940 struct map_info *map = mtd->priv;
2941 struct cfi_private *cfi = map->fldrv_priv;
2942
2943 cfi_amdstd_reset(mtd);
2944 unregister_reboot_notifier(&mtd->reboot_notifier);
2945 kfree(cfi->cmdset_priv);
2946 kfree(cfi->cfiq);
2947 kfree(cfi);
2948 kfree(mtd->eraseregions);
2949 }
2950
2951 MODULE_LICENSE("GPL");
2952 MODULE_AUTHOR("Crossnet Co. <info@crossnet.co.jp> et al.");
2953 MODULE_DESCRIPTION("MTD chip driver for AMD/Fujitsu flash chips");
2954 MODULE_ALIAS("cfi_cmdset_0006");
2955 MODULE_ALIAS("cfi_cmdset_0701");
2956