1 /*
2 * Copyright 2009-2015 Freescale Semiconductor, Inc. and others
3 *
4 * Description: MPC5125, VF610, MCF54418 and Kinetis K70 Nand driver.
5 * Jason ported to M54418TWR and MVFA5 (VF610).
6 * Authors: Stefan Agner <stefan.agner@toradex.com>
7 * Bill Pringlemeir <bpringlemeir@nbsps.com>
8 * Shaohui Xie <b21989@freescale.com>
9 * Jason Jin <Jason.jin@freescale.com>
10 *
11 * Based on original driver mpc5121_nfc.c.
12 *
13 * This is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * Limitations:
19 * - Untested on MPC5125 and M54418.
20 * - DMA and pipelining not used.
21 * - 2K pages or less.
22 * - HW ECC: Only 2K page with 64+ OOB.
23 * - HW ECC: Only 24 and 32-bit error correction implemented.
24 */
25
26 #include <linux/module.h>
27 #include <linux/bitops.h>
28 #include <linux/clk.h>
29 #include <linux/delay.h>
30 #include <linux/init.h>
31 #include <linux/interrupt.h>
32 #include <linux/io.h>
33 #include <linux/mtd/mtd.h>
34 #include <linux/mtd/rawnand.h>
35 #include <linux/mtd/partitions.h>
36 #include <linux/of_device.h>
37 #include <linux/platform_device.h>
38 #include <linux/slab.h>
39
40 #define DRV_NAME "vf610_nfc"
41
42 /* Register Offsets */
43 #define NFC_FLASH_CMD1 0x3F00
44 #define NFC_FLASH_CMD2 0x3F04
45 #define NFC_COL_ADDR 0x3F08
46 #define NFC_ROW_ADDR 0x3F0c
47 #define NFC_ROW_ADDR_INC 0x3F14
48 #define NFC_FLASH_STATUS1 0x3F18
49 #define NFC_FLASH_STATUS2 0x3F1c
50 #define NFC_CACHE_SWAP 0x3F28
51 #define NFC_SECTOR_SIZE 0x3F2c
52 #define NFC_FLASH_CONFIG 0x3F30
53 #define NFC_IRQ_STATUS 0x3F38
54
55 /* Addresses for NFC MAIN RAM BUFFER areas */
56 #define NFC_MAIN_AREA(n) ((n) * 0x1000)
57
58 #define PAGE_2K 0x0800
59 #define OOB_64 0x0040
60 #define OOB_MAX 0x0100
61
62 /*
63 * NFC_CMD2[CODE] values. See section:
64 * - 31.4.7 Flash Command Code Description, Vybrid manual
65 * - 23.8.6 Flash Command Sequencer, MPC5125 manual
66 *
67 * Briefly these are bitmasks of controller cycles.
68 */
69 #define READ_PAGE_CMD_CODE 0x7EE0
70 #define READ_ONFI_PARAM_CMD_CODE 0x4860
71 #define PROGRAM_PAGE_CMD_CODE 0x7FC0
72 #define ERASE_CMD_CODE 0x4EC0
73 #define READ_ID_CMD_CODE 0x4804
74 #define RESET_CMD_CODE 0x4040
75 #define STATUS_READ_CMD_CODE 0x4068
76
77 /* NFC ECC mode define */
78 #define ECC_BYPASS 0
79 #define ECC_45_BYTE 6
80 #define ECC_60_BYTE 7
81
82 /*** Register Mask and bit definitions */
83
84 /* NFC_FLASH_CMD1 Field */
85 #define CMD_BYTE2_MASK 0xFF000000
86 #define CMD_BYTE2_SHIFT 24
87
88 /* NFC_FLASH_CM2 Field */
89 #define CMD_BYTE1_MASK 0xFF000000
90 #define CMD_BYTE1_SHIFT 24
91 #define CMD_CODE_MASK 0x00FFFF00
92 #define CMD_CODE_SHIFT 8
93 #define BUFNO_MASK 0x00000006
94 #define BUFNO_SHIFT 1
95 #define START_BIT BIT(0)
96
97 /* NFC_COL_ADDR Field */
98 #define COL_ADDR_MASK 0x0000FFFF
99 #define COL_ADDR_SHIFT 0
100
101 /* NFC_ROW_ADDR Field */
102 #define ROW_ADDR_MASK 0x00FFFFFF
103 #define ROW_ADDR_SHIFT 0
104 #define ROW_ADDR_CHIP_SEL_RB_MASK 0xF0000000
105 #define ROW_ADDR_CHIP_SEL_RB_SHIFT 28
106 #define ROW_ADDR_CHIP_SEL_MASK 0x0F000000
107 #define ROW_ADDR_CHIP_SEL_SHIFT 24
108
109 /* NFC_FLASH_STATUS2 Field */
110 #define STATUS_BYTE1_MASK 0x000000FF
111
112 /* NFC_FLASH_CONFIG Field */
113 #define CONFIG_ECC_SRAM_ADDR_MASK 0x7FC00000
114 #define CONFIG_ECC_SRAM_ADDR_SHIFT 22
115 #define CONFIG_ECC_SRAM_REQ_BIT BIT(21)
116 #define CONFIG_DMA_REQ_BIT BIT(20)
117 #define CONFIG_ECC_MODE_MASK 0x000E0000
118 #define CONFIG_ECC_MODE_SHIFT 17
119 #define CONFIG_FAST_FLASH_BIT BIT(16)
120 #define CONFIG_16BIT BIT(7)
121 #define CONFIG_BOOT_MODE_BIT BIT(6)
122 #define CONFIG_ADDR_AUTO_INCR_BIT BIT(5)
123 #define CONFIG_BUFNO_AUTO_INCR_BIT BIT(4)
124 #define CONFIG_PAGE_CNT_MASK 0xF
125 #define CONFIG_PAGE_CNT_SHIFT 0
126
127 /* NFC_IRQ_STATUS Field */
128 #define IDLE_IRQ_BIT BIT(29)
129 #define IDLE_EN_BIT BIT(20)
130 #define CMD_DONE_CLEAR_BIT BIT(18)
131 #define IDLE_CLEAR_BIT BIT(17)
132
133 /*
134 * ECC status - seems to consume 8 bytes (double word). The documented
135 * status byte is located in the lowest byte of the second word (which is
136 * the 4th or 7th byte depending on endianness).
137 * Calculate an offset to store the ECC status at the end of the buffer.
138 */
139 #define ECC_SRAM_ADDR (PAGE_2K + OOB_MAX - 8)
140
141 #define ECC_STATUS 0x4
142 #define ECC_STATUS_MASK 0x80
143 #define ECC_STATUS_ERR_COUNT 0x3F
144
145 enum vf610_nfc_alt_buf {
146 ALT_BUF_DATA = 0,
147 ALT_BUF_ID = 1,
148 ALT_BUF_STAT = 2,
149 ALT_BUF_ONFI = 3,
150 };
151
152 enum vf610_nfc_variant {
153 NFC_VFC610 = 1,
154 };
155
156 struct vf610_nfc {
157 struct nand_chip chip;
158 struct device *dev;
159 void __iomem *regs;
160 struct completion cmd_done;
161 uint buf_offset;
162 int write_sz;
163 /* Status and ID are in alternate locations. */
164 enum vf610_nfc_alt_buf alt_buf;
165 enum vf610_nfc_variant variant;
166 struct clk *clk;
167 bool use_hw_ecc;
168 u32 ecc_mode;
169 };
170
mtd_to_nfc(struct mtd_info * mtd)171 static inline struct vf610_nfc *mtd_to_nfc(struct mtd_info *mtd)
172 {
173 return container_of(mtd_to_nand(mtd), struct vf610_nfc, chip);
174 }
175
vf610_nfc_read(struct vf610_nfc * nfc,uint reg)176 static inline u32 vf610_nfc_read(struct vf610_nfc *nfc, uint reg)
177 {
178 return readl(nfc->regs + reg);
179 }
180
vf610_nfc_write(struct vf610_nfc * nfc,uint reg,u32 val)181 static inline void vf610_nfc_write(struct vf610_nfc *nfc, uint reg, u32 val)
182 {
183 writel(val, nfc->regs + reg);
184 }
185
vf610_nfc_set(struct vf610_nfc * nfc,uint reg,u32 bits)186 static inline void vf610_nfc_set(struct vf610_nfc *nfc, uint reg, u32 bits)
187 {
188 vf610_nfc_write(nfc, reg, vf610_nfc_read(nfc, reg) | bits);
189 }
190
vf610_nfc_clear(struct vf610_nfc * nfc,uint reg,u32 bits)191 static inline void vf610_nfc_clear(struct vf610_nfc *nfc, uint reg, u32 bits)
192 {
193 vf610_nfc_write(nfc, reg, vf610_nfc_read(nfc, reg) & ~bits);
194 }
195
vf610_nfc_set_field(struct vf610_nfc * nfc,u32 reg,u32 mask,u32 shift,u32 val)196 static inline void vf610_nfc_set_field(struct vf610_nfc *nfc, u32 reg,
197 u32 mask, u32 shift, u32 val)
198 {
199 vf610_nfc_write(nfc, reg,
200 (vf610_nfc_read(nfc, reg) & (~mask)) | val << shift);
201 }
202
vf610_nfc_memcpy(void * dst,const void __iomem * src,size_t n)203 static inline void vf610_nfc_memcpy(void *dst, const void __iomem *src,
204 size_t n)
205 {
206 /*
207 * Use this accessor for the internal SRAM buffers. On the ARM
208 * Freescale Vybrid SoC it's known that the driver can treat
209 * the SRAM buffer as if it's memory. Other platform might need
210 * to treat the buffers differently.
211 *
212 * For the time being, use memcpy
213 */
214 memcpy(dst, src, n);
215 }
216
217 /* Clear flags for upcoming command */
vf610_nfc_clear_status(struct vf610_nfc * nfc)218 static inline void vf610_nfc_clear_status(struct vf610_nfc *nfc)
219 {
220 u32 tmp = vf610_nfc_read(nfc, NFC_IRQ_STATUS);
221
222 tmp |= CMD_DONE_CLEAR_BIT | IDLE_CLEAR_BIT;
223 vf610_nfc_write(nfc, NFC_IRQ_STATUS, tmp);
224 }
225
vf610_nfc_done(struct vf610_nfc * nfc)226 static void vf610_nfc_done(struct vf610_nfc *nfc)
227 {
228 unsigned long timeout = msecs_to_jiffies(100);
229
230 /*
231 * Barrier is needed after this write. This write need
232 * to be done before reading the next register the first
233 * time.
234 * vf610_nfc_set implicates such a barrier by using writel
235 * to write to the register.
236 */
237 vf610_nfc_set(nfc, NFC_IRQ_STATUS, IDLE_EN_BIT);
238 vf610_nfc_set(nfc, NFC_FLASH_CMD2, START_BIT);
239
240 if (!wait_for_completion_timeout(&nfc->cmd_done, timeout))
241 dev_warn(nfc->dev, "Timeout while waiting for BUSY.\n");
242
243 vf610_nfc_clear_status(nfc);
244 }
245
vf610_nfc_get_id(struct vf610_nfc * nfc,int col)246 static u8 vf610_nfc_get_id(struct vf610_nfc *nfc, int col)
247 {
248 u32 flash_id;
249
250 if (col < 4) {
251 flash_id = vf610_nfc_read(nfc, NFC_FLASH_STATUS1);
252 flash_id >>= (3 - col) * 8;
253 } else {
254 flash_id = vf610_nfc_read(nfc, NFC_FLASH_STATUS2);
255 flash_id >>= 24;
256 }
257
258 return flash_id & 0xff;
259 }
260
vf610_nfc_get_status(struct vf610_nfc * nfc)261 static u8 vf610_nfc_get_status(struct vf610_nfc *nfc)
262 {
263 return vf610_nfc_read(nfc, NFC_FLASH_STATUS2) & STATUS_BYTE1_MASK;
264 }
265
vf610_nfc_send_command(struct vf610_nfc * nfc,u32 cmd_byte1,u32 cmd_code)266 static void vf610_nfc_send_command(struct vf610_nfc *nfc, u32 cmd_byte1,
267 u32 cmd_code)
268 {
269 u32 tmp;
270
271 vf610_nfc_clear_status(nfc);
272
273 tmp = vf610_nfc_read(nfc, NFC_FLASH_CMD2);
274 tmp &= ~(CMD_BYTE1_MASK | CMD_CODE_MASK | BUFNO_MASK);
275 tmp |= cmd_byte1 << CMD_BYTE1_SHIFT;
276 tmp |= cmd_code << CMD_CODE_SHIFT;
277 vf610_nfc_write(nfc, NFC_FLASH_CMD2, tmp);
278 }
279
vf610_nfc_send_commands(struct vf610_nfc * nfc,u32 cmd_byte1,u32 cmd_byte2,u32 cmd_code)280 static void vf610_nfc_send_commands(struct vf610_nfc *nfc, u32 cmd_byte1,
281 u32 cmd_byte2, u32 cmd_code)
282 {
283 u32 tmp;
284
285 vf610_nfc_send_command(nfc, cmd_byte1, cmd_code);
286
287 tmp = vf610_nfc_read(nfc, NFC_FLASH_CMD1);
288 tmp &= ~CMD_BYTE2_MASK;
289 tmp |= cmd_byte2 << CMD_BYTE2_SHIFT;
290 vf610_nfc_write(nfc, NFC_FLASH_CMD1, tmp);
291 }
292
vf610_nfc_irq(int irq,void * data)293 static irqreturn_t vf610_nfc_irq(int irq, void *data)
294 {
295 struct mtd_info *mtd = data;
296 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
297
298 vf610_nfc_clear(nfc, NFC_IRQ_STATUS, IDLE_EN_BIT);
299 complete(&nfc->cmd_done);
300
301 return IRQ_HANDLED;
302 }
303
vf610_nfc_addr_cycle(struct vf610_nfc * nfc,int column,int page)304 static void vf610_nfc_addr_cycle(struct vf610_nfc *nfc, int column, int page)
305 {
306 if (column != -1) {
307 if (nfc->chip.options & NAND_BUSWIDTH_16)
308 column = column / 2;
309 vf610_nfc_set_field(nfc, NFC_COL_ADDR, COL_ADDR_MASK,
310 COL_ADDR_SHIFT, column);
311 }
312 if (page != -1)
313 vf610_nfc_set_field(nfc, NFC_ROW_ADDR, ROW_ADDR_MASK,
314 ROW_ADDR_SHIFT, page);
315 }
316
vf610_nfc_ecc_mode(struct vf610_nfc * nfc,int ecc_mode)317 static inline void vf610_nfc_ecc_mode(struct vf610_nfc *nfc, int ecc_mode)
318 {
319 vf610_nfc_set_field(nfc, NFC_FLASH_CONFIG,
320 CONFIG_ECC_MODE_MASK,
321 CONFIG_ECC_MODE_SHIFT, ecc_mode);
322 }
323
vf610_nfc_transfer_size(struct vf610_nfc * nfc,int size)324 static inline void vf610_nfc_transfer_size(struct vf610_nfc *nfc, int size)
325 {
326 vf610_nfc_write(nfc, NFC_SECTOR_SIZE, size);
327 }
328
vf610_nfc_command(struct mtd_info * mtd,unsigned command,int column,int page)329 static void vf610_nfc_command(struct mtd_info *mtd, unsigned command,
330 int column, int page)
331 {
332 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
333 int trfr_sz = nfc->chip.options & NAND_BUSWIDTH_16 ? 1 : 0;
334
335 nfc->buf_offset = max(column, 0);
336 nfc->alt_buf = ALT_BUF_DATA;
337
338 switch (command) {
339 case NAND_CMD_SEQIN:
340 /* Use valid column/page from preread... */
341 vf610_nfc_addr_cycle(nfc, column, page);
342 nfc->buf_offset = 0;
343
344 /*
345 * SEQIN => data => PAGEPROG sequence is done by the controller
346 * hence we do not need to issue the command here...
347 */
348 return;
349 case NAND_CMD_PAGEPROG:
350 trfr_sz += nfc->write_sz;
351 vf610_nfc_transfer_size(nfc, trfr_sz);
352 vf610_nfc_send_commands(nfc, NAND_CMD_SEQIN,
353 command, PROGRAM_PAGE_CMD_CODE);
354 if (nfc->use_hw_ecc)
355 vf610_nfc_ecc_mode(nfc, nfc->ecc_mode);
356 else
357 vf610_nfc_ecc_mode(nfc, ECC_BYPASS);
358 break;
359
360 case NAND_CMD_RESET:
361 vf610_nfc_transfer_size(nfc, 0);
362 vf610_nfc_send_command(nfc, command, RESET_CMD_CODE);
363 break;
364
365 case NAND_CMD_READOOB:
366 trfr_sz += mtd->oobsize;
367 column = mtd->writesize;
368 vf610_nfc_transfer_size(nfc, trfr_sz);
369 vf610_nfc_send_commands(nfc, NAND_CMD_READ0,
370 NAND_CMD_READSTART, READ_PAGE_CMD_CODE);
371 vf610_nfc_addr_cycle(nfc, column, page);
372 vf610_nfc_ecc_mode(nfc, ECC_BYPASS);
373 break;
374
375 case NAND_CMD_READ0:
376 trfr_sz += mtd->writesize + mtd->oobsize;
377 vf610_nfc_transfer_size(nfc, trfr_sz);
378 vf610_nfc_send_commands(nfc, NAND_CMD_READ0,
379 NAND_CMD_READSTART, READ_PAGE_CMD_CODE);
380 vf610_nfc_addr_cycle(nfc, column, page);
381 vf610_nfc_ecc_mode(nfc, nfc->ecc_mode);
382 break;
383
384 case NAND_CMD_PARAM:
385 nfc->alt_buf = ALT_BUF_ONFI;
386 trfr_sz = 3 * sizeof(struct nand_onfi_params);
387 vf610_nfc_transfer_size(nfc, trfr_sz);
388 vf610_nfc_send_command(nfc, command, READ_ONFI_PARAM_CMD_CODE);
389 vf610_nfc_addr_cycle(nfc, -1, column);
390 vf610_nfc_ecc_mode(nfc, ECC_BYPASS);
391 break;
392
393 case NAND_CMD_ERASE1:
394 vf610_nfc_transfer_size(nfc, 0);
395 vf610_nfc_send_commands(nfc, command,
396 NAND_CMD_ERASE2, ERASE_CMD_CODE);
397 vf610_nfc_addr_cycle(nfc, column, page);
398 break;
399
400 case NAND_CMD_READID:
401 nfc->alt_buf = ALT_BUF_ID;
402 nfc->buf_offset = 0;
403 vf610_nfc_transfer_size(nfc, 0);
404 vf610_nfc_send_command(nfc, command, READ_ID_CMD_CODE);
405 vf610_nfc_addr_cycle(nfc, -1, column);
406 break;
407
408 case NAND_CMD_STATUS:
409 nfc->alt_buf = ALT_BUF_STAT;
410 vf610_nfc_transfer_size(nfc, 0);
411 vf610_nfc_send_command(nfc, command, STATUS_READ_CMD_CODE);
412 break;
413 default:
414 return;
415 }
416
417 vf610_nfc_done(nfc);
418
419 nfc->use_hw_ecc = false;
420 nfc->write_sz = 0;
421 }
422
vf610_nfc_read_buf(struct mtd_info * mtd,u_char * buf,int len)423 static void vf610_nfc_read_buf(struct mtd_info *mtd, u_char *buf, int len)
424 {
425 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
426 uint c = nfc->buf_offset;
427
428 /* Alternate buffers are only supported through read_byte */
429 WARN_ON(nfc->alt_buf);
430
431 vf610_nfc_memcpy(buf, nfc->regs + NFC_MAIN_AREA(0) + c, len);
432
433 nfc->buf_offset += len;
434 }
435
vf610_nfc_write_buf(struct mtd_info * mtd,const uint8_t * buf,int len)436 static void vf610_nfc_write_buf(struct mtd_info *mtd, const uint8_t *buf,
437 int len)
438 {
439 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
440 uint c = nfc->buf_offset;
441 uint l;
442
443 l = min_t(uint, len, mtd->writesize + mtd->oobsize - c);
444 vf610_nfc_memcpy(nfc->regs + NFC_MAIN_AREA(0) + c, buf, l);
445
446 nfc->write_sz += l;
447 nfc->buf_offset += l;
448 }
449
vf610_nfc_read_byte(struct mtd_info * mtd)450 static uint8_t vf610_nfc_read_byte(struct mtd_info *mtd)
451 {
452 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
453 u8 tmp;
454 uint c = nfc->buf_offset;
455
456 switch (nfc->alt_buf) {
457 case ALT_BUF_ID:
458 tmp = vf610_nfc_get_id(nfc, c);
459 break;
460 case ALT_BUF_STAT:
461 tmp = vf610_nfc_get_status(nfc);
462 break;
463 #ifdef __LITTLE_ENDIAN
464 case ALT_BUF_ONFI:
465 /* Reverse byte since the controller uses big endianness */
466 c = nfc->buf_offset ^ 0x3;
467 /* fall-through */
468 #endif
469 default:
470 tmp = *((u8 *)(nfc->regs + NFC_MAIN_AREA(0) + c));
471 break;
472 }
473 nfc->buf_offset++;
474 return tmp;
475 }
476
vf610_nfc_read_word(struct mtd_info * mtd)477 static u16 vf610_nfc_read_word(struct mtd_info *mtd)
478 {
479 u16 tmp;
480
481 vf610_nfc_read_buf(mtd, (u_char *)&tmp, sizeof(tmp));
482 return tmp;
483 }
484
485 /* If not provided, upper layers apply a fixed delay. */
vf610_nfc_dev_ready(struct mtd_info * mtd)486 static int vf610_nfc_dev_ready(struct mtd_info *mtd)
487 {
488 /* NFC handles R/B internally; always ready. */
489 return 1;
490 }
491
492 /*
493 * This function supports Vybrid only (MPC5125 would have full RB and four CS)
494 */
vf610_nfc_select_chip(struct mtd_info * mtd,int chip)495 static void vf610_nfc_select_chip(struct mtd_info *mtd, int chip)
496 {
497 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
498 u32 tmp = vf610_nfc_read(nfc, NFC_ROW_ADDR);
499
500 /* Vybrid only (MPC5125 would have full RB and four CS) */
501 if (nfc->variant != NFC_VFC610)
502 return;
503
504 tmp &= ~(ROW_ADDR_CHIP_SEL_RB_MASK | ROW_ADDR_CHIP_SEL_MASK);
505
506 if (chip >= 0) {
507 tmp |= 1 << ROW_ADDR_CHIP_SEL_RB_SHIFT;
508 tmp |= BIT(chip) << ROW_ADDR_CHIP_SEL_SHIFT;
509 }
510
511 vf610_nfc_write(nfc, NFC_ROW_ADDR, tmp);
512 }
513
514 /* Count the number of 0's in buff up to max_bits */
count_written_bits(uint8_t * buff,int size,int max_bits)515 static inline int count_written_bits(uint8_t *buff, int size, int max_bits)
516 {
517 uint32_t *buff32 = (uint32_t *)buff;
518 int k, written_bits = 0;
519
520 for (k = 0; k < (size / 4); k++) {
521 written_bits += hweight32(~buff32[k]);
522 if (unlikely(written_bits > max_bits))
523 break;
524 }
525
526 return written_bits;
527 }
528
vf610_nfc_correct_data(struct mtd_info * mtd,uint8_t * dat,uint8_t * oob,int page)529 static inline int vf610_nfc_correct_data(struct mtd_info *mtd, uint8_t *dat,
530 uint8_t *oob, int page)
531 {
532 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
533 u32 ecc_status_off = NFC_MAIN_AREA(0) + ECC_SRAM_ADDR + ECC_STATUS;
534 u8 ecc_status;
535 u8 ecc_count;
536 int flips_threshold = nfc->chip.ecc.strength / 2;
537
538 ecc_status = vf610_nfc_read(nfc, ecc_status_off) & 0xff;
539 ecc_count = ecc_status & ECC_STATUS_ERR_COUNT;
540
541 if (!(ecc_status & ECC_STATUS_MASK))
542 return ecc_count;
543
544 /* Read OOB without ECC unit enabled */
545 vf610_nfc_command(mtd, NAND_CMD_READOOB, 0, page);
546 vf610_nfc_read_buf(mtd, oob, mtd->oobsize);
547
548 /*
549 * On an erased page, bit count (including OOB) should be zero or
550 * at least less then half of the ECC strength.
551 */
552 return nand_check_erased_ecc_chunk(dat, nfc->chip.ecc.size, oob,
553 mtd->oobsize, NULL, 0,
554 flips_threshold);
555 }
556
vf610_nfc_read_page(struct mtd_info * mtd,struct nand_chip * chip,uint8_t * buf,int oob_required,int page)557 static int vf610_nfc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
558 uint8_t *buf, int oob_required, int page)
559 {
560 int eccsize = chip->ecc.size;
561 int stat;
562
563 vf610_nfc_read_buf(mtd, buf, eccsize);
564 if (oob_required)
565 vf610_nfc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
566
567 stat = vf610_nfc_correct_data(mtd, buf, chip->oob_poi, page);
568
569 if (stat < 0) {
570 mtd->ecc_stats.failed++;
571 return 0;
572 } else {
573 mtd->ecc_stats.corrected += stat;
574 return stat;
575 }
576 }
577
vf610_nfc_write_page(struct mtd_info * mtd,struct nand_chip * chip,const uint8_t * buf,int oob_required,int page)578 static int vf610_nfc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
579 const uint8_t *buf, int oob_required, int page)
580 {
581 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
582
583 vf610_nfc_write_buf(mtd, buf, mtd->writesize);
584 if (oob_required)
585 vf610_nfc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
586
587 /* Always write whole page including OOB due to HW ECC */
588 nfc->use_hw_ecc = true;
589 nfc->write_sz = mtd->writesize + mtd->oobsize;
590
591 return 0;
592 }
593
594 static const struct of_device_id vf610_nfc_dt_ids[] = {
595 { .compatible = "fsl,vf610-nfc", .data = (void *)NFC_VFC610 },
596 { /* sentinel */ }
597 };
598 MODULE_DEVICE_TABLE(of, vf610_nfc_dt_ids);
599
vf610_nfc_preinit_controller(struct vf610_nfc * nfc)600 static void vf610_nfc_preinit_controller(struct vf610_nfc *nfc)
601 {
602 vf610_nfc_clear(nfc, NFC_FLASH_CONFIG, CONFIG_16BIT);
603 vf610_nfc_clear(nfc, NFC_FLASH_CONFIG, CONFIG_ADDR_AUTO_INCR_BIT);
604 vf610_nfc_clear(nfc, NFC_FLASH_CONFIG, CONFIG_BUFNO_AUTO_INCR_BIT);
605 vf610_nfc_clear(nfc, NFC_FLASH_CONFIG, CONFIG_BOOT_MODE_BIT);
606 vf610_nfc_clear(nfc, NFC_FLASH_CONFIG, CONFIG_DMA_REQ_BIT);
607 vf610_nfc_set(nfc, NFC_FLASH_CONFIG, CONFIG_FAST_FLASH_BIT);
608
609 /* Disable virtual pages, only one elementary transfer unit */
610 vf610_nfc_set_field(nfc, NFC_FLASH_CONFIG, CONFIG_PAGE_CNT_MASK,
611 CONFIG_PAGE_CNT_SHIFT, 1);
612 }
613
vf610_nfc_init_controller(struct vf610_nfc * nfc)614 static void vf610_nfc_init_controller(struct vf610_nfc *nfc)
615 {
616 if (nfc->chip.options & NAND_BUSWIDTH_16)
617 vf610_nfc_set(nfc, NFC_FLASH_CONFIG, CONFIG_16BIT);
618 else
619 vf610_nfc_clear(nfc, NFC_FLASH_CONFIG, CONFIG_16BIT);
620
621 if (nfc->chip.ecc.mode == NAND_ECC_HW) {
622 /* Set ECC status offset in SRAM */
623 vf610_nfc_set_field(nfc, NFC_FLASH_CONFIG,
624 CONFIG_ECC_SRAM_ADDR_MASK,
625 CONFIG_ECC_SRAM_ADDR_SHIFT,
626 ECC_SRAM_ADDR >> 3);
627
628 /* Enable ECC status in SRAM */
629 vf610_nfc_set(nfc, NFC_FLASH_CONFIG, CONFIG_ECC_SRAM_REQ_BIT);
630 }
631 }
632
vf610_nfc_probe(struct platform_device * pdev)633 static int vf610_nfc_probe(struct platform_device *pdev)
634 {
635 struct vf610_nfc *nfc;
636 struct resource *res;
637 struct mtd_info *mtd;
638 struct nand_chip *chip;
639 struct device_node *child;
640 const struct of_device_id *of_id;
641 int err;
642 int irq;
643
644 nfc = devm_kzalloc(&pdev->dev, sizeof(*nfc), GFP_KERNEL);
645 if (!nfc)
646 return -ENOMEM;
647
648 nfc->dev = &pdev->dev;
649 chip = &nfc->chip;
650 mtd = nand_to_mtd(chip);
651
652 mtd->owner = THIS_MODULE;
653 mtd->dev.parent = nfc->dev;
654 mtd->name = DRV_NAME;
655
656 irq = platform_get_irq(pdev, 0);
657 if (irq <= 0)
658 return -EINVAL;
659
660 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
661 nfc->regs = devm_ioremap_resource(nfc->dev, res);
662 if (IS_ERR(nfc->regs))
663 return PTR_ERR(nfc->regs);
664
665 nfc->clk = devm_clk_get(&pdev->dev, NULL);
666 if (IS_ERR(nfc->clk))
667 return PTR_ERR(nfc->clk);
668
669 err = clk_prepare_enable(nfc->clk);
670 if (err) {
671 dev_err(nfc->dev, "Unable to enable clock!\n");
672 return err;
673 }
674
675 of_id = of_match_device(vf610_nfc_dt_ids, &pdev->dev);
676 nfc->variant = (enum vf610_nfc_variant)of_id->data;
677
678 for_each_available_child_of_node(nfc->dev->of_node, child) {
679 if (of_device_is_compatible(child, "fsl,vf610-nfc-nandcs")) {
680
681 if (nand_get_flash_node(chip)) {
682 dev_err(nfc->dev,
683 "Only one NAND chip supported!\n");
684 err = -EINVAL;
685 goto error;
686 }
687
688 nand_set_flash_node(chip, child);
689 }
690 }
691
692 if (!nand_get_flash_node(chip)) {
693 dev_err(nfc->dev, "NAND chip sub-node missing!\n");
694 err = -ENODEV;
695 goto err_clk;
696 }
697
698 chip->dev_ready = vf610_nfc_dev_ready;
699 chip->cmdfunc = vf610_nfc_command;
700 chip->read_byte = vf610_nfc_read_byte;
701 chip->read_word = vf610_nfc_read_word;
702 chip->read_buf = vf610_nfc_read_buf;
703 chip->write_buf = vf610_nfc_write_buf;
704 chip->select_chip = vf610_nfc_select_chip;
705 chip->onfi_set_features = nand_onfi_get_set_features_notsupp;
706 chip->onfi_get_features = nand_onfi_get_set_features_notsupp;
707
708 chip->options |= NAND_NO_SUBPAGE_WRITE;
709
710 init_completion(&nfc->cmd_done);
711
712 err = devm_request_irq(nfc->dev, irq, vf610_nfc_irq, 0, DRV_NAME, mtd);
713 if (err) {
714 dev_err(nfc->dev, "Error requesting IRQ!\n");
715 goto error;
716 }
717
718 vf610_nfc_preinit_controller(nfc);
719
720 /* first scan to find the device and get the page size */
721 err = nand_scan_ident(mtd, 1, NULL);
722 if (err)
723 goto error;
724
725 vf610_nfc_init_controller(nfc);
726
727 /* Bad block options. */
728 if (chip->bbt_options & NAND_BBT_USE_FLASH)
729 chip->bbt_options |= NAND_BBT_NO_OOB;
730
731 /* Single buffer only, max 256 OOB minus ECC status */
732 if (mtd->writesize + mtd->oobsize > PAGE_2K + OOB_MAX - 8) {
733 dev_err(nfc->dev, "Unsupported flash page size\n");
734 err = -ENXIO;
735 goto error;
736 }
737
738 if (chip->ecc.mode == NAND_ECC_HW) {
739 if (mtd->writesize != PAGE_2K && mtd->oobsize < 64) {
740 dev_err(nfc->dev, "Unsupported flash with hwecc\n");
741 err = -ENXIO;
742 goto error;
743 }
744
745 if (chip->ecc.size != mtd->writesize) {
746 dev_err(nfc->dev, "Step size needs to be page size\n");
747 err = -ENXIO;
748 goto error;
749 }
750
751 /* Only 64 byte ECC layouts known */
752 if (mtd->oobsize > 64)
753 mtd->oobsize = 64;
754
755 /* Use default large page ECC layout defined in NAND core */
756 mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops);
757 if (chip->ecc.strength == 32) {
758 nfc->ecc_mode = ECC_60_BYTE;
759 chip->ecc.bytes = 60;
760 } else if (chip->ecc.strength == 24) {
761 nfc->ecc_mode = ECC_45_BYTE;
762 chip->ecc.bytes = 45;
763 } else {
764 dev_err(nfc->dev, "Unsupported ECC strength\n");
765 err = -ENXIO;
766 goto error;
767 }
768
769 chip->ecc.read_page = vf610_nfc_read_page;
770 chip->ecc.write_page = vf610_nfc_write_page;
771
772 chip->ecc.size = PAGE_2K;
773 }
774
775 /* second phase scan */
776 err = nand_scan_tail(mtd);
777 if (err)
778 goto error;
779
780 platform_set_drvdata(pdev, mtd);
781
782 /* Register device in MTD */
783 return mtd_device_register(mtd, NULL, 0);
784
785 error:
786 of_node_put(nand_get_flash_node(chip));
787 err_clk:
788 clk_disable_unprepare(nfc->clk);
789 return err;
790 }
791
vf610_nfc_remove(struct platform_device * pdev)792 static int vf610_nfc_remove(struct platform_device *pdev)
793 {
794 struct mtd_info *mtd = platform_get_drvdata(pdev);
795 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
796
797 nand_release(mtd);
798 clk_disable_unprepare(nfc->clk);
799 return 0;
800 }
801
802 #ifdef CONFIG_PM_SLEEP
vf610_nfc_suspend(struct device * dev)803 static int vf610_nfc_suspend(struct device *dev)
804 {
805 struct mtd_info *mtd = dev_get_drvdata(dev);
806 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
807
808 clk_disable_unprepare(nfc->clk);
809 return 0;
810 }
811
vf610_nfc_resume(struct device * dev)812 static int vf610_nfc_resume(struct device *dev)
813 {
814 int err;
815
816 struct mtd_info *mtd = dev_get_drvdata(dev);
817 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
818
819 err = clk_prepare_enable(nfc->clk);
820 if (err)
821 return err;
822
823 vf610_nfc_preinit_controller(nfc);
824 vf610_nfc_init_controller(nfc);
825 return 0;
826 }
827 #endif
828
829 static SIMPLE_DEV_PM_OPS(vf610_nfc_pm_ops, vf610_nfc_suspend, vf610_nfc_resume);
830
831 static struct platform_driver vf610_nfc_driver = {
832 .driver = {
833 .name = DRV_NAME,
834 .of_match_table = vf610_nfc_dt_ids,
835 .pm = &vf610_nfc_pm_ops,
836 },
837 .probe = vf610_nfc_probe,
838 .remove = vf610_nfc_remove,
839 };
840
841 module_platform_driver(vf610_nfc_driver);
842
843 MODULE_AUTHOR("Stefan Agner <stefan.agner@toradex.com>");
844 MODULE_DESCRIPTION("Freescale VF610/MPC5125 NFC MTD NAND driver");
845 MODULE_LICENSE("GPL");
846