1 /*
2 * Broadcom UniMAC MDIO bus controller driver
3 *
4 * Copyright (C) 2014-2017 Broadcom
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12 #include <linux/kernel.h>
13 #include <linux/phy.h>
14 #include <linux/platform_device.h>
15 #include <linux/sched.h>
16 #include <linux/module.h>
17 #include <linux/io.h>
18 #include <linux/delay.h>
19 #include <linux/clk.h>
20
21 #include <linux/of.h>
22 #include <linux/of_platform.h>
23 #include <linux/of_mdio.h>
24
25 #include <linux/platform_data/mdio-bcm-unimac.h>
26
27 #define MDIO_CMD 0x00
28 #define MDIO_START_BUSY (1 << 29)
29 #define MDIO_READ_FAIL (1 << 28)
30 #define MDIO_RD (2 << 26)
31 #define MDIO_WR (1 << 26)
32 #define MDIO_PMD_SHIFT 21
33 #define MDIO_PMD_MASK 0x1F
34 #define MDIO_REG_SHIFT 16
35 #define MDIO_REG_MASK 0x1F
36
37 #define MDIO_CFG 0x04
38 #define MDIO_C22 (1 << 0)
39 #define MDIO_C45 0
40 #define MDIO_CLK_DIV_SHIFT 4
41 #define MDIO_CLK_DIV_MASK 0x3F
42 #define MDIO_SUPP_PREAMBLE (1 << 12)
43
44 struct unimac_mdio_priv {
45 struct mii_bus *mii_bus;
46 void __iomem *base;
47 int (*wait_func) (void *wait_func_data);
48 void *wait_func_data;
49 struct clk *clk;
50 u32 clk_freq;
51 };
52
unimac_mdio_readl(struct unimac_mdio_priv * priv,u32 offset)53 static inline u32 unimac_mdio_readl(struct unimac_mdio_priv *priv, u32 offset)
54 {
55 /* MIPS chips strapped for BE will automagically configure the
56 * peripheral registers for CPU-native byte order.
57 */
58 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
59 return __raw_readl(priv->base + offset);
60 else
61 return readl_relaxed(priv->base + offset);
62 }
63
unimac_mdio_writel(struct unimac_mdio_priv * priv,u32 val,u32 offset)64 static inline void unimac_mdio_writel(struct unimac_mdio_priv *priv, u32 val,
65 u32 offset)
66 {
67 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
68 __raw_writel(val, priv->base + offset);
69 else
70 writel_relaxed(val, priv->base + offset);
71 }
72
unimac_mdio_start(struct unimac_mdio_priv * priv)73 static inline void unimac_mdio_start(struct unimac_mdio_priv *priv)
74 {
75 u32 reg;
76
77 reg = unimac_mdio_readl(priv, MDIO_CMD);
78 reg |= MDIO_START_BUSY;
79 unimac_mdio_writel(priv, reg, MDIO_CMD);
80 }
81
unimac_mdio_busy(struct unimac_mdio_priv * priv)82 static inline unsigned int unimac_mdio_busy(struct unimac_mdio_priv *priv)
83 {
84 return unimac_mdio_readl(priv, MDIO_CMD) & MDIO_START_BUSY;
85 }
86
unimac_mdio_poll(void * wait_func_data)87 static int unimac_mdio_poll(void *wait_func_data)
88 {
89 struct unimac_mdio_priv *priv = wait_func_data;
90 unsigned int timeout = 1000;
91
92 do {
93 if (!unimac_mdio_busy(priv))
94 return 0;
95
96 usleep_range(1000, 2000);
97 } while (--timeout);
98
99 if (!timeout)
100 return -ETIMEDOUT;
101
102 return 0;
103 }
104
unimac_mdio_read(struct mii_bus * bus,int phy_id,int reg)105 static int unimac_mdio_read(struct mii_bus *bus, int phy_id, int reg)
106 {
107 struct unimac_mdio_priv *priv = bus->priv;
108 int ret;
109 u32 cmd;
110
111 /* Prepare the read operation */
112 cmd = MDIO_RD | (phy_id << MDIO_PMD_SHIFT) | (reg << MDIO_REG_SHIFT);
113 unimac_mdio_writel(priv, cmd, MDIO_CMD);
114
115 /* Start MDIO transaction */
116 unimac_mdio_start(priv);
117
118 ret = priv->wait_func(priv->wait_func_data);
119 if (ret)
120 return ret;
121
122 cmd = unimac_mdio_readl(priv, MDIO_CMD);
123
124 /* Some broken devices are known not to release the line during
125 * turn-around, e.g: Broadcom BCM53125 external switches, so check for
126 * that condition here and ignore the MDIO controller read failure
127 * indication.
128 */
129 if (!(bus->phy_ignore_ta_mask & 1 << phy_id) && (cmd & MDIO_READ_FAIL))
130 return -EIO;
131
132 return cmd & 0xffff;
133 }
134
unimac_mdio_write(struct mii_bus * bus,int phy_id,int reg,u16 val)135 static int unimac_mdio_write(struct mii_bus *bus, int phy_id,
136 int reg, u16 val)
137 {
138 struct unimac_mdio_priv *priv = bus->priv;
139 u32 cmd;
140
141 /* Prepare the write operation */
142 cmd = MDIO_WR | (phy_id << MDIO_PMD_SHIFT) |
143 (reg << MDIO_REG_SHIFT) | (0xffff & val);
144 unimac_mdio_writel(priv, cmd, MDIO_CMD);
145
146 unimac_mdio_start(priv);
147
148 return priv->wait_func(priv->wait_func_data);
149 }
150
151 /* Workaround for integrated BCM7xxx Gigabit PHYs which have a problem with
152 * their internal MDIO management controller making them fail to successfully
153 * be read from or written to for the first transaction. We insert a dummy
154 * BMSR read here to make sure that phy_get_device() and get_phy_id() can
155 * correctly read the PHY MII_PHYSID1/2 registers and successfully register a
156 * PHY device for this peripheral.
157 *
158 * Once the PHY driver is registered, we can workaround subsequent reads from
159 * there (e.g: during system-wide power management).
160 *
161 * bus->reset is invoked before mdiobus_scan during mdiobus_register and is
162 * therefore the right location to stick that workaround. Since we do not want
163 * to read from non-existing PHYs, we either use bus->phy_mask or do a manual
164 * Device Tree scan to limit the search area.
165 */
unimac_mdio_reset(struct mii_bus * bus)166 static int unimac_mdio_reset(struct mii_bus *bus)
167 {
168 struct device_node *np = bus->dev.of_node;
169 struct device_node *child;
170 u32 read_mask = 0;
171 int addr;
172
173 if (!np) {
174 read_mask = ~bus->phy_mask;
175 } else {
176 for_each_available_child_of_node(np, child) {
177 addr = of_mdio_parse_addr(&bus->dev, child);
178 if (addr < 0)
179 continue;
180
181 read_mask |= 1 << addr;
182 }
183 }
184
185 for (addr = 0; addr < PHY_MAX_ADDR; addr++) {
186 if (read_mask & 1 << addr) {
187 dev_dbg(&bus->dev, "Workaround for PHY @ %d\n", addr);
188 mdiobus_read(bus, addr, MII_BMSR);
189 }
190 }
191
192 return 0;
193 }
194
unimac_mdio_clk_set(struct unimac_mdio_priv * priv)195 static void unimac_mdio_clk_set(struct unimac_mdio_priv *priv)
196 {
197 unsigned long rate;
198 u32 reg, div;
199
200 /* Keep the hardware default values */
201 if (!priv->clk_freq)
202 return;
203
204 if (!priv->clk)
205 rate = 250000000;
206 else
207 rate = clk_get_rate(priv->clk);
208
209 div = (rate / (2 * priv->clk_freq)) - 1;
210 if (div & ~MDIO_CLK_DIV_MASK) {
211 pr_warn("Incorrect MDIO clock frequency, ignoring\n");
212 return;
213 }
214
215 /* The MDIO clock is the reference clock (typicaly 250Mhz) divided by
216 * 2 x (MDIO_CLK_DIV + 1)
217 */
218 reg = unimac_mdio_readl(priv, MDIO_CFG);
219 reg &= ~(MDIO_CLK_DIV_MASK << MDIO_CLK_DIV_SHIFT);
220 reg |= div << MDIO_CLK_DIV_SHIFT;
221 unimac_mdio_writel(priv, reg, MDIO_CFG);
222 }
223
unimac_mdio_probe(struct platform_device * pdev)224 static int unimac_mdio_probe(struct platform_device *pdev)
225 {
226 struct unimac_mdio_pdata *pdata = pdev->dev.platform_data;
227 struct unimac_mdio_priv *priv;
228 struct device_node *np;
229 struct mii_bus *bus;
230 struct resource *r;
231 int ret;
232
233 np = pdev->dev.of_node;
234
235 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
236 if (!priv)
237 return -ENOMEM;
238
239 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
240
241 /* Just ioremap, as this MDIO block is usually integrated into an
242 * Ethernet MAC controller register range
243 */
244 priv->base = devm_ioremap(&pdev->dev, r->start, resource_size(r));
245 if (!priv->base) {
246 dev_err(&pdev->dev, "failed to remap register\n");
247 return -ENOMEM;
248 }
249
250 priv->clk = devm_clk_get(&pdev->dev, NULL);
251 if (PTR_ERR(priv->clk) == -EPROBE_DEFER)
252 return PTR_ERR(priv->clk);
253 else
254 priv->clk = NULL;
255
256 ret = clk_prepare_enable(priv->clk);
257 if (ret)
258 return ret;
259
260 if (of_property_read_u32(np, "clock-frequency", &priv->clk_freq))
261 priv->clk_freq = 0;
262
263 unimac_mdio_clk_set(priv);
264
265 priv->mii_bus = mdiobus_alloc();
266 if (!priv->mii_bus) {
267 ret = -ENOMEM;
268 goto out_clk_disable;
269 }
270
271 bus = priv->mii_bus;
272 bus->priv = priv;
273 if (pdata) {
274 bus->name = pdata->bus_name;
275 priv->wait_func = pdata->wait_func;
276 priv->wait_func_data = pdata->wait_func_data;
277 bus->phy_mask = ~pdata->phy_mask;
278 } else {
279 bus->name = "unimac MII bus";
280 priv->wait_func_data = priv;
281 priv->wait_func = unimac_mdio_poll;
282 }
283 bus->parent = &pdev->dev;
284 bus->read = unimac_mdio_read;
285 bus->write = unimac_mdio_write;
286 bus->reset = unimac_mdio_reset;
287 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-%d", pdev->name, pdev->id);
288
289 ret = of_mdiobus_register(bus, np);
290 if (ret) {
291 dev_err(&pdev->dev, "MDIO bus registration failed\n");
292 goto out_mdio_free;
293 }
294
295 platform_set_drvdata(pdev, priv);
296
297 dev_info(&pdev->dev, "Broadcom UniMAC MDIO bus at 0x%p\n", priv->base);
298
299 return 0;
300
301 out_mdio_free:
302 mdiobus_free(bus);
303 out_clk_disable:
304 clk_disable_unprepare(priv->clk);
305 return ret;
306 }
307
unimac_mdio_remove(struct platform_device * pdev)308 static int unimac_mdio_remove(struct platform_device *pdev)
309 {
310 struct unimac_mdio_priv *priv = platform_get_drvdata(pdev);
311
312 mdiobus_unregister(priv->mii_bus);
313 mdiobus_free(priv->mii_bus);
314 clk_disable_unprepare(priv->clk);
315
316 return 0;
317 }
318
unimac_mdio_suspend(struct device * d)319 static int __maybe_unused unimac_mdio_suspend(struct device *d)
320 {
321 struct unimac_mdio_priv *priv = dev_get_drvdata(d);
322
323 clk_disable_unprepare(priv->clk);
324
325 return 0;
326 }
327
unimac_mdio_resume(struct device * d)328 static int __maybe_unused unimac_mdio_resume(struct device *d)
329 {
330 struct unimac_mdio_priv *priv = dev_get_drvdata(d);
331 int ret;
332
333 ret = clk_prepare_enable(priv->clk);
334 if (ret)
335 return ret;
336
337 unimac_mdio_clk_set(priv);
338
339 return 0;
340 }
341
342 static SIMPLE_DEV_PM_OPS(unimac_mdio_pm_ops,
343 unimac_mdio_suspend, unimac_mdio_resume);
344
345 static const struct of_device_id unimac_mdio_ids[] = {
346 { .compatible = "brcm,genet-mdio-v5", },
347 { .compatible = "brcm,genet-mdio-v4", },
348 { .compatible = "brcm,genet-mdio-v3", },
349 { .compatible = "brcm,genet-mdio-v2", },
350 { .compatible = "brcm,genet-mdio-v1", },
351 { .compatible = "brcm,unimac-mdio", },
352 { /* sentinel */ },
353 };
354 MODULE_DEVICE_TABLE(of, unimac_mdio_ids);
355
356 static struct platform_driver unimac_mdio_driver = {
357 .driver = {
358 .name = UNIMAC_MDIO_DRV_NAME,
359 .of_match_table = unimac_mdio_ids,
360 .pm = &unimac_mdio_pm_ops,
361 },
362 .probe = unimac_mdio_probe,
363 .remove = unimac_mdio_remove,
364 };
365 module_platform_driver(unimac_mdio_driver);
366
367 MODULE_AUTHOR("Broadcom Corporation");
368 MODULE_DESCRIPTION("Broadcom UniMAC MDIO bus controller");
369 MODULE_LICENSE("GPL");
370 MODULE_ALIAS("platform:" UNIMAC_MDIO_DRV_NAME);
371