1 /*
2 * QUICC Engine GPIOs
3 *
4 * Copyright (c) MontaVista Software, Inc. 2008.
5 *
6 * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/spinlock.h>
17 #include <linux/err.h>
18 #include <linux/io.h>
19 #include <linux/of.h>
20 #include <linux/of_gpio.h>
21 #include <linux/gpio/driver.h>
22 /* FIXME: needed for gpio_to_chip() get rid of this */
23 #include <linux/gpio.h>
24 #include <linux/slab.h>
25 #include <linux/export.h>
26 #include <soc/fsl/qe/qe.h>
27
28 struct qe_gpio_chip {
29 struct of_mm_gpio_chip mm_gc;
30 spinlock_t lock;
31
32 unsigned long pin_flags[QE_PIO_PINS];
33 #define QE_PIN_REQUESTED 0
34
35 /* shadowed data register to clear/set bits safely */
36 u32 cpdata;
37
38 /* saved_regs used to restore dedicated functions */
39 struct qe_pio_regs saved_regs;
40 };
41
qe_gpio_save_regs(struct of_mm_gpio_chip * mm_gc)42 static void qe_gpio_save_regs(struct of_mm_gpio_chip *mm_gc)
43 {
44 struct qe_gpio_chip *qe_gc =
45 container_of(mm_gc, struct qe_gpio_chip, mm_gc);
46 struct qe_pio_regs __iomem *regs = mm_gc->regs;
47
48 qe_gc->cpdata = in_be32(®s->cpdata);
49 qe_gc->saved_regs.cpdata = qe_gc->cpdata;
50 qe_gc->saved_regs.cpdir1 = in_be32(®s->cpdir1);
51 qe_gc->saved_regs.cpdir2 = in_be32(®s->cpdir2);
52 qe_gc->saved_regs.cppar1 = in_be32(®s->cppar1);
53 qe_gc->saved_regs.cppar2 = in_be32(®s->cppar2);
54 qe_gc->saved_regs.cpodr = in_be32(®s->cpodr);
55 }
56
qe_gpio_get(struct gpio_chip * gc,unsigned int gpio)57 static int qe_gpio_get(struct gpio_chip *gc, unsigned int gpio)
58 {
59 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
60 struct qe_pio_regs __iomem *regs = mm_gc->regs;
61 u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio);
62
63 return !!(in_be32(®s->cpdata) & pin_mask);
64 }
65
qe_gpio_set(struct gpio_chip * gc,unsigned int gpio,int val)66 static void qe_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
67 {
68 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
69 struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);
70 struct qe_pio_regs __iomem *regs = mm_gc->regs;
71 unsigned long flags;
72 u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio);
73
74 spin_lock_irqsave(&qe_gc->lock, flags);
75
76 if (val)
77 qe_gc->cpdata |= pin_mask;
78 else
79 qe_gc->cpdata &= ~pin_mask;
80
81 out_be32(®s->cpdata, qe_gc->cpdata);
82
83 spin_unlock_irqrestore(&qe_gc->lock, flags);
84 }
85
qe_gpio_dir_in(struct gpio_chip * gc,unsigned int gpio)86 static int qe_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
87 {
88 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
89 struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);
90 unsigned long flags;
91
92 spin_lock_irqsave(&qe_gc->lock, flags);
93
94 __par_io_config_pin(mm_gc->regs, gpio, QE_PIO_DIR_IN, 0, 0, 0);
95
96 spin_unlock_irqrestore(&qe_gc->lock, flags);
97
98 return 0;
99 }
100
qe_gpio_dir_out(struct gpio_chip * gc,unsigned int gpio,int val)101 static int qe_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
102 {
103 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
104 struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);
105 unsigned long flags;
106
107 qe_gpio_set(gc, gpio, val);
108
109 spin_lock_irqsave(&qe_gc->lock, flags);
110
111 __par_io_config_pin(mm_gc->regs, gpio, QE_PIO_DIR_OUT, 0, 0, 0);
112
113 spin_unlock_irqrestore(&qe_gc->lock, flags);
114
115 return 0;
116 }
117
118 struct qe_pin {
119 /*
120 * The qe_gpio_chip name is unfortunate, we should change that to
121 * something like qe_pio_controller. Someday.
122 */
123 struct qe_gpio_chip *controller;
124 int num;
125 };
126
127 /**
128 * qe_pin_request - Request a QE pin
129 * @np: device node to get a pin from
130 * @index: index of a pin in the device tree
131 * Context: non-atomic
132 *
133 * This function return qe_pin so that you could use it with the rest of
134 * the QE Pin Multiplexing API.
135 */
qe_pin_request(struct device_node * np,int index)136 struct qe_pin *qe_pin_request(struct device_node *np, int index)
137 {
138 struct qe_pin *qe_pin;
139 struct gpio_chip *gc;
140 struct of_mm_gpio_chip *mm_gc;
141 struct qe_gpio_chip *qe_gc;
142 int err;
143 unsigned long flags;
144
145 qe_pin = kzalloc(sizeof(*qe_pin), GFP_KERNEL);
146 if (!qe_pin) {
147 pr_debug("%s: can't allocate memory\n", __func__);
148 return ERR_PTR(-ENOMEM);
149 }
150
151 err = of_get_gpio(np, index);
152 if (err < 0)
153 goto err0;
154 gc = gpio_to_chip(err);
155 if (WARN_ON(!gc)) {
156 err = -ENODEV;
157 goto err0;
158 }
159
160 if (!of_device_is_compatible(gc->of_node, "fsl,mpc8323-qe-pario-bank")) {
161 pr_debug("%s: tried to get a non-qe pin\n", __func__);
162 err = -EINVAL;
163 goto err0;
164 }
165
166 mm_gc = to_of_mm_gpio_chip(gc);
167 qe_gc = gpiochip_get_data(gc);
168
169 spin_lock_irqsave(&qe_gc->lock, flags);
170
171 err -= gc->base;
172 if (test_and_set_bit(QE_PIN_REQUESTED, &qe_gc->pin_flags[err]) == 0) {
173 qe_pin->controller = qe_gc;
174 qe_pin->num = err;
175 err = 0;
176 } else {
177 err = -EBUSY;
178 }
179
180 spin_unlock_irqrestore(&qe_gc->lock, flags);
181
182 if (!err)
183 return qe_pin;
184 err0:
185 kfree(qe_pin);
186 pr_debug("%s failed with status %d\n", __func__, err);
187 return ERR_PTR(err);
188 }
189 EXPORT_SYMBOL(qe_pin_request);
190
191 /**
192 * qe_pin_free - Free a pin
193 * @qe_pin: pointer to the qe_pin structure
194 * Context: any
195 *
196 * This function frees the qe_pin structure and makes a pin available
197 * for further qe_pin_request() calls.
198 */
qe_pin_free(struct qe_pin * qe_pin)199 void qe_pin_free(struct qe_pin *qe_pin)
200 {
201 struct qe_gpio_chip *qe_gc = qe_pin->controller;
202 unsigned long flags;
203 const int pin = qe_pin->num;
204
205 spin_lock_irqsave(&qe_gc->lock, flags);
206 test_and_clear_bit(QE_PIN_REQUESTED, &qe_gc->pin_flags[pin]);
207 spin_unlock_irqrestore(&qe_gc->lock, flags);
208
209 kfree(qe_pin);
210 }
211 EXPORT_SYMBOL(qe_pin_free);
212
213 /**
214 * qe_pin_set_dedicated - Revert a pin to a dedicated peripheral function mode
215 * @qe_pin: pointer to the qe_pin structure
216 * Context: any
217 *
218 * This function resets a pin to a dedicated peripheral function that
219 * has been set up by the firmware.
220 */
qe_pin_set_dedicated(struct qe_pin * qe_pin)221 void qe_pin_set_dedicated(struct qe_pin *qe_pin)
222 {
223 struct qe_gpio_chip *qe_gc = qe_pin->controller;
224 struct qe_pio_regs __iomem *regs = qe_gc->mm_gc.regs;
225 struct qe_pio_regs *sregs = &qe_gc->saved_regs;
226 int pin = qe_pin->num;
227 u32 mask1 = 1 << (QE_PIO_PINS - (pin + 1));
228 u32 mask2 = 0x3 << (QE_PIO_PINS - (pin % (QE_PIO_PINS / 2) + 1) * 2);
229 bool second_reg = pin > (QE_PIO_PINS / 2) - 1;
230 unsigned long flags;
231
232 spin_lock_irqsave(&qe_gc->lock, flags);
233
234 if (second_reg) {
235 clrsetbits_be32(®s->cpdir2, mask2, sregs->cpdir2 & mask2);
236 clrsetbits_be32(®s->cppar2, mask2, sregs->cppar2 & mask2);
237 } else {
238 clrsetbits_be32(®s->cpdir1, mask2, sregs->cpdir1 & mask2);
239 clrsetbits_be32(®s->cppar1, mask2, sregs->cppar1 & mask2);
240 }
241
242 if (sregs->cpdata & mask1)
243 qe_gc->cpdata |= mask1;
244 else
245 qe_gc->cpdata &= ~mask1;
246
247 out_be32(®s->cpdata, qe_gc->cpdata);
248 clrsetbits_be32(®s->cpodr, mask1, sregs->cpodr & mask1);
249
250 spin_unlock_irqrestore(&qe_gc->lock, flags);
251 }
252 EXPORT_SYMBOL(qe_pin_set_dedicated);
253
254 /**
255 * qe_pin_set_gpio - Set a pin to the GPIO mode
256 * @qe_pin: pointer to the qe_pin structure
257 * Context: any
258 *
259 * This function sets a pin to the GPIO mode.
260 */
qe_pin_set_gpio(struct qe_pin * qe_pin)261 void qe_pin_set_gpio(struct qe_pin *qe_pin)
262 {
263 struct qe_gpio_chip *qe_gc = qe_pin->controller;
264 struct qe_pio_regs __iomem *regs = qe_gc->mm_gc.regs;
265 unsigned long flags;
266
267 spin_lock_irqsave(&qe_gc->lock, flags);
268
269 /* Let's make it input by default, GPIO API is able to change that. */
270 __par_io_config_pin(regs, qe_pin->num, QE_PIO_DIR_IN, 0, 0, 0);
271
272 spin_unlock_irqrestore(&qe_gc->lock, flags);
273 }
274 EXPORT_SYMBOL(qe_pin_set_gpio);
275
qe_add_gpiochips(void)276 static int __init qe_add_gpiochips(void)
277 {
278 struct device_node *np;
279
280 for_each_compatible_node(np, NULL, "fsl,mpc8323-qe-pario-bank") {
281 int ret;
282 struct qe_gpio_chip *qe_gc;
283 struct of_mm_gpio_chip *mm_gc;
284 struct gpio_chip *gc;
285
286 qe_gc = kzalloc(sizeof(*qe_gc), GFP_KERNEL);
287 if (!qe_gc) {
288 ret = -ENOMEM;
289 goto err;
290 }
291
292 spin_lock_init(&qe_gc->lock);
293
294 mm_gc = &qe_gc->mm_gc;
295 gc = &mm_gc->gc;
296
297 mm_gc->save_regs = qe_gpio_save_regs;
298 gc->ngpio = QE_PIO_PINS;
299 gc->direction_input = qe_gpio_dir_in;
300 gc->direction_output = qe_gpio_dir_out;
301 gc->get = qe_gpio_get;
302 gc->set = qe_gpio_set;
303
304 ret = of_mm_gpiochip_add_data(np, mm_gc, qe_gc);
305 if (ret)
306 goto err;
307 continue;
308 err:
309 pr_err("%pOF: registration failed with status %d\n",
310 np, ret);
311 kfree(qe_gc);
312 /* try others anyway */
313 }
314 return 0;
315 }
316 arch_initcall(qe_add_gpiochips);
317