1 /*
2 * Probe module for 8250/16550-type Exar chips PCI serial ports.
3 *
4 * Based on drivers/tty/serial/8250/8250_pci.c,
5 *
6 * Copyright (C) 2017 Sudip Mukherjee, All Rights Reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License.
11 */
12 #include <linux/acpi.h>
13 #include <linux/dmi.h>
14 #include <linux/io.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/pci.h>
18 #include <linux/property.h>
19 #include <linux/serial_core.h>
20 #include <linux/serial_reg.h>
21 #include <linux/slab.h>
22 #include <linux/string.h>
23 #include <linux/tty.h>
24 #include <linux/8250_pci.h>
25
26 #include <asm/byteorder.h>
27
28 #include "8250.h"
29
30 #define PCI_DEVICE_ID_ACCES_COM_2S 0x1052
31 #define PCI_DEVICE_ID_ACCES_COM_4S 0x105d
32 #define PCI_DEVICE_ID_ACCES_COM_8S 0x106c
33 #define PCI_DEVICE_ID_ACCES_COM232_8 0x10a8
34 #define PCI_DEVICE_ID_ACCES_COM_2SM 0x10d2
35 #define PCI_DEVICE_ID_ACCES_COM_4SM 0x10db
36 #define PCI_DEVICE_ID_ACCES_COM_8SM 0x10ea
37
38 #define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002
39 #define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004
40 #define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a
41 #define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b
42 #define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020
43 #define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021
44 #define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022
45 #define PCI_DEVICE_ID_EXAR_XR17V4358 0x4358
46 #define PCI_DEVICE_ID_EXAR_XR17V8358 0x8358
47
48 #define UART_EXAR_INT0 0x80
49 #define UART_EXAR_8XMODE 0x88 /* 8X sampling rate select */
50
51 #define UART_EXAR_FCTR 0x08 /* Feature Control Register */
52 #define UART_FCTR_EXAR_IRDA 0x10 /* IrDa data encode select */
53 #define UART_FCTR_EXAR_485 0x20 /* Auto 485 half duplex dir ctl */
54 #define UART_FCTR_EXAR_TRGA 0x00 /* FIFO trigger table A */
55 #define UART_FCTR_EXAR_TRGB 0x60 /* FIFO trigger table B */
56 #define UART_FCTR_EXAR_TRGC 0x80 /* FIFO trigger table C */
57 #define UART_FCTR_EXAR_TRGD 0xc0 /* FIFO trigger table D programmable */
58
59 #define UART_EXAR_TXTRG 0x0a /* Tx FIFO trigger level write-only */
60 #define UART_EXAR_RXTRG 0x0b /* Rx FIFO trigger level write-only */
61
62 #define UART_EXAR_MPIOINT_7_0 0x8f /* MPIOINT[7:0] */
63 #define UART_EXAR_MPIOLVL_7_0 0x90 /* MPIOLVL[7:0] */
64 #define UART_EXAR_MPIO3T_7_0 0x91 /* MPIO3T[7:0] */
65 #define UART_EXAR_MPIOINV_7_0 0x92 /* MPIOINV[7:0] */
66 #define UART_EXAR_MPIOSEL_7_0 0x93 /* MPIOSEL[7:0] */
67 #define UART_EXAR_MPIOOD_7_0 0x94 /* MPIOOD[7:0] */
68 #define UART_EXAR_MPIOINT_15_8 0x95 /* MPIOINT[15:8] */
69 #define UART_EXAR_MPIOLVL_15_8 0x96 /* MPIOLVL[15:8] */
70 #define UART_EXAR_MPIO3T_15_8 0x97 /* MPIO3T[15:8] */
71 #define UART_EXAR_MPIOINV_15_8 0x98 /* MPIOINV[15:8] */
72 #define UART_EXAR_MPIOSEL_15_8 0x99 /* MPIOSEL[15:8] */
73 #define UART_EXAR_MPIOOD_15_8 0x9a /* MPIOOD[15:8] */
74
75 #define UART_EXAR_RS485_DLY(x) ((x) << 4)
76
77 /*
78 * IOT2040 MPIO wiring semantics:
79 *
80 * MPIO Port Function
81 * ---- ---- --------
82 * 0 2 Mode bit 0
83 * 1 2 Mode bit 1
84 * 2 2 Terminate bus
85 * 3 - <reserved>
86 * 4 3 Mode bit 0
87 * 5 3 Mode bit 1
88 * 6 3 Terminate bus
89 * 7 - <reserved>
90 * 8 2 Enable
91 * 9 3 Enable
92 * 10 - Red LED
93 * 11..15 - <unused>
94 */
95
96 /* IOT2040 MPIOs 0..7 */
97 #define IOT2040_UART_MODE_RS232 0x01
98 #define IOT2040_UART_MODE_RS485 0x02
99 #define IOT2040_UART_MODE_RS422 0x03
100 #define IOT2040_UART_TERMINATE_BUS 0x04
101
102 #define IOT2040_UART1_MASK 0x0f
103 #define IOT2040_UART2_SHIFT 4
104
105 #define IOT2040_UARTS_DEFAULT_MODE 0x11 /* both RS232 */
106 #define IOT2040_UARTS_GPIO_LO_MODE 0x88 /* reserved pins as input */
107
108 /* IOT2040 MPIOs 8..15 */
109 #define IOT2040_UARTS_ENABLE 0x03
110 #define IOT2040_UARTS_GPIO_HI_MODE 0xF8 /* enable & LED as outputs */
111
112 struct exar8250;
113
114 struct exar8250_platform {
115 int (*rs485_config)(struct uart_port *, struct serial_rs485 *);
116 int (*register_gpio)(struct pci_dev *, struct uart_8250_port *);
117 };
118
119 /**
120 * struct exar8250_board - board information
121 * @num_ports: number of serial ports
122 * @reg_shift: describes UART register mapping in PCI memory
123 */
124 struct exar8250_board {
125 unsigned int num_ports;
126 unsigned int reg_shift;
127 bool has_slave;
128 int (*setup)(struct exar8250 *, struct pci_dev *,
129 struct uart_8250_port *, int);
130 void (*exit)(struct pci_dev *pcidev);
131 };
132
133 struct exar8250 {
134 unsigned int nr;
135 struct exar8250_board *board;
136 void __iomem *virt;
137 int line[0];
138 };
139
default_setup(struct exar8250 * priv,struct pci_dev * pcidev,int idx,unsigned int offset,struct uart_8250_port * port)140 static int default_setup(struct exar8250 *priv, struct pci_dev *pcidev,
141 int idx, unsigned int offset,
142 struct uart_8250_port *port)
143 {
144 const struct exar8250_board *board = priv->board;
145 unsigned int bar = 0;
146
147 port->port.iotype = UPIO_MEM;
148 port->port.mapbase = pci_resource_start(pcidev, bar) + offset;
149 port->port.membase = priv->virt + offset;
150 port->port.regshift = board->reg_shift;
151
152 return 0;
153 }
154
155 static int
pci_fastcom335_setup(struct exar8250 * priv,struct pci_dev * pcidev,struct uart_8250_port * port,int idx)156 pci_fastcom335_setup(struct exar8250 *priv, struct pci_dev *pcidev,
157 struct uart_8250_port *port, int idx)
158 {
159 unsigned int offset = idx * 0x200;
160 unsigned int baud = 1843200;
161 u8 __iomem *p;
162 int err;
163
164 port->port.uartclk = baud * 16;
165
166 err = default_setup(priv, pcidev, idx, offset, port);
167 if (err)
168 return err;
169
170 p = port->port.membase;
171
172 writeb(0x00, p + UART_EXAR_8XMODE);
173 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
174 writeb(32, p + UART_EXAR_TXTRG);
175 writeb(32, p + UART_EXAR_RXTRG);
176
177 /*
178 * Setup Multipurpose Input/Output pins.
179 */
180 if (idx == 0) {
181 switch (pcidev->device) {
182 case PCI_DEVICE_ID_COMMTECH_4222PCI335:
183 case PCI_DEVICE_ID_COMMTECH_4224PCI335:
184 writeb(0x78, p + UART_EXAR_MPIOLVL_7_0);
185 writeb(0x00, p + UART_EXAR_MPIOINV_7_0);
186 writeb(0x00, p + UART_EXAR_MPIOSEL_7_0);
187 break;
188 case PCI_DEVICE_ID_COMMTECH_2324PCI335:
189 case PCI_DEVICE_ID_COMMTECH_2328PCI335:
190 writeb(0x00, p + UART_EXAR_MPIOLVL_7_0);
191 writeb(0xc0, p + UART_EXAR_MPIOINV_7_0);
192 writeb(0xc0, p + UART_EXAR_MPIOSEL_7_0);
193 break;
194 }
195 writeb(0x00, p + UART_EXAR_MPIOINT_7_0);
196 writeb(0x00, p + UART_EXAR_MPIO3T_7_0);
197 writeb(0x00, p + UART_EXAR_MPIOOD_7_0);
198 }
199
200 return 0;
201 }
202
203 static int
pci_connect_tech_setup(struct exar8250 * priv,struct pci_dev * pcidev,struct uart_8250_port * port,int idx)204 pci_connect_tech_setup(struct exar8250 *priv, struct pci_dev *pcidev,
205 struct uart_8250_port *port, int idx)
206 {
207 unsigned int offset = idx * 0x200;
208 unsigned int baud = 1843200;
209
210 port->port.uartclk = baud * 16;
211 return default_setup(priv, pcidev, idx, offset, port);
212 }
213
214 static int
pci_xr17c154_setup(struct exar8250 * priv,struct pci_dev * pcidev,struct uart_8250_port * port,int idx)215 pci_xr17c154_setup(struct exar8250 *priv, struct pci_dev *pcidev,
216 struct uart_8250_port *port, int idx)
217 {
218 unsigned int offset = idx * 0x200;
219 unsigned int baud = 921600;
220
221 port->port.uartclk = baud * 16;
222 return default_setup(priv, pcidev, idx, offset, port);
223 }
224
setup_gpio(struct pci_dev * pcidev,u8 __iomem * p)225 static void setup_gpio(struct pci_dev *pcidev, u8 __iomem *p)
226 {
227 /*
228 * The Commtech adapters required the MPIOs to be driven low. The Exar
229 * devices will export them as GPIOs, so we pre-configure them safely
230 * as inputs.
231 */
232 u8 dir = pcidev->vendor == PCI_VENDOR_ID_EXAR ? 0xff : 0x00;
233
234 writeb(0x00, p + UART_EXAR_MPIOINT_7_0);
235 writeb(0x00, p + UART_EXAR_MPIOLVL_7_0);
236 writeb(0x00, p + UART_EXAR_MPIO3T_7_0);
237 writeb(0x00, p + UART_EXAR_MPIOINV_7_0);
238 writeb(dir, p + UART_EXAR_MPIOSEL_7_0);
239 writeb(0x00, p + UART_EXAR_MPIOOD_7_0);
240 writeb(0x00, p + UART_EXAR_MPIOINT_15_8);
241 writeb(0x00, p + UART_EXAR_MPIOLVL_15_8);
242 writeb(0x00, p + UART_EXAR_MPIO3T_15_8);
243 writeb(0x00, p + UART_EXAR_MPIOINV_15_8);
244 writeb(dir, p + UART_EXAR_MPIOSEL_15_8);
245 writeb(0x00, p + UART_EXAR_MPIOOD_15_8);
246 }
247
248 static void *
__xr17v35x_register_gpio(struct pci_dev * pcidev,const struct property_entry * properties)249 __xr17v35x_register_gpio(struct pci_dev *pcidev,
250 const struct property_entry *properties)
251 {
252 struct platform_device *pdev;
253
254 pdev = platform_device_alloc("gpio_exar", PLATFORM_DEVID_AUTO);
255 if (!pdev)
256 return NULL;
257
258 pdev->dev.parent = &pcidev->dev;
259 ACPI_COMPANION_SET(&pdev->dev, ACPI_COMPANION(&pcidev->dev));
260
261 if (platform_device_add_properties(pdev, properties) < 0 ||
262 platform_device_add(pdev) < 0) {
263 platform_device_put(pdev);
264 return NULL;
265 }
266
267 return pdev;
268 }
269
270 static const struct property_entry exar_gpio_properties[] = {
271 PROPERTY_ENTRY_U32("exar,first-pin", 0),
272 PROPERTY_ENTRY_U32("ngpios", 16),
273 { }
274 };
275
xr17v35x_register_gpio(struct pci_dev * pcidev,struct uart_8250_port * port)276 static int xr17v35x_register_gpio(struct pci_dev *pcidev,
277 struct uart_8250_port *port)
278 {
279 if (pcidev->vendor == PCI_VENDOR_ID_EXAR)
280 port->port.private_data =
281 __xr17v35x_register_gpio(pcidev, exar_gpio_properties);
282
283 return 0;
284 }
285
286 static const struct exar8250_platform exar8250_default_platform = {
287 .register_gpio = xr17v35x_register_gpio,
288 };
289
iot2040_rs485_config(struct uart_port * port,struct serial_rs485 * rs485)290 static int iot2040_rs485_config(struct uart_port *port,
291 struct serial_rs485 *rs485)
292 {
293 bool is_rs485 = !!(rs485->flags & SER_RS485_ENABLED);
294 u8 __iomem *p = port->membase;
295 u8 mask = IOT2040_UART1_MASK;
296 u8 mode, value;
297
298 if (is_rs485) {
299 if (rs485->flags & SER_RS485_RX_DURING_TX)
300 mode = IOT2040_UART_MODE_RS422;
301 else
302 mode = IOT2040_UART_MODE_RS485;
303
304 if (rs485->flags & SER_RS485_TERMINATE_BUS)
305 mode |= IOT2040_UART_TERMINATE_BUS;
306 } else {
307 mode = IOT2040_UART_MODE_RS232;
308 }
309
310 if (port->line == 3) {
311 mask <<= IOT2040_UART2_SHIFT;
312 mode <<= IOT2040_UART2_SHIFT;
313 }
314
315 value = readb(p + UART_EXAR_MPIOLVL_7_0);
316 value &= ~mask;
317 value |= mode;
318 writeb(value, p + UART_EXAR_MPIOLVL_7_0);
319
320 value = readb(p + UART_EXAR_FCTR);
321 if (is_rs485)
322 value |= UART_FCTR_EXAR_485;
323 else
324 value &= ~UART_FCTR_EXAR_485;
325 writeb(value, p + UART_EXAR_FCTR);
326
327 if (is_rs485)
328 writeb(UART_EXAR_RS485_DLY(4), p + UART_MSR);
329
330 port->rs485 = *rs485;
331
332 return 0;
333 }
334
335 static const struct property_entry iot2040_gpio_properties[] = {
336 PROPERTY_ENTRY_U32("exar,first-pin", 10),
337 PROPERTY_ENTRY_U32("ngpios", 1),
338 { }
339 };
340
iot2040_register_gpio(struct pci_dev * pcidev,struct uart_8250_port * port)341 static int iot2040_register_gpio(struct pci_dev *pcidev,
342 struct uart_8250_port *port)
343 {
344 u8 __iomem *p = port->port.membase;
345
346 writeb(IOT2040_UARTS_DEFAULT_MODE, p + UART_EXAR_MPIOLVL_7_0);
347 writeb(IOT2040_UARTS_GPIO_LO_MODE, p + UART_EXAR_MPIOSEL_7_0);
348 writeb(IOT2040_UARTS_ENABLE, p + UART_EXAR_MPIOLVL_15_8);
349 writeb(IOT2040_UARTS_GPIO_HI_MODE, p + UART_EXAR_MPIOSEL_15_8);
350
351 port->port.private_data =
352 __xr17v35x_register_gpio(pcidev, iot2040_gpio_properties);
353
354 return 0;
355 }
356
357 static const struct exar8250_platform iot2040_platform = {
358 .rs485_config = iot2040_rs485_config,
359 .register_gpio = iot2040_register_gpio,
360 };
361
362 static const struct dmi_system_id exar_platforms[] = {
363 {
364 .matches = {
365 DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"),
366 DMI_EXACT_MATCH(DMI_BOARD_ASSET_TAG,
367 "6ES7647-0AA00-1YA2"),
368 },
369 .driver_data = (void *)&iot2040_platform,
370 },
371 {}
372 };
373
374 static int
pci_xr17v35x_setup(struct exar8250 * priv,struct pci_dev * pcidev,struct uart_8250_port * port,int idx)375 pci_xr17v35x_setup(struct exar8250 *priv, struct pci_dev *pcidev,
376 struct uart_8250_port *port, int idx)
377 {
378 const struct exar8250_board *board = priv->board;
379 const struct exar8250_platform *platform;
380 const struct dmi_system_id *dmi_match;
381 unsigned int offset = idx * 0x400;
382 unsigned int baud = 7812500;
383 u8 __iomem *p;
384 int ret;
385
386 dmi_match = dmi_first_match(exar_platforms);
387 if (dmi_match)
388 platform = dmi_match->driver_data;
389 else
390 platform = &exar8250_default_platform;
391
392 port->port.uartclk = baud * 16;
393 port->port.rs485_config = platform->rs485_config;
394
395 /*
396 * Setup the uart clock for the devices on expansion slot to
397 * half the clock speed of the main chip (which is 125MHz)
398 */
399 if (board->has_slave && idx >= 8)
400 port->port.uartclk /= 2;
401
402 ret = default_setup(priv, pcidev, idx, offset, port);
403 if (ret)
404 return ret;
405
406 p = port->port.membase;
407
408 writeb(0x00, p + UART_EXAR_8XMODE);
409 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
410 writeb(128, p + UART_EXAR_TXTRG);
411 writeb(128, p + UART_EXAR_RXTRG);
412
413 if (idx == 0) {
414 /* Setup Multipurpose Input/Output pins. */
415 setup_gpio(pcidev, p);
416
417 ret = platform->register_gpio(pcidev, port);
418 }
419
420 return ret;
421 }
422
pci_xr17v35x_exit(struct pci_dev * pcidev)423 static void pci_xr17v35x_exit(struct pci_dev *pcidev)
424 {
425 struct exar8250 *priv = pci_get_drvdata(pcidev);
426 struct uart_8250_port *port = serial8250_get_port(priv->line[0]);
427 struct platform_device *pdev = port->port.private_data;
428
429 platform_device_unregister(pdev);
430 port->port.private_data = NULL;
431 }
432
433 /*
434 * These Exar UARTs have an extra interrupt indicator that could fire for a
435 * few interrupts that are not presented/cleared through IIR. One of which is
436 * a wakeup interrupt when coming out of sleep. These interrupts are only
437 * cleared by reading global INT0 or INT1 registers as interrupts are
438 * associated with channel 0. The INT[3:0] registers _are_ accessible from each
439 * channel's address space, but for the sake of bus efficiency we register a
440 * dedicated handler at the PCI device level to handle them.
441 */
exar_misc_handler(int irq,void * data)442 static irqreturn_t exar_misc_handler(int irq, void *data)
443 {
444 struct exar8250 *priv = data;
445
446 /* Clear all PCI interrupts by reading INT0. No effect on IIR */
447 readb(priv->virt + UART_EXAR_INT0);
448
449 /* Clear INT0 for Expansion Interface slave ports, too */
450 if (priv->board->num_ports > 8)
451 readb(priv->virt + 0x2000 + UART_EXAR_INT0);
452
453 return IRQ_HANDLED;
454 }
455
456 static int
exar_pci_probe(struct pci_dev * pcidev,const struct pci_device_id * ent)457 exar_pci_probe(struct pci_dev *pcidev, const struct pci_device_id *ent)
458 {
459 unsigned int nr_ports, i, bar = 0, maxnr;
460 struct exar8250_board *board;
461 struct uart_8250_port uart;
462 struct exar8250 *priv;
463 int rc;
464
465 board = (struct exar8250_board *)ent->driver_data;
466 if (!board)
467 return -EINVAL;
468
469 rc = pcim_enable_device(pcidev);
470 if (rc)
471 return rc;
472
473 maxnr = pci_resource_len(pcidev, bar) >> (board->reg_shift + 3);
474
475 nr_ports = board->num_ports ? board->num_ports : pcidev->device & 0x0f;
476
477 priv = devm_kzalloc(&pcidev->dev, sizeof(*priv) +
478 sizeof(unsigned int) * nr_ports,
479 GFP_KERNEL);
480 if (!priv)
481 return -ENOMEM;
482
483 priv->board = board;
484 priv->virt = pcim_iomap(pcidev, bar, 0);
485 if (!priv->virt)
486 return -ENOMEM;
487
488 pci_set_master(pcidev);
489
490 rc = pci_alloc_irq_vectors(pcidev, 1, 1, PCI_IRQ_ALL_TYPES);
491 if (rc < 0)
492 return rc;
493
494 memset(&uart, 0, sizeof(uart));
495 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ
496 | UPF_EXAR_EFR;
497 uart.port.irq = pci_irq_vector(pcidev, 0);
498 uart.port.dev = &pcidev->dev;
499
500 rc = devm_request_irq(&pcidev->dev, uart.port.irq, exar_misc_handler,
501 IRQF_SHARED, "exar_uart", priv);
502 if (rc)
503 return rc;
504
505 for (i = 0; i < nr_ports && i < maxnr; i++) {
506 rc = board->setup(priv, pcidev, &uart, i);
507 if (rc) {
508 dev_err(&pcidev->dev, "Failed to setup port %u\n", i);
509 break;
510 }
511
512 dev_dbg(&pcidev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
513 uart.port.iobase, uart.port.irq, uart.port.iotype);
514
515 priv->line[i] = serial8250_register_8250_port(&uart);
516 if (priv->line[i] < 0) {
517 dev_err(&pcidev->dev,
518 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
519 uart.port.iobase, uart.port.irq,
520 uart.port.iotype, priv->line[i]);
521 break;
522 }
523 }
524 priv->nr = i;
525 pci_set_drvdata(pcidev, priv);
526 return 0;
527 }
528
exar_pci_remove(struct pci_dev * pcidev)529 static void exar_pci_remove(struct pci_dev *pcidev)
530 {
531 struct exar8250 *priv = pci_get_drvdata(pcidev);
532 unsigned int i;
533
534 for (i = 0; i < priv->nr; i++)
535 serial8250_unregister_port(priv->line[i]);
536
537 if (priv->board->exit)
538 priv->board->exit(pcidev);
539 }
540
exar_suspend(struct device * dev)541 static int __maybe_unused exar_suspend(struct device *dev)
542 {
543 struct pci_dev *pcidev = to_pci_dev(dev);
544 struct exar8250 *priv = pci_get_drvdata(pcidev);
545 unsigned int i;
546
547 for (i = 0; i < priv->nr; i++)
548 if (priv->line[i] >= 0)
549 serial8250_suspend_port(priv->line[i]);
550
551 /* Ensure that every init quirk is properly torn down */
552 if (priv->board->exit)
553 priv->board->exit(pcidev);
554
555 return 0;
556 }
557
exar_resume(struct device * dev)558 static int __maybe_unused exar_resume(struct device *dev)
559 {
560 struct pci_dev *pcidev = to_pci_dev(dev);
561 struct exar8250 *priv = pci_get_drvdata(pcidev);
562 unsigned int i;
563
564 for (i = 0; i < priv->nr; i++)
565 if (priv->line[i] >= 0)
566 serial8250_resume_port(priv->line[i]);
567
568 return 0;
569 }
570
571 static SIMPLE_DEV_PM_OPS(exar_pci_pm, exar_suspend, exar_resume);
572
573 static const struct exar8250_board acces_com_2x = {
574 .num_ports = 2,
575 .setup = pci_xr17c154_setup,
576 };
577
578 static const struct exar8250_board acces_com_4x = {
579 .num_ports = 4,
580 .setup = pci_xr17c154_setup,
581 };
582
583 static const struct exar8250_board acces_com_8x = {
584 .num_ports = 8,
585 .setup = pci_xr17c154_setup,
586 };
587
588
589 static const struct exar8250_board pbn_fastcom335_2 = {
590 .num_ports = 2,
591 .setup = pci_fastcom335_setup,
592 };
593
594 static const struct exar8250_board pbn_fastcom335_4 = {
595 .num_ports = 4,
596 .setup = pci_fastcom335_setup,
597 };
598
599 static const struct exar8250_board pbn_fastcom335_8 = {
600 .num_ports = 8,
601 .setup = pci_fastcom335_setup,
602 };
603
604 static const struct exar8250_board pbn_connect = {
605 .setup = pci_connect_tech_setup,
606 };
607
608 static const struct exar8250_board pbn_exar_ibm_saturn = {
609 .num_ports = 1,
610 .setup = pci_xr17c154_setup,
611 };
612
613 static const struct exar8250_board pbn_exar_XR17C15x = {
614 .setup = pci_xr17c154_setup,
615 };
616
617 static const struct exar8250_board pbn_exar_XR17V35x = {
618 .setup = pci_xr17v35x_setup,
619 .exit = pci_xr17v35x_exit,
620 };
621
622 static const struct exar8250_board pbn_exar_XR17V4358 = {
623 .num_ports = 12,
624 .has_slave = true,
625 .setup = pci_xr17v35x_setup,
626 .exit = pci_xr17v35x_exit,
627 };
628
629 static const struct exar8250_board pbn_exar_XR17V8358 = {
630 .num_ports = 16,
631 .has_slave = true,
632 .setup = pci_xr17v35x_setup,
633 .exit = pci_xr17v35x_exit,
634 };
635
636 #define CONNECT_DEVICE(devid, sdevid, bd) { \
637 PCI_DEVICE_SUB( \
638 PCI_VENDOR_ID_EXAR, \
639 PCI_DEVICE_ID_EXAR_##devid, \
640 PCI_SUBVENDOR_ID_CONNECT_TECH, \
641 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_##sdevid), 0, 0, \
642 (kernel_ulong_t)&bd \
643 }
644
645 #define EXAR_DEVICE(vend, devid, bd) { \
646 PCI_VDEVICE(vend, PCI_DEVICE_ID_##devid), (kernel_ulong_t)&bd \
647 }
648
649 #define IBM_DEVICE(devid, sdevid, bd) { \
650 PCI_DEVICE_SUB( \
651 PCI_VENDOR_ID_EXAR, \
652 PCI_DEVICE_ID_EXAR_##devid, \
653 PCI_VENDOR_ID_IBM, \
654 PCI_SUBDEVICE_ID_IBM_##sdevid), 0, 0, \
655 (kernel_ulong_t)&bd \
656 }
657
658 static const struct pci_device_id exar_pci_tbl[] = {
659 EXAR_DEVICE(ACCESSIO, ACCES_COM_2S, acces_com_2x),
660 EXAR_DEVICE(ACCESSIO, ACCES_COM_4S, acces_com_4x),
661 EXAR_DEVICE(ACCESSIO, ACCES_COM_8S, acces_com_8x),
662 EXAR_DEVICE(ACCESSIO, ACCES_COM232_8, acces_com_8x),
663 EXAR_DEVICE(ACCESSIO, ACCES_COM_2SM, acces_com_2x),
664 EXAR_DEVICE(ACCESSIO, ACCES_COM_4SM, acces_com_4x),
665 EXAR_DEVICE(ACCESSIO, ACCES_COM_8SM, acces_com_8x),
666
667
668 CONNECT_DEVICE(XR17C152, UART_2_232, pbn_connect),
669 CONNECT_DEVICE(XR17C154, UART_4_232, pbn_connect),
670 CONNECT_DEVICE(XR17C158, UART_8_232, pbn_connect),
671 CONNECT_DEVICE(XR17C152, UART_1_1, pbn_connect),
672 CONNECT_DEVICE(XR17C154, UART_2_2, pbn_connect),
673 CONNECT_DEVICE(XR17C158, UART_4_4, pbn_connect),
674 CONNECT_DEVICE(XR17C152, UART_2, pbn_connect),
675 CONNECT_DEVICE(XR17C154, UART_4, pbn_connect),
676 CONNECT_DEVICE(XR17C158, UART_8, pbn_connect),
677 CONNECT_DEVICE(XR17C152, UART_2_485, pbn_connect),
678 CONNECT_DEVICE(XR17C154, UART_4_485, pbn_connect),
679 CONNECT_DEVICE(XR17C158, UART_8_485, pbn_connect),
680
681 IBM_DEVICE(XR17C152, SATURN_SERIAL_ONE_PORT, pbn_exar_ibm_saturn),
682
683 /* Exar Corp. XR17C15[248] Dual/Quad/Octal UART */
684 EXAR_DEVICE(EXAR, EXAR_XR17C152, pbn_exar_XR17C15x),
685 EXAR_DEVICE(EXAR, EXAR_XR17C154, pbn_exar_XR17C15x),
686 EXAR_DEVICE(EXAR, EXAR_XR17C158, pbn_exar_XR17C15x),
687
688 /* Exar Corp. XR17V[48]35[248] Dual/Quad/Octal/Hexa PCIe UARTs */
689 EXAR_DEVICE(EXAR, EXAR_XR17V352, pbn_exar_XR17V35x),
690 EXAR_DEVICE(EXAR, EXAR_XR17V354, pbn_exar_XR17V35x),
691 EXAR_DEVICE(EXAR, EXAR_XR17V358, pbn_exar_XR17V35x),
692 EXAR_DEVICE(EXAR, EXAR_XR17V4358, pbn_exar_XR17V4358),
693 EXAR_DEVICE(EXAR, EXAR_XR17V8358, pbn_exar_XR17V8358),
694 EXAR_DEVICE(COMMTECH, COMMTECH_4222PCIE, pbn_exar_XR17V35x),
695 EXAR_DEVICE(COMMTECH, COMMTECH_4224PCIE, pbn_exar_XR17V35x),
696 EXAR_DEVICE(COMMTECH, COMMTECH_4228PCIE, pbn_exar_XR17V35x),
697
698 EXAR_DEVICE(COMMTECH, COMMTECH_4222PCI335, pbn_fastcom335_2),
699 EXAR_DEVICE(COMMTECH, COMMTECH_4224PCI335, pbn_fastcom335_4),
700 EXAR_DEVICE(COMMTECH, COMMTECH_2324PCI335, pbn_fastcom335_4),
701 EXAR_DEVICE(COMMTECH, COMMTECH_2328PCI335, pbn_fastcom335_8),
702 { 0, }
703 };
704 MODULE_DEVICE_TABLE(pci, exar_pci_tbl);
705
706 static struct pci_driver exar_pci_driver = {
707 .name = "exar_serial",
708 .probe = exar_pci_probe,
709 .remove = exar_pci_remove,
710 .driver = {
711 .pm = &exar_pci_pm,
712 },
713 .id_table = exar_pci_tbl,
714 };
715 module_pci_driver(exar_pci_driver);
716
717 MODULE_LICENSE("GPL");
718 MODULE_DESCRIPTION("Exar Serial Driver");
719 MODULE_AUTHOR("Sudip Mukherjee <sudip.mukherjee@codethink.co.uk>");
720