1 /* QLogic qed NIC Driver 2 * Copyright (c) 2015-2017 QLogic Corporation 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and /or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef __ETH_COMMON__ 34 #define __ETH_COMMON__ 35 36 /********************/ 37 /* ETH FW CONSTANTS */ 38 /********************/ 39 #define ETH_HSI_VER_MAJOR 3 40 #define ETH_HSI_VER_MINOR 10 41 42 #define ETH_HSI_VER_NO_PKT_LEN_TUNN 5 43 44 #define ETH_CACHE_LINE_SIZE 64 45 #define ETH_RX_CQE_GAP 32 46 #define ETH_MAX_RAMROD_PER_CON 8 47 #define ETH_TX_BD_PAGE_SIZE_BYTES 4096 48 #define ETH_RX_BD_PAGE_SIZE_BYTES 4096 49 #define ETH_RX_CQE_PAGE_SIZE_BYTES 4096 50 #define ETH_RX_NUM_NEXT_PAGE_BDS 2 51 52 #define ETH_MAX_TUNN_LSO_INNER_IPV4_OFFSET 253 53 #define ETH_MAX_TUNN_LSO_INNER_IPV6_OFFSET 251 54 55 #define ETH_TX_MIN_BDS_PER_NON_LSO_PKT 1 56 #define ETH_TX_MAX_BDS_PER_NON_LSO_PACKET 18 57 #define ETH_TX_MAX_BDS_PER_LSO_PACKET 255 58 #define ETH_TX_MAX_LSO_HDR_NBD 4 59 #define ETH_TX_MIN_BDS_PER_LSO_PKT 3 60 #define ETH_TX_MIN_BDS_PER_TUNN_IPV6_WITH_EXT_PKT 3 61 #define ETH_TX_MIN_BDS_PER_IPV6_WITH_EXT_PKT 2 62 #define ETH_TX_MIN_BDS_PER_PKT_W_LOOPBACK_MODE 2 63 #define ETH_TX_MAX_NON_LSO_PKT_LEN (9700 - (4 + 4 + 12 + 8)) 64 #define ETH_TX_MAX_LSO_HDR_BYTES 510 65 #define ETH_TX_LSO_WINDOW_BDS_NUM (18 - 1) 66 #define ETH_TX_LSO_WINDOW_MIN_LEN 9700 67 #define ETH_TX_MAX_LSO_PAYLOAD_LEN 0xFE000 68 #define ETH_TX_NUM_SAME_AS_LAST_ENTRIES 320 69 #define ETH_TX_INACTIVE_SAME_AS_LAST 0xFFFF 70 71 #define ETH_NUM_STATISTIC_COUNTERS MAX_NUM_VPORTS 72 #define ETH_NUM_STATISTIC_COUNTERS_DOUBLE_VF_ZONE \ 73 (ETH_NUM_STATISTIC_COUNTERS - MAX_NUM_VFS / 2) 74 #define ETH_NUM_STATISTIC_COUNTERS_QUAD_VF_ZONE \ 75 (ETH_NUM_STATISTIC_COUNTERS - 3 * MAX_NUM_VFS / 4) 76 77 /* Maximum number of buffers, used for RX packet placement */ 78 #define ETH_RX_MAX_BUFF_PER_PKT 5 79 #define ETH_RX_BD_THRESHOLD 12 80 81 /* num of MAC/VLAN filters */ 82 #define ETH_NUM_MAC_FILTERS 512 83 #define ETH_NUM_VLAN_FILTERS 512 84 85 /* approx. multicast constants */ 86 #define ETH_MULTICAST_BIN_FROM_MAC_SEED 0 87 #define ETH_MULTICAST_MAC_BINS 256 88 #define ETH_MULTICAST_MAC_BINS_IN_REGS (ETH_MULTICAST_MAC_BINS / 32) 89 90 /* ethernet vport update constants */ 91 #define ETH_FILTER_RULES_COUNT 10 92 #define ETH_RSS_IND_TABLE_ENTRIES_NUM 128 93 #define ETH_RSS_KEY_SIZE_REGS 10 94 #define ETH_RSS_ENGINE_NUM_K2 207 95 #define ETH_RSS_ENGINE_NUM_BB 127 96 97 /* TPA constants */ 98 #define ETH_TPA_MAX_AGGS_NUM 64 99 #define ETH_TPA_CQE_START_LEN_LIST_SIZE ETH_RX_MAX_BUFF_PER_PKT 100 #define ETH_TPA_CQE_CONT_LEN_LIST_SIZE 6 101 #define ETH_TPA_CQE_END_LEN_LIST_SIZE 4 102 103 /* Control frame check constants */ 104 #define ETH_CTL_FRAME_ETH_TYPE_NUM 4 105 106 struct eth_tx_1st_bd_flags { 107 u8 bitfields; 108 #define ETH_TX_1ST_BD_FLAGS_START_BD_MASK 0x1 109 #define ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT 0 110 #define ETH_TX_1ST_BD_FLAGS_FORCE_VLAN_MODE_MASK 0x1 111 #define ETH_TX_1ST_BD_FLAGS_FORCE_VLAN_MODE_SHIFT 1 112 #define ETH_TX_1ST_BD_FLAGS_IP_CSUM_MASK 0x1 113 #define ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT 2 114 #define ETH_TX_1ST_BD_FLAGS_L4_CSUM_MASK 0x1 115 #define ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT 3 116 #define ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_MASK 0x1 117 #define ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_SHIFT 4 118 #define ETH_TX_1ST_BD_FLAGS_LSO_MASK 0x1 119 #define ETH_TX_1ST_BD_FLAGS_LSO_SHIFT 5 120 #define ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_MASK 0x1 121 #define ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_SHIFT 6 122 #define ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_MASK 0x1 123 #define ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_SHIFT 7 124 }; 125 126 /* The parsing information data fo rthe first tx bd of a given packet. */ 127 struct eth_tx_data_1st_bd { 128 __le16 vlan; 129 u8 nbds; 130 struct eth_tx_1st_bd_flags bd_flags; 131 __le16 bitfields; 132 #define ETH_TX_DATA_1ST_BD_TUNN_FLAG_MASK 0x1 133 #define ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT 0 134 #define ETH_TX_DATA_1ST_BD_RESERVED0_MASK 0x1 135 #define ETH_TX_DATA_1ST_BD_RESERVED0_SHIFT 1 136 #define ETH_TX_DATA_1ST_BD_PKT_LEN_MASK 0x3FFF 137 #define ETH_TX_DATA_1ST_BD_PKT_LEN_SHIFT 2 138 }; 139 140 /* The parsing information data for the second tx bd of a given packet. */ 141 struct eth_tx_data_2nd_bd { 142 __le16 tunn_ip_size; 143 __le16 bitfields1; 144 #define ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_MASK 0xF 145 #define ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_SHIFT 0 146 #define ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_MASK 0x3 147 #define ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_SHIFT 4 148 #define ETH_TX_DATA_2ND_BD_DEST_PORT_MODE_MASK 0x3 149 #define ETH_TX_DATA_2ND_BD_DEST_PORT_MODE_SHIFT 6 150 #define ETH_TX_DATA_2ND_BD_START_BD_MASK 0x1 151 #define ETH_TX_DATA_2ND_BD_START_BD_SHIFT 8 152 #define ETH_TX_DATA_2ND_BD_TUNN_TYPE_MASK 0x3 153 #define ETH_TX_DATA_2ND_BD_TUNN_TYPE_SHIFT 9 154 #define ETH_TX_DATA_2ND_BD_TUNN_INNER_IPV6_MASK 0x1 155 #define ETH_TX_DATA_2ND_BD_TUNN_INNER_IPV6_SHIFT 11 156 #define ETH_TX_DATA_2ND_BD_IPV6_EXT_MASK 0x1 157 #define ETH_TX_DATA_2ND_BD_IPV6_EXT_SHIFT 12 158 #define ETH_TX_DATA_2ND_BD_TUNN_IPV6_EXT_MASK 0x1 159 #define ETH_TX_DATA_2ND_BD_TUNN_IPV6_EXT_SHIFT 13 160 #define ETH_TX_DATA_2ND_BD_L4_UDP_MASK 0x1 161 #define ETH_TX_DATA_2ND_BD_L4_UDP_SHIFT 14 162 #define ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_MASK 0x1 163 #define ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_SHIFT 15 164 __le16 bitfields2; 165 #define ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_MASK 0x1FFF 166 #define ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_SHIFT 0 167 #define ETH_TX_DATA_2ND_BD_RESERVED0_MASK 0x7 168 #define ETH_TX_DATA_2ND_BD_RESERVED0_SHIFT 13 169 }; 170 171 /* Firmware data for L2-EDPM packet. */ 172 struct eth_edpm_fw_data { 173 struct eth_tx_data_1st_bd data_1st_bd; 174 struct eth_tx_data_2nd_bd data_2nd_bd; 175 __le32 reserved; 176 }; 177 178 struct eth_fast_path_cqe_fw_debug { 179 __le16 reserved2; 180 }; 181 182 /* tunneling parsing flags */ 183 struct eth_tunnel_parsing_flags { 184 u8 flags; 185 #define ETH_TUNNEL_PARSING_FLAGS_TYPE_MASK 0x3 186 #define ETH_TUNNEL_PARSING_FLAGS_TYPE_SHIFT 0 187 #define ETH_TUNNEL_PARSING_FLAGS_TENNANT_ID_EXIST_MASK 0x1 188 #define ETH_TUNNEL_PARSING_FLAGS_TENNANT_ID_EXIST_SHIFT 2 189 #define ETH_TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_MASK 0x3 190 #define ETH_TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_SHIFT 3 191 #define ETH_TUNNEL_PARSING_FLAGS_FIRSTHDRIPMATCH_MASK 0x1 192 #define ETH_TUNNEL_PARSING_FLAGS_FIRSTHDRIPMATCH_SHIFT 5 193 #define ETH_TUNNEL_PARSING_FLAGS_IPV4_FRAGMENT_MASK 0x1 194 #define ETH_TUNNEL_PARSING_FLAGS_IPV4_FRAGMENT_SHIFT 6 195 #define ETH_TUNNEL_PARSING_FLAGS_IPV4_OPTIONS_MASK 0x1 196 #define ETH_TUNNEL_PARSING_FLAGS_IPV4_OPTIONS_SHIFT 7 197 }; 198 199 /* PMD flow control bits */ 200 struct eth_pmd_flow_flags { 201 u8 flags; 202 #define ETH_PMD_FLOW_FLAGS_VALID_MASK 0x1 203 #define ETH_PMD_FLOW_FLAGS_VALID_SHIFT 0 204 #define ETH_PMD_FLOW_FLAGS_TOGGLE_MASK 0x1 205 #define ETH_PMD_FLOW_FLAGS_TOGGLE_SHIFT 1 206 #define ETH_PMD_FLOW_FLAGS_RESERVED_MASK 0x3F 207 #define ETH_PMD_FLOW_FLAGS_RESERVED_SHIFT 2 208 }; 209 210 /* Regular ETH Rx FP CQE. */ 211 struct eth_fast_path_rx_reg_cqe { 212 u8 type; 213 u8 bitfields; 214 #define ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE_MASK 0x7 215 #define ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE_SHIFT 0 216 #define ETH_FAST_PATH_RX_REG_CQE_TC_MASK 0xF 217 #define ETH_FAST_PATH_RX_REG_CQE_TC_SHIFT 3 218 #define ETH_FAST_PATH_RX_REG_CQE_RESERVED0_MASK 0x1 219 #define ETH_FAST_PATH_RX_REG_CQE_RESERVED0_SHIFT 7 220 __le16 pkt_len; 221 struct parsing_and_err_flags pars_flags; 222 __le16 vlan_tag; 223 __le32 rss_hash; 224 __le16 len_on_first_bd; 225 u8 placement_offset; 226 struct eth_tunnel_parsing_flags tunnel_pars_flags; 227 u8 bd_num; 228 u8 reserved[9]; 229 struct eth_fast_path_cqe_fw_debug fw_debug; 230 u8 reserved1[3]; 231 struct eth_pmd_flow_flags pmd_flags; 232 }; 233 234 /* TPA-continue ETH Rx FP CQE. */ 235 struct eth_fast_path_rx_tpa_cont_cqe { 236 u8 type; 237 u8 tpa_agg_index; 238 __le16 len_list[ETH_TPA_CQE_CONT_LEN_LIST_SIZE]; 239 u8 reserved; 240 u8 reserved1; 241 __le16 reserved2[ETH_TPA_CQE_CONT_LEN_LIST_SIZE]; 242 u8 reserved3[3]; 243 struct eth_pmd_flow_flags pmd_flags; 244 }; 245 246 /* TPA-end ETH Rx FP CQE. */ 247 struct eth_fast_path_rx_tpa_end_cqe { 248 u8 type; 249 u8 tpa_agg_index; 250 __le16 total_packet_len; 251 u8 num_of_bds; 252 u8 end_reason; 253 __le16 num_of_coalesced_segs; 254 __le32 ts_delta; 255 __le16 len_list[ETH_TPA_CQE_END_LEN_LIST_SIZE]; 256 __le16 reserved3[ETH_TPA_CQE_END_LEN_LIST_SIZE]; 257 __le16 reserved1; 258 u8 reserved2; 259 struct eth_pmd_flow_flags pmd_flags; 260 }; 261 262 /* TPA-start ETH Rx FP CQE. */ 263 struct eth_fast_path_rx_tpa_start_cqe { 264 u8 type; 265 u8 bitfields; 266 #define ETH_FAST_PATH_RX_TPA_START_CQE_RSS_HASH_TYPE_MASK 0x7 267 #define ETH_FAST_PATH_RX_TPA_START_CQE_RSS_HASH_TYPE_SHIFT 0 268 #define ETH_FAST_PATH_RX_TPA_START_CQE_TC_MASK 0xF 269 #define ETH_FAST_PATH_RX_TPA_START_CQE_TC_SHIFT 3 270 #define ETH_FAST_PATH_RX_TPA_START_CQE_RESERVED0_MASK 0x1 271 #define ETH_FAST_PATH_RX_TPA_START_CQE_RESERVED0_SHIFT 7 272 __le16 seg_len; 273 struct parsing_and_err_flags pars_flags; 274 __le16 vlan_tag; 275 __le32 rss_hash; 276 __le16 len_on_first_bd; 277 u8 placement_offset; 278 struct eth_tunnel_parsing_flags tunnel_pars_flags; 279 u8 tpa_agg_index; 280 u8 header_len; 281 __le16 ext_bd_len_list[ETH_TPA_CQE_START_LEN_LIST_SIZE]; 282 struct eth_fast_path_cqe_fw_debug fw_debug; 283 u8 reserved; 284 struct eth_pmd_flow_flags pmd_flags; 285 }; 286 287 /* The L4 pseudo checksum mode for Ethernet */ 288 enum eth_l4_pseudo_checksum_mode { 289 ETH_L4_PSEUDO_CSUM_CORRECT_LENGTH, 290 ETH_L4_PSEUDO_CSUM_ZERO_LENGTH, 291 MAX_ETH_L4_PSEUDO_CHECKSUM_MODE 292 }; 293 294 struct eth_rx_bd { 295 struct regpair addr; 296 }; 297 298 /* regular ETH Rx SP CQE */ 299 struct eth_slow_path_rx_cqe { 300 u8 type; 301 u8 ramrod_cmd_id; 302 u8 error_flag; 303 u8 reserved[25]; 304 __le16 echo; 305 u8 reserved1; 306 struct eth_pmd_flow_flags pmd_flags; 307 }; 308 309 /* union for all ETH Rx CQE types */ 310 union eth_rx_cqe { 311 struct eth_fast_path_rx_reg_cqe fast_path_regular; 312 struct eth_fast_path_rx_tpa_start_cqe fast_path_tpa_start; 313 struct eth_fast_path_rx_tpa_cont_cqe fast_path_tpa_cont; 314 struct eth_fast_path_rx_tpa_end_cqe fast_path_tpa_end; 315 struct eth_slow_path_rx_cqe slow_path; 316 }; 317 318 /* ETH Rx CQE type */ 319 enum eth_rx_cqe_type { 320 ETH_RX_CQE_TYPE_UNUSED, 321 ETH_RX_CQE_TYPE_REGULAR, 322 ETH_RX_CQE_TYPE_SLOW_PATH, 323 ETH_RX_CQE_TYPE_TPA_START, 324 ETH_RX_CQE_TYPE_TPA_CONT, 325 ETH_RX_CQE_TYPE_TPA_END, 326 MAX_ETH_RX_CQE_TYPE 327 }; 328 329 struct eth_rx_pmd_cqe { 330 union eth_rx_cqe cqe; 331 u8 reserved[ETH_RX_CQE_GAP]; 332 }; 333 334 enum eth_rx_tunn_type { 335 ETH_RX_NO_TUNN, 336 ETH_RX_TUNN_GENEVE, 337 ETH_RX_TUNN_GRE, 338 ETH_RX_TUNN_VXLAN, 339 MAX_ETH_RX_TUNN_TYPE 340 }; 341 342 /* Aggregation end reason. */ 343 enum eth_tpa_end_reason { 344 ETH_AGG_END_UNUSED, 345 ETH_AGG_END_SP_UPDATE, 346 ETH_AGG_END_MAX_LEN, 347 ETH_AGG_END_LAST_SEG, 348 ETH_AGG_END_TIMEOUT, 349 ETH_AGG_END_NOT_CONSISTENT, 350 ETH_AGG_END_OUT_OF_ORDER, 351 ETH_AGG_END_NON_TPA_SEG, 352 MAX_ETH_TPA_END_REASON 353 }; 354 355 /* The first tx bd of a given packet */ 356 struct eth_tx_1st_bd { 357 struct regpair addr; 358 __le16 nbytes; 359 struct eth_tx_data_1st_bd data; 360 }; 361 362 /* The second tx bd of a given packet */ 363 struct eth_tx_2nd_bd { 364 struct regpair addr; 365 __le16 nbytes; 366 struct eth_tx_data_2nd_bd data; 367 }; 368 369 /* The parsing information data for the third tx bd of a given packet. */ 370 struct eth_tx_data_3rd_bd { 371 __le16 lso_mss; 372 __le16 bitfields; 373 #define ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_MASK 0xF 374 #define ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_SHIFT 0 375 #define ETH_TX_DATA_3RD_BD_HDR_NBD_MASK 0xF 376 #define ETH_TX_DATA_3RD_BD_HDR_NBD_SHIFT 4 377 #define ETH_TX_DATA_3RD_BD_START_BD_MASK 0x1 378 #define ETH_TX_DATA_3RD_BD_START_BD_SHIFT 8 379 #define ETH_TX_DATA_3RD_BD_RESERVED0_MASK 0x7F 380 #define ETH_TX_DATA_3RD_BD_RESERVED0_SHIFT 9 381 u8 tunn_l4_hdr_start_offset_w; 382 u8 tunn_hdr_size_w; 383 }; 384 385 /* The third tx bd of a given packet */ 386 struct eth_tx_3rd_bd { 387 struct regpair addr; 388 __le16 nbytes; 389 struct eth_tx_data_3rd_bd data; 390 }; 391 392 /* Complementary information for the regular tx bd of a given packet. */ 393 struct eth_tx_data_bd { 394 __le16 reserved0; 395 __le16 bitfields; 396 #define ETH_TX_DATA_BD_RESERVED1_MASK 0xFF 397 #define ETH_TX_DATA_BD_RESERVED1_SHIFT 0 398 #define ETH_TX_DATA_BD_START_BD_MASK 0x1 399 #define ETH_TX_DATA_BD_START_BD_SHIFT 8 400 #define ETH_TX_DATA_BD_RESERVED2_MASK 0x7F 401 #define ETH_TX_DATA_BD_RESERVED2_SHIFT 9 402 __le16 reserved3; 403 }; 404 405 /* The common non-special TX BD ring element */ 406 struct eth_tx_bd { 407 struct regpair addr; 408 __le16 nbytes; 409 struct eth_tx_data_bd data; 410 }; 411 412 union eth_tx_bd_types { 413 struct eth_tx_1st_bd first_bd; 414 struct eth_tx_2nd_bd second_bd; 415 struct eth_tx_3rd_bd third_bd; 416 struct eth_tx_bd reg_bd; 417 }; 418 419 /* Mstorm Queue Zone */ 420 enum eth_tx_tunn_type { 421 ETH_TX_TUNN_GENEVE, 422 ETH_TX_TUNN_TTAG, 423 ETH_TX_TUNN_GRE, 424 ETH_TX_TUNN_VXLAN, 425 MAX_ETH_TX_TUNN_TYPE 426 }; 427 428 /* Ystorm Queue Zone */ 429 struct xstorm_eth_queue_zone { 430 struct coalescing_timeset int_coalescing_timeset; 431 u8 reserved[7]; 432 }; 433 434 /* ETH doorbell data */ 435 struct eth_db_data { 436 u8 params; 437 #define ETH_DB_DATA_DEST_MASK 0x3 438 #define ETH_DB_DATA_DEST_SHIFT 0 439 #define ETH_DB_DATA_AGG_CMD_MASK 0x3 440 #define ETH_DB_DATA_AGG_CMD_SHIFT 2 441 #define ETH_DB_DATA_BYPASS_EN_MASK 0x1 442 #define ETH_DB_DATA_BYPASS_EN_SHIFT 4 443 #define ETH_DB_DATA_RESERVED_MASK 0x1 444 #define ETH_DB_DATA_RESERVED_SHIFT 5 445 #define ETH_DB_DATA_AGG_VAL_SEL_MASK 0x3 446 #define ETH_DB_DATA_AGG_VAL_SEL_SHIFT 6 447 u8 agg_flags; 448 __le16 bd_prod; 449 }; 450 451 #endif /* __ETH_COMMON__ */ 452