1 /* sound/soc/samsung/i2s.c
2 *
3 * ALSA SoC Audio Layer - Samsung I2S Controller driver
4 *
5 * Copyright (c) 2010 Samsung Electronics Co. Ltd.
6 * Jaswinder Singh <jassisinghbrar@gmail.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 #include <dt-bindings/sound/samsung-i2s.h>
14 #include <linux/delay.h>
15 #include <linux/slab.h>
16 #include <linux/clk.h>
17 #include <linux/clk-provider.h>
18 #include <linux/io.h>
19 #include <linux/module.h>
20 #include <linux/of.h>
21 #include <linux/of_device.h>
22 #include <linux/of_gpio.h>
23 #include <linux/pm_runtime.h>
24
25 #include <sound/soc.h>
26 #include <sound/pcm_params.h>
27
28 #include <linux/platform_data/asoc-s3c.h>
29
30 #include "dma.h"
31 #include "idma.h"
32 #include "i2s.h"
33 #include "i2s-regs.h"
34
35 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
36
37 struct samsung_i2s_variant_regs {
38 unsigned int bfs_off;
39 unsigned int rfs_off;
40 unsigned int sdf_off;
41 unsigned int txr_off;
42 unsigned int rclksrc_off;
43 unsigned int mss_off;
44 unsigned int cdclkcon_off;
45 unsigned int lrp_off;
46 unsigned int bfs_mask;
47 unsigned int rfs_mask;
48 unsigned int ftx0cnt_off;
49 };
50
51 struct samsung_i2s_dai_data {
52 u32 quirks;
53 unsigned int pcm_rates;
54 const struct samsung_i2s_variant_regs *i2s_variant_regs;
55 };
56
57 struct i2s_dai {
58 /* Platform device for this DAI */
59 struct platform_device *pdev;
60 /* Memory mapped SFR region */
61 void __iomem *addr;
62 /* Rate of RCLK source clock */
63 unsigned long rclk_srcrate;
64 /* Frame Clock */
65 unsigned frmclk;
66 /*
67 * Specifically requested RCLK,BCLK by MACHINE Driver.
68 * 0 indicates CPU driver is free to choose any value.
69 */
70 unsigned rfs, bfs;
71 /* I2S Controller's core clock */
72 struct clk *clk;
73 /* Clock for generating I2S signals */
74 struct clk *op_clk;
75 /* Pointer to the Primary_Fifo if this is Sec_Fifo, NULL otherwise */
76 struct i2s_dai *pri_dai;
77 /* Pointer to the Secondary_Fifo if it has one, NULL otherwise */
78 struct i2s_dai *sec_dai;
79 #define DAI_OPENED (1 << 0) /* Dai is opened */
80 #define DAI_MANAGER (1 << 1) /* Dai is the manager */
81 unsigned mode;
82 /* Driver for this DAI */
83 struct snd_soc_dai_driver i2s_dai_drv;
84 /* DMA parameters */
85 struct snd_dmaengine_dai_dma_data dma_playback;
86 struct snd_dmaengine_dai_dma_data dma_capture;
87 struct snd_dmaengine_dai_dma_data idma_playback;
88 dma_filter_fn filter;
89 u32 quirks;
90 u32 suspend_i2smod;
91 u32 suspend_i2scon;
92 u32 suspend_i2spsr;
93 const struct samsung_i2s_variant_regs *variant_regs;
94
95 /* Spinlock protecting access to the device's registers */
96 spinlock_t spinlock;
97 spinlock_t *lock;
98
99 /* Below fields are only valid if this is the primary FIFO */
100 struct clk *clk_table[3];
101 struct clk_onecell_data clk_data;
102 };
103
104 /* Lock for cross i/f checks */
105 static DEFINE_SPINLOCK(lock);
106
107 /* If this is the 'overlay' stereo DAI */
is_secondary(struct i2s_dai * i2s)108 static inline bool is_secondary(struct i2s_dai *i2s)
109 {
110 return i2s->pri_dai ? true : false;
111 }
112
113 /* If operating in SoC-Slave mode */
is_slave(struct i2s_dai * i2s)114 static inline bool is_slave(struct i2s_dai *i2s)
115 {
116 u32 mod = readl(i2s->addr + I2SMOD);
117 return (mod & (1 << i2s->variant_regs->mss_off)) ? true : false;
118 }
119
120 /* If this interface of the controller is transmitting data */
tx_active(struct i2s_dai * i2s)121 static inline bool tx_active(struct i2s_dai *i2s)
122 {
123 u32 active;
124
125 if (!i2s)
126 return false;
127
128 active = readl(i2s->addr + I2SCON);
129
130 if (is_secondary(i2s))
131 active &= CON_TXSDMA_ACTIVE;
132 else
133 active &= CON_TXDMA_ACTIVE;
134
135 return active ? true : false;
136 }
137
138 /* Return pointer to the other DAI */
get_other_dai(struct i2s_dai * i2s)139 static inline struct i2s_dai *get_other_dai(struct i2s_dai *i2s)
140 {
141 return i2s->pri_dai ? : i2s->sec_dai;
142 }
143
144 /* If the other interface of the controller is transmitting data */
other_tx_active(struct i2s_dai * i2s)145 static inline bool other_tx_active(struct i2s_dai *i2s)
146 {
147 struct i2s_dai *other = get_other_dai(i2s);
148
149 return tx_active(other);
150 }
151
152 /* If any interface of the controller is transmitting data */
any_tx_active(struct i2s_dai * i2s)153 static inline bool any_tx_active(struct i2s_dai *i2s)
154 {
155 return tx_active(i2s) || other_tx_active(i2s);
156 }
157
158 /* If this interface of the controller is receiving data */
rx_active(struct i2s_dai * i2s)159 static inline bool rx_active(struct i2s_dai *i2s)
160 {
161 u32 active;
162
163 if (!i2s)
164 return false;
165
166 active = readl(i2s->addr + I2SCON) & CON_RXDMA_ACTIVE;
167
168 return active ? true : false;
169 }
170
171 /* If the other interface of the controller is receiving data */
other_rx_active(struct i2s_dai * i2s)172 static inline bool other_rx_active(struct i2s_dai *i2s)
173 {
174 struct i2s_dai *other = get_other_dai(i2s);
175
176 return rx_active(other);
177 }
178
179 /* If any interface of the controller is receiving data */
any_rx_active(struct i2s_dai * i2s)180 static inline bool any_rx_active(struct i2s_dai *i2s)
181 {
182 return rx_active(i2s) || other_rx_active(i2s);
183 }
184
185 /* If the other DAI is transmitting or receiving data */
other_active(struct i2s_dai * i2s)186 static inline bool other_active(struct i2s_dai *i2s)
187 {
188 return other_rx_active(i2s) || other_tx_active(i2s);
189 }
190
191 /* If this DAI is transmitting or receiving data */
this_active(struct i2s_dai * i2s)192 static inline bool this_active(struct i2s_dai *i2s)
193 {
194 return tx_active(i2s) || rx_active(i2s);
195 }
196
197 /* If the controller is active anyway */
any_active(struct i2s_dai * i2s)198 static inline bool any_active(struct i2s_dai *i2s)
199 {
200 return this_active(i2s) || other_active(i2s);
201 }
202
to_info(struct snd_soc_dai * dai)203 static inline struct i2s_dai *to_info(struct snd_soc_dai *dai)
204 {
205 return snd_soc_dai_get_drvdata(dai);
206 }
207
is_opened(struct i2s_dai * i2s)208 static inline bool is_opened(struct i2s_dai *i2s)
209 {
210 if (i2s && (i2s->mode & DAI_OPENED))
211 return true;
212 else
213 return false;
214 }
215
is_manager(struct i2s_dai * i2s)216 static inline bool is_manager(struct i2s_dai *i2s)
217 {
218 if (is_opened(i2s) && (i2s->mode & DAI_MANAGER))
219 return true;
220 else
221 return false;
222 }
223
224 /* Read RCLK of I2S (in multiples of LRCLK) */
get_rfs(struct i2s_dai * i2s)225 static inline unsigned get_rfs(struct i2s_dai *i2s)
226 {
227 u32 rfs;
228 rfs = readl(i2s->addr + I2SMOD) >> i2s->variant_regs->rfs_off;
229 rfs &= i2s->variant_regs->rfs_mask;
230
231 switch (rfs) {
232 case 7: return 192;
233 case 6: return 96;
234 case 5: return 128;
235 case 4: return 64;
236 case 3: return 768;
237 case 2: return 384;
238 case 1: return 512;
239 default: return 256;
240 }
241 }
242
243 /* Write RCLK of I2S (in multiples of LRCLK) */
set_rfs(struct i2s_dai * i2s,unsigned rfs)244 static inline void set_rfs(struct i2s_dai *i2s, unsigned rfs)
245 {
246 u32 mod = readl(i2s->addr + I2SMOD);
247 int rfs_shift = i2s->variant_regs->rfs_off;
248
249 mod &= ~(i2s->variant_regs->rfs_mask << rfs_shift);
250
251 switch (rfs) {
252 case 192:
253 mod |= (EXYNOS7_MOD_RCLK_192FS << rfs_shift);
254 break;
255 case 96:
256 mod |= (EXYNOS7_MOD_RCLK_96FS << rfs_shift);
257 break;
258 case 128:
259 mod |= (EXYNOS7_MOD_RCLK_128FS << rfs_shift);
260 break;
261 case 64:
262 mod |= (EXYNOS7_MOD_RCLK_64FS << rfs_shift);
263 break;
264 case 768:
265 mod |= (MOD_RCLK_768FS << rfs_shift);
266 break;
267 case 512:
268 mod |= (MOD_RCLK_512FS << rfs_shift);
269 break;
270 case 384:
271 mod |= (MOD_RCLK_384FS << rfs_shift);
272 break;
273 default:
274 mod |= (MOD_RCLK_256FS << rfs_shift);
275 break;
276 }
277
278 writel(mod, i2s->addr + I2SMOD);
279 }
280
281 /* Read Bit-Clock of I2S (in multiples of LRCLK) */
get_bfs(struct i2s_dai * i2s)282 static inline unsigned get_bfs(struct i2s_dai *i2s)
283 {
284 u32 bfs;
285 bfs = readl(i2s->addr + I2SMOD) >> i2s->variant_regs->bfs_off;
286 bfs &= i2s->variant_regs->bfs_mask;
287
288 switch (bfs) {
289 case 8: return 256;
290 case 7: return 192;
291 case 6: return 128;
292 case 5: return 96;
293 case 4: return 64;
294 case 3: return 24;
295 case 2: return 16;
296 case 1: return 48;
297 default: return 32;
298 }
299 }
300
301 /* Write Bit-Clock of I2S (in multiples of LRCLK) */
set_bfs(struct i2s_dai * i2s,unsigned bfs)302 static inline void set_bfs(struct i2s_dai *i2s, unsigned bfs)
303 {
304 u32 mod = readl(i2s->addr + I2SMOD);
305 int tdm = i2s->quirks & QUIRK_SUPPORTS_TDM;
306 int bfs_shift = i2s->variant_regs->bfs_off;
307
308 /* Non-TDM I2S controllers do not support BCLK > 48 * FS */
309 if (!tdm && bfs > 48) {
310 dev_err(&i2s->pdev->dev, "Unsupported BCLK divider\n");
311 return;
312 }
313
314 mod &= ~(i2s->variant_regs->bfs_mask << bfs_shift);
315
316 switch (bfs) {
317 case 48:
318 mod |= (MOD_BCLK_48FS << bfs_shift);
319 break;
320 case 32:
321 mod |= (MOD_BCLK_32FS << bfs_shift);
322 break;
323 case 24:
324 mod |= (MOD_BCLK_24FS << bfs_shift);
325 break;
326 case 16:
327 mod |= (MOD_BCLK_16FS << bfs_shift);
328 break;
329 case 64:
330 mod |= (EXYNOS5420_MOD_BCLK_64FS << bfs_shift);
331 break;
332 case 96:
333 mod |= (EXYNOS5420_MOD_BCLK_96FS << bfs_shift);
334 break;
335 case 128:
336 mod |= (EXYNOS5420_MOD_BCLK_128FS << bfs_shift);
337 break;
338 case 192:
339 mod |= (EXYNOS5420_MOD_BCLK_192FS << bfs_shift);
340 break;
341 case 256:
342 mod |= (EXYNOS5420_MOD_BCLK_256FS << bfs_shift);
343 break;
344 default:
345 dev_err(&i2s->pdev->dev, "Wrong BCLK Divider!\n");
346 return;
347 }
348
349 writel(mod, i2s->addr + I2SMOD);
350 }
351
352 /* Sample-Size */
get_blc(struct i2s_dai * i2s)353 static inline int get_blc(struct i2s_dai *i2s)
354 {
355 int blc = readl(i2s->addr + I2SMOD);
356
357 blc = (blc >> 13) & 0x3;
358
359 switch (blc) {
360 case 2: return 24;
361 case 1: return 8;
362 default: return 16;
363 }
364 }
365
366 /* TX Channel Control */
i2s_txctrl(struct i2s_dai * i2s,int on)367 static void i2s_txctrl(struct i2s_dai *i2s, int on)
368 {
369 void __iomem *addr = i2s->addr;
370 int txr_off = i2s->variant_regs->txr_off;
371 u32 con = readl(addr + I2SCON);
372 u32 mod = readl(addr + I2SMOD) & ~(3 << txr_off);
373
374 if (on) {
375 con |= CON_ACTIVE;
376 con &= ~CON_TXCH_PAUSE;
377
378 if (is_secondary(i2s)) {
379 con |= CON_TXSDMA_ACTIVE;
380 con &= ~CON_TXSDMA_PAUSE;
381 } else {
382 con |= CON_TXDMA_ACTIVE;
383 con &= ~CON_TXDMA_PAUSE;
384 }
385
386 if (any_rx_active(i2s))
387 mod |= 2 << txr_off;
388 else
389 mod |= 0 << txr_off;
390 } else {
391 if (is_secondary(i2s)) {
392 con |= CON_TXSDMA_PAUSE;
393 con &= ~CON_TXSDMA_ACTIVE;
394 } else {
395 con |= CON_TXDMA_PAUSE;
396 con &= ~CON_TXDMA_ACTIVE;
397 }
398
399 if (other_tx_active(i2s)) {
400 writel(con, addr + I2SCON);
401 return;
402 }
403
404 con |= CON_TXCH_PAUSE;
405
406 if (any_rx_active(i2s))
407 mod |= 1 << txr_off;
408 else
409 con &= ~CON_ACTIVE;
410 }
411
412 writel(mod, addr + I2SMOD);
413 writel(con, addr + I2SCON);
414 }
415
416 /* RX Channel Control */
i2s_rxctrl(struct i2s_dai * i2s,int on)417 static void i2s_rxctrl(struct i2s_dai *i2s, int on)
418 {
419 void __iomem *addr = i2s->addr;
420 int txr_off = i2s->variant_regs->txr_off;
421 u32 con = readl(addr + I2SCON);
422 u32 mod = readl(addr + I2SMOD) & ~(3 << txr_off);
423
424 if (on) {
425 con |= CON_RXDMA_ACTIVE | CON_ACTIVE;
426 con &= ~(CON_RXDMA_PAUSE | CON_RXCH_PAUSE);
427
428 if (any_tx_active(i2s))
429 mod |= 2 << txr_off;
430 else
431 mod |= 1 << txr_off;
432 } else {
433 con |= CON_RXDMA_PAUSE | CON_RXCH_PAUSE;
434 con &= ~CON_RXDMA_ACTIVE;
435
436 if (any_tx_active(i2s))
437 mod |= 0 << txr_off;
438 else
439 con &= ~CON_ACTIVE;
440 }
441
442 writel(mod, addr + I2SMOD);
443 writel(con, addr + I2SCON);
444 }
445
446 /* Flush FIFO of an interface */
i2s_fifo(struct i2s_dai * i2s,u32 flush)447 static inline void i2s_fifo(struct i2s_dai *i2s, u32 flush)
448 {
449 void __iomem *fic;
450 u32 val;
451
452 if (!i2s)
453 return;
454
455 if (is_secondary(i2s))
456 fic = i2s->addr + I2SFICS;
457 else
458 fic = i2s->addr + I2SFIC;
459
460 /* Flush the FIFO */
461 writel(readl(fic) | flush, fic);
462
463 /* Be patient */
464 val = msecs_to_loops(1) / 1000; /* 1 usec */
465 while (--val)
466 cpu_relax();
467
468 writel(readl(fic) & ~flush, fic);
469 }
470
i2s_set_sysclk(struct snd_soc_dai * dai,int clk_id,unsigned int rfs,int dir)471 static int i2s_set_sysclk(struct snd_soc_dai *dai,
472 int clk_id, unsigned int rfs, int dir)
473 {
474 struct i2s_dai *i2s = to_info(dai);
475 struct i2s_dai *other = get_other_dai(i2s);
476 const struct samsung_i2s_variant_regs *i2s_regs = i2s->variant_regs;
477 unsigned int cdcon_mask = 1 << i2s_regs->cdclkcon_off;
478 unsigned int rsrc_mask = 1 << i2s_regs->rclksrc_off;
479 u32 mod, mask, val = 0;
480 unsigned long flags;
481 int ret = 0;
482
483 pm_runtime_get_sync(dai->dev);
484
485 spin_lock_irqsave(i2s->lock, flags);
486 mod = readl(i2s->addr + I2SMOD);
487 spin_unlock_irqrestore(i2s->lock, flags);
488
489 switch (clk_id) {
490 case SAMSUNG_I2S_OPCLK:
491 mask = MOD_OPCLK_MASK;
492 val = dir;
493 break;
494 case SAMSUNG_I2S_CDCLK:
495 mask = 1 << i2s_regs->cdclkcon_off;
496 /* Shouldn't matter in GATING(CLOCK_IN) mode */
497 if (dir == SND_SOC_CLOCK_IN)
498 rfs = 0;
499
500 if ((rfs && other && other->rfs && (other->rfs != rfs)) ||
501 (any_active(i2s) &&
502 (((dir == SND_SOC_CLOCK_IN)
503 && !(mod & cdcon_mask)) ||
504 ((dir == SND_SOC_CLOCK_OUT)
505 && (mod & cdcon_mask))))) {
506 dev_err(&i2s->pdev->dev,
507 "%s:%d Other DAI busy\n", __func__, __LINE__);
508 ret = -EAGAIN;
509 goto err;
510 }
511
512 if (dir == SND_SOC_CLOCK_IN)
513 val = 1 << i2s_regs->cdclkcon_off;
514
515 i2s->rfs = rfs;
516 break;
517
518 case SAMSUNG_I2S_RCLKSRC_0: /* clock corrsponding to IISMOD[10] := 0 */
519 case SAMSUNG_I2S_RCLKSRC_1: /* clock corrsponding to IISMOD[10] := 1 */
520 mask = 1 << i2s_regs->rclksrc_off;
521
522 if ((i2s->quirks & QUIRK_NO_MUXPSR)
523 || (clk_id == SAMSUNG_I2S_RCLKSRC_0))
524 clk_id = 0;
525 else
526 clk_id = 1;
527
528 if (!any_active(i2s)) {
529 if (i2s->op_clk && !IS_ERR(i2s->op_clk)) {
530 if ((clk_id && !(mod & rsrc_mask)) ||
531 (!clk_id && (mod & rsrc_mask))) {
532 clk_disable_unprepare(i2s->op_clk);
533 clk_put(i2s->op_clk);
534 } else {
535 i2s->rclk_srcrate =
536 clk_get_rate(i2s->op_clk);
537 goto done;
538 }
539 }
540
541 if (clk_id)
542 i2s->op_clk = clk_get(&i2s->pdev->dev,
543 "i2s_opclk1");
544 else
545 i2s->op_clk = clk_get(&i2s->pdev->dev,
546 "i2s_opclk0");
547
548 if (WARN_ON(IS_ERR(i2s->op_clk))) {
549 ret = PTR_ERR(i2s->op_clk);
550 i2s->op_clk = NULL;
551 goto err;
552 }
553
554 ret = clk_prepare_enable(i2s->op_clk);
555 if (ret) {
556 clk_put(i2s->op_clk);
557 i2s->op_clk = NULL;
558 goto err;
559 }
560 i2s->rclk_srcrate = clk_get_rate(i2s->op_clk);
561
562 /* Over-ride the other's */
563 if (other) {
564 other->op_clk = i2s->op_clk;
565 other->rclk_srcrate = i2s->rclk_srcrate;
566 }
567 } else if ((!clk_id && (mod & rsrc_mask))
568 || (clk_id && !(mod & rsrc_mask))) {
569 dev_err(&i2s->pdev->dev,
570 "%s:%d Other DAI busy\n", __func__, __LINE__);
571 ret = -EAGAIN;
572 goto err;
573 } else {
574 /* Call can't be on the active DAI */
575 i2s->op_clk = other->op_clk;
576 i2s->rclk_srcrate = other->rclk_srcrate;
577 goto done;
578 }
579
580 if (clk_id == 1)
581 val = 1 << i2s_regs->rclksrc_off;
582 break;
583 default:
584 dev_err(&i2s->pdev->dev, "We don't serve that!\n");
585 ret = -EINVAL;
586 goto err;
587 }
588
589 spin_lock_irqsave(i2s->lock, flags);
590 mod = readl(i2s->addr + I2SMOD);
591 mod = (mod & ~mask) | val;
592 writel(mod, i2s->addr + I2SMOD);
593 spin_unlock_irqrestore(i2s->lock, flags);
594 done:
595 pm_runtime_put(dai->dev);
596
597 return 0;
598 err:
599 pm_runtime_put(dai->dev);
600 return ret;
601 }
602
i2s_set_fmt(struct snd_soc_dai * dai,unsigned int fmt)603 static int i2s_set_fmt(struct snd_soc_dai *dai,
604 unsigned int fmt)
605 {
606 struct i2s_dai *i2s = to_info(dai);
607 int lrp_shift, sdf_shift, sdf_mask, lrp_rlow, mod_slave;
608 u32 mod, tmp = 0;
609 unsigned long flags;
610
611 lrp_shift = i2s->variant_regs->lrp_off;
612 sdf_shift = i2s->variant_regs->sdf_off;
613 mod_slave = 1 << i2s->variant_regs->mss_off;
614
615 sdf_mask = MOD_SDF_MASK << sdf_shift;
616 lrp_rlow = MOD_LR_RLOW << lrp_shift;
617
618 /* Format is priority */
619 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
620 case SND_SOC_DAIFMT_RIGHT_J:
621 tmp |= lrp_rlow;
622 tmp |= (MOD_SDF_MSB << sdf_shift);
623 break;
624 case SND_SOC_DAIFMT_LEFT_J:
625 tmp |= lrp_rlow;
626 tmp |= (MOD_SDF_LSB << sdf_shift);
627 break;
628 case SND_SOC_DAIFMT_I2S:
629 tmp |= (MOD_SDF_IIS << sdf_shift);
630 break;
631 default:
632 dev_err(&i2s->pdev->dev, "Format not supported\n");
633 return -EINVAL;
634 }
635
636 /*
637 * INV flag is relative to the FORMAT flag - if set it simply
638 * flips the polarity specified by the Standard
639 */
640 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
641 case SND_SOC_DAIFMT_NB_NF:
642 break;
643 case SND_SOC_DAIFMT_NB_IF:
644 if (tmp & lrp_rlow)
645 tmp &= ~lrp_rlow;
646 else
647 tmp |= lrp_rlow;
648 break;
649 default:
650 dev_err(&i2s->pdev->dev, "Polarity not supported\n");
651 return -EINVAL;
652 }
653
654 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
655 case SND_SOC_DAIFMT_CBM_CFM:
656 tmp |= mod_slave;
657 break;
658 case SND_SOC_DAIFMT_CBS_CFS:
659 /*
660 * Set default source clock in Master mode, only when the
661 * CLK_I2S_RCLK_SRC clock is not exposed so we ensure any
662 * clock configuration assigned in DT is not overwritten.
663 */
664 if (i2s->rclk_srcrate == 0 && i2s->clk_data.clks == NULL)
665 i2s_set_sysclk(dai, SAMSUNG_I2S_RCLKSRC_0,
666 0, SND_SOC_CLOCK_IN);
667 break;
668 default:
669 dev_err(&i2s->pdev->dev, "master/slave format not supported\n");
670 return -EINVAL;
671 }
672
673 pm_runtime_get_sync(dai->dev);
674 spin_lock_irqsave(i2s->lock, flags);
675 mod = readl(i2s->addr + I2SMOD);
676 /*
677 * Don't change the I2S mode if any controller is active on this
678 * channel.
679 */
680 if (any_active(i2s) &&
681 ((mod & (sdf_mask | lrp_rlow | mod_slave)) != tmp)) {
682 spin_unlock_irqrestore(i2s->lock, flags);
683 pm_runtime_put(dai->dev);
684 dev_err(&i2s->pdev->dev,
685 "%s:%d Other DAI busy\n", __func__, __LINE__);
686 return -EAGAIN;
687 }
688
689 mod &= ~(sdf_mask | lrp_rlow | mod_slave);
690 mod |= tmp;
691 writel(mod, i2s->addr + I2SMOD);
692 spin_unlock_irqrestore(i2s->lock, flags);
693 pm_runtime_put(dai->dev);
694
695 return 0;
696 }
697
i2s_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)698 static int i2s_hw_params(struct snd_pcm_substream *substream,
699 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
700 {
701 struct i2s_dai *i2s = to_info(dai);
702 u32 mod, mask = 0, val = 0;
703 unsigned long flags;
704
705 WARN_ON(!pm_runtime_active(dai->dev));
706
707 if (!is_secondary(i2s))
708 mask |= (MOD_DC2_EN | MOD_DC1_EN);
709
710 switch (params_channels(params)) {
711 case 6:
712 val |= MOD_DC2_EN;
713 case 4:
714 val |= MOD_DC1_EN;
715 break;
716 case 2:
717 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
718 i2s->dma_playback.addr_width = 4;
719 else
720 i2s->dma_capture.addr_width = 4;
721 break;
722 case 1:
723 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
724 i2s->dma_playback.addr_width = 2;
725 else
726 i2s->dma_capture.addr_width = 2;
727
728 break;
729 default:
730 dev_err(&i2s->pdev->dev, "%d channels not supported\n",
731 params_channels(params));
732 return -EINVAL;
733 }
734
735 if (is_secondary(i2s))
736 mask |= MOD_BLCS_MASK;
737 else
738 mask |= MOD_BLCP_MASK;
739
740 if (is_manager(i2s))
741 mask |= MOD_BLC_MASK;
742
743 switch (params_width(params)) {
744 case 8:
745 if (is_secondary(i2s))
746 val |= MOD_BLCS_8BIT;
747 else
748 val |= MOD_BLCP_8BIT;
749 if (is_manager(i2s))
750 val |= MOD_BLC_8BIT;
751 break;
752 case 16:
753 if (is_secondary(i2s))
754 val |= MOD_BLCS_16BIT;
755 else
756 val |= MOD_BLCP_16BIT;
757 if (is_manager(i2s))
758 val |= MOD_BLC_16BIT;
759 break;
760 case 24:
761 if (is_secondary(i2s))
762 val |= MOD_BLCS_24BIT;
763 else
764 val |= MOD_BLCP_24BIT;
765 if (is_manager(i2s))
766 val |= MOD_BLC_24BIT;
767 break;
768 default:
769 dev_err(&i2s->pdev->dev, "Format(%d) not supported\n",
770 params_format(params));
771 return -EINVAL;
772 }
773
774 spin_lock_irqsave(i2s->lock, flags);
775 mod = readl(i2s->addr + I2SMOD);
776 mod = (mod & ~mask) | val;
777 writel(mod, i2s->addr + I2SMOD);
778 spin_unlock_irqrestore(i2s->lock, flags);
779
780 snd_soc_dai_init_dma_data(dai, &i2s->dma_playback, &i2s->dma_capture);
781
782 i2s->frmclk = params_rate(params);
783
784 return 0;
785 }
786
787 /* We set constraints on the substream acc to the version of I2S */
i2s_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)788 static int i2s_startup(struct snd_pcm_substream *substream,
789 struct snd_soc_dai *dai)
790 {
791 struct i2s_dai *i2s = to_info(dai);
792 struct i2s_dai *other = get_other_dai(i2s);
793 unsigned long flags;
794
795 pm_runtime_get_sync(dai->dev);
796
797 spin_lock_irqsave(&lock, flags);
798
799 i2s->mode |= DAI_OPENED;
800
801 if (is_manager(other))
802 i2s->mode &= ~DAI_MANAGER;
803 else
804 i2s->mode |= DAI_MANAGER;
805
806 if (!any_active(i2s) && (i2s->quirks & QUIRK_NEED_RSTCLR))
807 writel(CON_RSTCLR, i2s->addr + I2SCON);
808
809 spin_unlock_irqrestore(&lock, flags);
810
811 return 0;
812 }
813
i2s_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)814 static void i2s_shutdown(struct snd_pcm_substream *substream,
815 struct snd_soc_dai *dai)
816 {
817 struct i2s_dai *i2s = to_info(dai);
818 struct i2s_dai *other = get_other_dai(i2s);
819 unsigned long flags;
820
821 spin_lock_irqsave(&lock, flags);
822
823 i2s->mode &= ~DAI_OPENED;
824 i2s->mode &= ~DAI_MANAGER;
825
826 if (is_opened(other))
827 other->mode |= DAI_MANAGER;
828
829 /* Reset any constraint on RFS and BFS */
830 i2s->rfs = 0;
831 i2s->bfs = 0;
832
833 spin_unlock_irqrestore(&lock, flags);
834
835 pm_runtime_put(dai->dev);
836 }
837
config_setup(struct i2s_dai * i2s)838 static int config_setup(struct i2s_dai *i2s)
839 {
840 struct i2s_dai *other = get_other_dai(i2s);
841 unsigned rfs, bfs, blc;
842 u32 psr;
843
844 blc = get_blc(i2s);
845
846 bfs = i2s->bfs;
847
848 if (!bfs && other)
849 bfs = other->bfs;
850
851 /* Select least possible multiple(2) if no constraint set */
852 if (!bfs)
853 bfs = blc * 2;
854
855 rfs = i2s->rfs;
856
857 if (!rfs && other)
858 rfs = other->rfs;
859
860 if ((rfs == 256 || rfs == 512) && (blc == 24)) {
861 dev_err(&i2s->pdev->dev,
862 "%d-RFS not supported for 24-blc\n", rfs);
863 return -EINVAL;
864 }
865
866 if (!rfs) {
867 if (bfs == 16 || bfs == 32)
868 rfs = 256;
869 else
870 rfs = 384;
871 }
872
873 /* If already setup and running */
874 if (any_active(i2s) && (get_rfs(i2s) != rfs || get_bfs(i2s) != bfs)) {
875 dev_err(&i2s->pdev->dev,
876 "%s:%d Other DAI busy\n", __func__, __LINE__);
877 return -EAGAIN;
878 }
879
880 set_bfs(i2s, bfs);
881 set_rfs(i2s, rfs);
882
883 /* Don't bother with PSR in Slave mode */
884 if (is_slave(i2s))
885 return 0;
886
887 if (!(i2s->quirks & QUIRK_NO_MUXPSR)) {
888 struct clk *rclksrc = i2s->clk_table[CLK_I2S_RCLK_SRC];
889
890 if (i2s->rclk_srcrate == 0 && rclksrc && !IS_ERR(rclksrc))
891 i2s->rclk_srcrate = clk_get_rate(rclksrc);
892
893 psr = i2s->rclk_srcrate / i2s->frmclk / rfs;
894 writel(((psr - 1) << 8) | PSR_PSREN, i2s->addr + I2SPSR);
895 dev_dbg(&i2s->pdev->dev,
896 "RCLK_SRC=%luHz PSR=%u, RCLK=%dfs, BCLK=%dfs\n",
897 i2s->rclk_srcrate, psr, rfs, bfs);
898 }
899
900 return 0;
901 }
902
i2s_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)903 static int i2s_trigger(struct snd_pcm_substream *substream,
904 int cmd, struct snd_soc_dai *dai)
905 {
906 int capture = (substream->stream == SNDRV_PCM_STREAM_CAPTURE);
907 struct snd_soc_pcm_runtime *rtd = substream->private_data;
908 struct i2s_dai *i2s = to_info(rtd->cpu_dai);
909 unsigned long flags;
910
911 switch (cmd) {
912 case SNDRV_PCM_TRIGGER_START:
913 case SNDRV_PCM_TRIGGER_RESUME:
914 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
915 pm_runtime_get_sync(dai->dev);
916 spin_lock_irqsave(i2s->lock, flags);
917
918 if (config_setup(i2s)) {
919 spin_unlock_irqrestore(i2s->lock, flags);
920 return -EINVAL;
921 }
922
923 if (capture)
924 i2s_rxctrl(i2s, 1);
925 else
926 i2s_txctrl(i2s, 1);
927
928 spin_unlock_irqrestore(i2s->lock, flags);
929 break;
930 case SNDRV_PCM_TRIGGER_STOP:
931 case SNDRV_PCM_TRIGGER_SUSPEND:
932 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
933 spin_lock_irqsave(i2s->lock, flags);
934
935 if (capture) {
936 i2s_rxctrl(i2s, 0);
937 i2s_fifo(i2s, FIC_RXFLUSH);
938 } else {
939 i2s_txctrl(i2s, 0);
940 i2s_fifo(i2s, FIC_TXFLUSH);
941 }
942
943 spin_unlock_irqrestore(i2s->lock, flags);
944 pm_runtime_put(dai->dev);
945 break;
946 }
947
948 return 0;
949 }
950
i2s_set_clkdiv(struct snd_soc_dai * dai,int div_id,int div)951 static int i2s_set_clkdiv(struct snd_soc_dai *dai,
952 int div_id, int div)
953 {
954 struct i2s_dai *i2s = to_info(dai);
955 struct i2s_dai *other = get_other_dai(i2s);
956
957 switch (div_id) {
958 case SAMSUNG_I2S_DIV_BCLK:
959 pm_runtime_get_sync(dai->dev);
960 if ((any_active(i2s) && div && (get_bfs(i2s) != div))
961 || (other && other->bfs && (other->bfs != div))) {
962 pm_runtime_put(dai->dev);
963 dev_err(&i2s->pdev->dev,
964 "%s:%d Other DAI busy\n", __func__, __LINE__);
965 return -EAGAIN;
966 }
967 i2s->bfs = div;
968 pm_runtime_put(dai->dev);
969 break;
970 default:
971 dev_err(&i2s->pdev->dev,
972 "Invalid clock divider(%d)\n", div_id);
973 return -EINVAL;
974 }
975
976 return 0;
977 }
978
979 static snd_pcm_sframes_t
i2s_delay(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)980 i2s_delay(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
981 {
982 struct i2s_dai *i2s = to_info(dai);
983 u32 reg = readl(i2s->addr + I2SFIC);
984 snd_pcm_sframes_t delay;
985 const struct samsung_i2s_variant_regs *i2s_regs = i2s->variant_regs;
986
987 WARN_ON(!pm_runtime_active(dai->dev));
988
989 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
990 delay = FIC_RXCOUNT(reg);
991 else if (is_secondary(i2s))
992 delay = FICS_TXCOUNT(readl(i2s->addr + I2SFICS));
993 else
994 delay = (reg >> i2s_regs->ftx0cnt_off) & 0x7f;
995
996 return delay;
997 }
998
999 #ifdef CONFIG_PM
i2s_suspend(struct snd_soc_dai * dai)1000 static int i2s_suspend(struct snd_soc_dai *dai)
1001 {
1002 return pm_runtime_force_suspend(dai->dev);
1003 }
1004
i2s_resume(struct snd_soc_dai * dai)1005 static int i2s_resume(struct snd_soc_dai *dai)
1006 {
1007 return pm_runtime_force_resume(dai->dev);
1008 }
1009 #else
1010 #define i2s_suspend NULL
1011 #define i2s_resume NULL
1012 #endif
1013
samsung_i2s_dai_probe(struct snd_soc_dai * dai)1014 static int samsung_i2s_dai_probe(struct snd_soc_dai *dai)
1015 {
1016 struct i2s_dai *i2s = to_info(dai);
1017 struct i2s_dai *other = get_other_dai(i2s);
1018 unsigned long flags;
1019
1020 pm_runtime_get_sync(dai->dev);
1021
1022 if (is_secondary(i2s)) { /* If this is probe on the secondary DAI */
1023 snd_soc_dai_init_dma_data(dai, &other->sec_dai->dma_playback,
1024 NULL);
1025 } else {
1026 snd_soc_dai_init_dma_data(dai, &i2s->dma_playback,
1027 &i2s->dma_capture);
1028
1029 if (i2s->quirks & QUIRK_NEED_RSTCLR)
1030 writel(CON_RSTCLR, i2s->addr + I2SCON);
1031
1032 if (i2s->quirks & QUIRK_SUPPORTS_IDMA)
1033 idma_reg_addr_init(i2s->addr,
1034 i2s->sec_dai->idma_playback.addr);
1035 }
1036
1037 /* Reset any constraint on RFS and BFS */
1038 i2s->rfs = 0;
1039 i2s->bfs = 0;
1040 i2s->rclk_srcrate = 0;
1041
1042 spin_lock_irqsave(i2s->lock, flags);
1043 i2s_txctrl(i2s, 0);
1044 i2s_rxctrl(i2s, 0);
1045 i2s_fifo(i2s, FIC_TXFLUSH);
1046 i2s_fifo(other, FIC_TXFLUSH);
1047 i2s_fifo(i2s, FIC_RXFLUSH);
1048 spin_unlock_irqrestore(i2s->lock, flags);
1049
1050 /* Gate CDCLK by default */
1051 if (!is_opened(other))
1052 i2s_set_sysclk(dai, SAMSUNG_I2S_CDCLK,
1053 0, SND_SOC_CLOCK_IN);
1054 pm_runtime_put(dai->dev);
1055
1056 return 0;
1057 }
1058
samsung_i2s_dai_remove(struct snd_soc_dai * dai)1059 static int samsung_i2s_dai_remove(struct snd_soc_dai *dai)
1060 {
1061 struct i2s_dai *i2s = snd_soc_dai_get_drvdata(dai);
1062 unsigned long flags;
1063
1064 pm_runtime_get_sync(dai->dev);
1065
1066 if (!is_secondary(i2s)) {
1067 if (i2s->quirks & QUIRK_NEED_RSTCLR) {
1068 spin_lock_irqsave(i2s->lock, flags);
1069 writel(0, i2s->addr + I2SCON);
1070 spin_unlock_irqrestore(i2s->lock, flags);
1071 }
1072 }
1073
1074 pm_runtime_put(dai->dev);
1075
1076 return 0;
1077 }
1078
1079 static const struct snd_soc_dai_ops samsung_i2s_dai_ops = {
1080 .trigger = i2s_trigger,
1081 .hw_params = i2s_hw_params,
1082 .set_fmt = i2s_set_fmt,
1083 .set_clkdiv = i2s_set_clkdiv,
1084 .set_sysclk = i2s_set_sysclk,
1085 .startup = i2s_startup,
1086 .shutdown = i2s_shutdown,
1087 .delay = i2s_delay,
1088 };
1089
1090 static const struct snd_soc_component_driver samsung_i2s_component = {
1091 .name = "samsung-i2s",
1092 };
1093
1094 #define SAMSUNG_I2S_FMTS (SNDRV_PCM_FMTBIT_S8 | \
1095 SNDRV_PCM_FMTBIT_S16_LE | \
1096 SNDRV_PCM_FMTBIT_S24_LE)
1097
i2s_alloc_dai(struct platform_device * pdev,const struct samsung_i2s_dai_data * i2s_dai_data,bool sec)1098 static struct i2s_dai *i2s_alloc_dai(struct platform_device *pdev,
1099 const struct samsung_i2s_dai_data *i2s_dai_data,
1100 bool sec)
1101 {
1102 struct i2s_dai *i2s;
1103
1104 i2s = devm_kzalloc(&pdev->dev, sizeof(struct i2s_dai), GFP_KERNEL);
1105 if (i2s == NULL)
1106 return NULL;
1107
1108 i2s->pdev = pdev;
1109 i2s->pri_dai = NULL;
1110 i2s->sec_dai = NULL;
1111 i2s->i2s_dai_drv.symmetric_rates = 1;
1112 i2s->i2s_dai_drv.probe = samsung_i2s_dai_probe;
1113 i2s->i2s_dai_drv.remove = samsung_i2s_dai_remove;
1114 i2s->i2s_dai_drv.ops = &samsung_i2s_dai_ops;
1115 i2s->i2s_dai_drv.suspend = i2s_suspend;
1116 i2s->i2s_dai_drv.resume = i2s_resume;
1117 i2s->i2s_dai_drv.playback.channels_min = 1;
1118 i2s->i2s_dai_drv.playback.channels_max = 2;
1119 i2s->i2s_dai_drv.playback.rates = i2s_dai_data->pcm_rates;
1120 i2s->i2s_dai_drv.playback.formats = SAMSUNG_I2S_FMTS;
1121
1122 if (!sec) {
1123 i2s->i2s_dai_drv.capture.channels_min = 1;
1124 i2s->i2s_dai_drv.capture.channels_max = 2;
1125 i2s->i2s_dai_drv.capture.rates = i2s_dai_data->pcm_rates;
1126 i2s->i2s_dai_drv.capture.formats = SAMSUNG_I2S_FMTS;
1127 }
1128 return i2s;
1129 }
1130
1131 #ifdef CONFIG_PM
i2s_runtime_suspend(struct device * dev)1132 static int i2s_runtime_suspend(struct device *dev)
1133 {
1134 struct i2s_dai *i2s = dev_get_drvdata(dev);
1135
1136 i2s->suspend_i2smod = readl(i2s->addr + I2SMOD);
1137 i2s->suspend_i2scon = readl(i2s->addr + I2SCON);
1138 i2s->suspend_i2spsr = readl(i2s->addr + I2SPSR);
1139
1140 if (i2s->op_clk)
1141 clk_disable_unprepare(i2s->op_clk);
1142 clk_disable_unprepare(i2s->clk);
1143
1144 return 0;
1145 }
1146
i2s_runtime_resume(struct device * dev)1147 static int i2s_runtime_resume(struct device *dev)
1148 {
1149 struct i2s_dai *i2s = dev_get_drvdata(dev);
1150 int ret;
1151
1152 ret = clk_prepare_enable(i2s->clk);
1153 if (ret)
1154 return ret;
1155
1156 if (i2s->op_clk) {
1157 ret = clk_prepare_enable(i2s->op_clk);
1158 if (ret) {
1159 clk_disable_unprepare(i2s->clk);
1160 return ret;
1161 }
1162 }
1163
1164 writel(i2s->suspend_i2scon, i2s->addr + I2SCON);
1165 writel(i2s->suspend_i2smod, i2s->addr + I2SMOD);
1166 writel(i2s->suspend_i2spsr, i2s->addr + I2SPSR);
1167
1168 return 0;
1169 }
1170 #endif /* CONFIG_PM */
1171
i2s_unregister_clocks(struct i2s_dai * i2s)1172 static void i2s_unregister_clocks(struct i2s_dai *i2s)
1173 {
1174 int i;
1175
1176 for (i = 0; i < i2s->clk_data.clk_num; i++) {
1177 if (!IS_ERR(i2s->clk_table[i]))
1178 clk_unregister(i2s->clk_table[i]);
1179 }
1180 }
1181
i2s_unregister_clock_provider(struct platform_device * pdev)1182 static void i2s_unregister_clock_provider(struct platform_device *pdev)
1183 {
1184 struct i2s_dai *i2s = dev_get_drvdata(&pdev->dev);
1185
1186 of_clk_del_provider(pdev->dev.of_node);
1187 i2s_unregister_clocks(i2s);
1188 }
1189
i2s_register_clock_provider(struct platform_device * pdev)1190 static int i2s_register_clock_provider(struct platform_device *pdev)
1191 {
1192 struct device *dev = &pdev->dev;
1193 struct i2s_dai *i2s = dev_get_drvdata(dev);
1194 const char *clk_name[2] = { "i2s_opclk0", "i2s_opclk1" };
1195 const char *p_names[2] = { NULL };
1196 const struct samsung_i2s_variant_regs *reg_info = i2s->variant_regs;
1197 struct clk *rclksrc;
1198 int ret, i;
1199
1200 /* Register the clock provider only if it's expected in the DTB */
1201 if (!of_find_property(dev->of_node, "#clock-cells", NULL))
1202 return 0;
1203
1204 /* Get the RCLKSRC mux clock parent clock names */
1205 for (i = 0; i < ARRAY_SIZE(p_names); i++) {
1206 rclksrc = clk_get(dev, clk_name[i]);
1207 if (IS_ERR(rclksrc))
1208 continue;
1209 p_names[i] = __clk_get_name(rclksrc);
1210 clk_put(rclksrc);
1211 }
1212
1213 if (!(i2s->quirks & QUIRK_NO_MUXPSR)) {
1214 /* Activate the prescaler */
1215 u32 val = readl(i2s->addr + I2SPSR);
1216 writel(val | PSR_PSREN, i2s->addr + I2SPSR);
1217
1218 i2s->clk_table[CLK_I2S_RCLK_SRC] = clk_register_mux(dev,
1219 "i2s_rclksrc", p_names, ARRAY_SIZE(p_names),
1220 CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
1221 i2s->addr + I2SMOD, reg_info->rclksrc_off,
1222 1, 0, i2s->lock);
1223
1224 i2s->clk_table[CLK_I2S_RCLK_PSR] = clk_register_divider(dev,
1225 "i2s_presc", "i2s_rclksrc",
1226 CLK_SET_RATE_PARENT,
1227 i2s->addr + I2SPSR, 8, 6, 0, i2s->lock);
1228
1229 p_names[0] = "i2s_presc";
1230 i2s->clk_data.clk_num = 2;
1231 }
1232 of_property_read_string_index(dev->of_node,
1233 "clock-output-names", 0, &clk_name[0]);
1234
1235 i2s->clk_table[CLK_I2S_CDCLK] = clk_register_gate(dev, clk_name[0],
1236 p_names[0], CLK_SET_RATE_PARENT,
1237 i2s->addr + I2SMOD, reg_info->cdclkcon_off,
1238 CLK_GATE_SET_TO_DISABLE, i2s->lock);
1239
1240 i2s->clk_data.clk_num += 1;
1241 i2s->clk_data.clks = i2s->clk_table;
1242
1243 ret = of_clk_add_provider(dev->of_node, of_clk_src_onecell_get,
1244 &i2s->clk_data);
1245 if (ret < 0) {
1246 dev_err(dev, "failed to add clock provider: %d\n", ret);
1247 i2s_unregister_clocks(i2s);
1248 }
1249
1250 return ret;
1251 }
1252
samsung_i2s_probe(struct platform_device * pdev)1253 static int samsung_i2s_probe(struct platform_device *pdev)
1254 {
1255 struct i2s_dai *pri_dai, *sec_dai = NULL;
1256 struct s3c_audio_pdata *i2s_pdata = pdev->dev.platform_data;
1257 struct resource *res;
1258 u32 regs_base, quirks = 0, idma_addr = 0;
1259 struct device_node *np = pdev->dev.of_node;
1260 const struct samsung_i2s_dai_data *i2s_dai_data;
1261 int ret;
1262
1263 if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node)
1264 i2s_dai_data = of_device_get_match_data(&pdev->dev);
1265 else
1266 i2s_dai_data = (struct samsung_i2s_dai_data *)
1267 platform_get_device_id(pdev)->driver_data;
1268
1269 pri_dai = i2s_alloc_dai(pdev, i2s_dai_data, false);
1270 if (!pri_dai) {
1271 dev_err(&pdev->dev, "Unable to alloc I2S_pri\n");
1272 return -ENOMEM;
1273 }
1274
1275 spin_lock_init(&pri_dai->spinlock);
1276 pri_dai->lock = &pri_dai->spinlock;
1277
1278 if (!np) {
1279 if (i2s_pdata == NULL) {
1280 dev_err(&pdev->dev, "Can't work without s3c_audio_pdata\n");
1281 return -EINVAL;
1282 }
1283
1284 pri_dai->dma_playback.filter_data = i2s_pdata->dma_playback;
1285 pri_dai->dma_capture.filter_data = i2s_pdata->dma_capture;
1286 pri_dai->filter = i2s_pdata->dma_filter;
1287
1288 quirks = i2s_pdata->type.quirks;
1289 idma_addr = i2s_pdata->type.idma_addr;
1290 } else {
1291 quirks = i2s_dai_data->quirks;
1292 if (of_property_read_u32(np, "samsung,idma-addr",
1293 &idma_addr)) {
1294 if (quirks & QUIRK_SUPPORTS_IDMA) {
1295 dev_info(&pdev->dev, "idma address is not"\
1296 "specified");
1297 }
1298 }
1299 }
1300
1301 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1302 pri_dai->addr = devm_ioremap_resource(&pdev->dev, res);
1303 if (IS_ERR(pri_dai->addr))
1304 return PTR_ERR(pri_dai->addr);
1305
1306 regs_base = res->start;
1307
1308 pri_dai->clk = devm_clk_get(&pdev->dev, "iis");
1309 if (IS_ERR(pri_dai->clk)) {
1310 dev_err(&pdev->dev, "Failed to get iis clock\n");
1311 return PTR_ERR(pri_dai->clk);
1312 }
1313
1314 ret = clk_prepare_enable(pri_dai->clk);
1315 if (ret != 0) {
1316 dev_err(&pdev->dev, "failed to enable clock: %d\n", ret);
1317 return ret;
1318 }
1319 pri_dai->dma_playback.addr = regs_base + I2STXD;
1320 pri_dai->dma_capture.addr = regs_base + I2SRXD;
1321 pri_dai->dma_playback.chan_name = "tx";
1322 pri_dai->dma_capture.chan_name = "rx";
1323 pri_dai->dma_playback.addr_width = 4;
1324 pri_dai->dma_capture.addr_width = 4;
1325 pri_dai->quirks = quirks;
1326 pri_dai->variant_regs = i2s_dai_data->i2s_variant_regs;
1327
1328 if (quirks & QUIRK_PRI_6CHAN)
1329 pri_dai->i2s_dai_drv.playback.channels_max = 6;
1330
1331 ret = samsung_asoc_dma_platform_register(&pdev->dev, pri_dai->filter,
1332 NULL, NULL);
1333 if (ret < 0)
1334 goto err_disable_clk;
1335
1336 ret = devm_snd_soc_register_component(&pdev->dev,
1337 &samsung_i2s_component,
1338 &pri_dai->i2s_dai_drv, 1);
1339 if (ret < 0)
1340 goto err_disable_clk;
1341
1342 if (quirks & QUIRK_SEC_DAI) {
1343 sec_dai = i2s_alloc_dai(pdev, i2s_dai_data, true);
1344 if (!sec_dai) {
1345 dev_err(&pdev->dev, "Unable to alloc I2S_sec\n");
1346 ret = -ENOMEM;
1347 goto err_disable_clk;
1348 }
1349
1350 sec_dai->lock = &pri_dai->spinlock;
1351 sec_dai->variant_regs = pri_dai->variant_regs;
1352 sec_dai->dma_playback.addr = regs_base + I2STXDS;
1353 sec_dai->dma_playback.chan_name = "tx-sec";
1354
1355 if (!np) {
1356 sec_dai->dma_playback.filter_data = i2s_pdata->dma_play_sec;
1357 sec_dai->filter = i2s_pdata->dma_filter;
1358 }
1359
1360 sec_dai->dma_playback.addr_width = 4;
1361 sec_dai->addr = pri_dai->addr;
1362 sec_dai->clk = pri_dai->clk;
1363 sec_dai->quirks = quirks;
1364 sec_dai->idma_playback.addr = idma_addr;
1365 sec_dai->pri_dai = pri_dai;
1366 pri_dai->sec_dai = sec_dai;
1367
1368 ret = samsung_asoc_dma_platform_register(&pdev->dev,
1369 sec_dai->filter, "tx-sec", NULL);
1370 if (ret < 0)
1371 goto err_disable_clk;
1372
1373 ret = devm_snd_soc_register_component(&pdev->dev,
1374 &samsung_i2s_component,
1375 &sec_dai->i2s_dai_drv, 1);
1376 if (ret < 0)
1377 goto err_disable_clk;
1378 }
1379
1380 if (i2s_pdata && i2s_pdata->cfg_gpio && i2s_pdata->cfg_gpio(pdev)) {
1381 dev_err(&pdev->dev, "Unable to configure gpio\n");
1382 ret = -EINVAL;
1383 goto err_disable_clk;
1384 }
1385
1386 dev_set_drvdata(&pdev->dev, pri_dai);
1387
1388 pm_runtime_set_active(&pdev->dev);
1389 pm_runtime_enable(&pdev->dev);
1390
1391 ret = i2s_register_clock_provider(pdev);
1392 if (!ret)
1393 return 0;
1394
1395 pm_runtime_disable(&pdev->dev);
1396 err_disable_clk:
1397 clk_disable_unprepare(pri_dai->clk);
1398 return ret;
1399 }
1400
samsung_i2s_remove(struct platform_device * pdev)1401 static int samsung_i2s_remove(struct platform_device *pdev)
1402 {
1403 struct i2s_dai *pri_dai;
1404
1405 pri_dai = dev_get_drvdata(&pdev->dev);
1406
1407 pm_runtime_get_sync(&pdev->dev);
1408 pm_runtime_disable(&pdev->dev);
1409
1410 i2s_unregister_clock_provider(pdev);
1411 clk_disable_unprepare(pri_dai->clk);
1412 pm_runtime_put_noidle(&pdev->dev);
1413
1414 return 0;
1415 }
1416
1417 static const struct samsung_i2s_variant_regs i2sv3_regs = {
1418 .bfs_off = 1,
1419 .rfs_off = 3,
1420 .sdf_off = 5,
1421 .txr_off = 8,
1422 .rclksrc_off = 10,
1423 .mss_off = 11,
1424 .cdclkcon_off = 12,
1425 .lrp_off = 7,
1426 .bfs_mask = 0x3,
1427 .rfs_mask = 0x3,
1428 .ftx0cnt_off = 8,
1429 };
1430
1431 static const struct samsung_i2s_variant_regs i2sv6_regs = {
1432 .bfs_off = 0,
1433 .rfs_off = 4,
1434 .sdf_off = 6,
1435 .txr_off = 8,
1436 .rclksrc_off = 10,
1437 .mss_off = 11,
1438 .cdclkcon_off = 12,
1439 .lrp_off = 15,
1440 .bfs_mask = 0xf,
1441 .rfs_mask = 0x3,
1442 .ftx0cnt_off = 8,
1443 };
1444
1445 static const struct samsung_i2s_variant_regs i2sv7_regs = {
1446 .bfs_off = 0,
1447 .rfs_off = 4,
1448 .sdf_off = 7,
1449 .txr_off = 9,
1450 .rclksrc_off = 11,
1451 .mss_off = 12,
1452 .cdclkcon_off = 22,
1453 .lrp_off = 15,
1454 .bfs_mask = 0xf,
1455 .rfs_mask = 0x7,
1456 .ftx0cnt_off = 0,
1457 };
1458
1459 static const struct samsung_i2s_variant_regs i2sv5_i2s1_regs = {
1460 .bfs_off = 0,
1461 .rfs_off = 3,
1462 .sdf_off = 6,
1463 .txr_off = 8,
1464 .rclksrc_off = 10,
1465 .mss_off = 11,
1466 .cdclkcon_off = 12,
1467 .lrp_off = 15,
1468 .bfs_mask = 0x7,
1469 .rfs_mask = 0x7,
1470 .ftx0cnt_off = 8,
1471 };
1472
1473 static const struct samsung_i2s_dai_data i2sv3_dai_type = {
1474 .quirks = QUIRK_NO_MUXPSR,
1475 .pcm_rates = SNDRV_PCM_RATE_8000_96000,
1476 .i2s_variant_regs = &i2sv3_regs,
1477 };
1478
1479 static const struct samsung_i2s_dai_data i2sv5_dai_type = {
1480 .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI | QUIRK_NEED_RSTCLR |
1481 QUIRK_SUPPORTS_IDMA,
1482 .pcm_rates = SNDRV_PCM_RATE_8000_96000,
1483 .i2s_variant_regs = &i2sv3_regs,
1484 };
1485
1486 static const struct samsung_i2s_dai_data i2sv6_dai_type = {
1487 .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI | QUIRK_NEED_RSTCLR |
1488 QUIRK_SUPPORTS_TDM | QUIRK_SUPPORTS_IDMA,
1489 .pcm_rates = SNDRV_PCM_RATE_8000_96000,
1490 .i2s_variant_regs = &i2sv6_regs,
1491 };
1492
1493 static const struct samsung_i2s_dai_data i2sv7_dai_type = {
1494 .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI | QUIRK_NEED_RSTCLR |
1495 QUIRK_SUPPORTS_TDM,
1496 .pcm_rates = SNDRV_PCM_RATE_8000_192000,
1497 .i2s_variant_regs = &i2sv7_regs,
1498 };
1499
1500 static const struct samsung_i2s_dai_data i2sv5_dai_type_i2s1 = {
1501 .quirks = QUIRK_PRI_6CHAN | QUIRK_NEED_RSTCLR,
1502 .pcm_rates = SNDRV_PCM_RATE_8000_96000,
1503 .i2s_variant_regs = &i2sv5_i2s1_regs,
1504 };
1505
1506 static const struct platform_device_id samsung_i2s_driver_ids[] = {
1507 {
1508 .name = "samsung-i2s",
1509 .driver_data = (kernel_ulong_t)&i2sv3_dai_type,
1510 },
1511 {},
1512 };
1513 MODULE_DEVICE_TABLE(platform, samsung_i2s_driver_ids);
1514
1515 #ifdef CONFIG_OF
1516 static const struct of_device_id exynos_i2s_match[] = {
1517 {
1518 .compatible = "samsung,s3c6410-i2s",
1519 .data = &i2sv3_dai_type,
1520 }, {
1521 .compatible = "samsung,s5pv210-i2s",
1522 .data = &i2sv5_dai_type,
1523 }, {
1524 .compatible = "samsung,exynos5420-i2s",
1525 .data = &i2sv6_dai_type,
1526 }, {
1527 .compatible = "samsung,exynos7-i2s",
1528 .data = &i2sv7_dai_type,
1529 }, {
1530 .compatible = "samsung,exynos7-i2s1",
1531 .data = &i2sv5_dai_type_i2s1,
1532 },
1533 {},
1534 };
1535 MODULE_DEVICE_TABLE(of, exynos_i2s_match);
1536 #endif
1537
1538 static const struct dev_pm_ops samsung_i2s_pm = {
1539 SET_RUNTIME_PM_OPS(i2s_runtime_suspend,
1540 i2s_runtime_resume, NULL)
1541 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1542 pm_runtime_force_resume)
1543 };
1544
1545 static struct platform_driver samsung_i2s_driver = {
1546 .probe = samsung_i2s_probe,
1547 .remove = samsung_i2s_remove,
1548 .id_table = samsung_i2s_driver_ids,
1549 .driver = {
1550 .name = "samsung-i2s",
1551 .of_match_table = of_match_ptr(exynos_i2s_match),
1552 .pm = &samsung_i2s_pm,
1553 },
1554 };
1555
1556 module_platform_driver(samsung_i2s_driver);
1557
1558 /* Module information */
1559 MODULE_AUTHOR("Jaswinder Singh, <jassisinghbrar@gmail.com>");
1560 MODULE_DESCRIPTION("Samsung I2S Interface");
1561 MODULE_ALIAS("platform:samsung-i2s");
1562 MODULE_LICENSE("GPL");
1563