Lines Matching refs:vulp
191 t2_cfg = *(vulp)T2_HAE_3 & ~0xc0000000UL; in conf_read()
192 *(vulp)T2_HAE_3 = 0x40000000UL | t2_cfg; in conf_read()
226 *(vulp)T2_HAE_3 = t2_cfg; in conf_read()
243 t2_cfg = *(vulp)T2_HAE_3 & ~0xc0000000UL; in conf_write()
244 *(vulp)T2_HAE_3 = t2_cfg | 0x40000000UL; in conf_write()
277 *(vulp)T2_HAE_3 = t2_cfg; in conf_write()
333 *(vulp)T2_WBASE1 = temp | 0x80000UL; /* OR in ENABLE bit */ in t2_direct_map_window1()
335 *(vulp)T2_WMASK1 = temp; in t2_direct_map_window1()
336 *(vulp)T2_TBASE1 = 0; in t2_direct_map_window1()
340 __func__, *(vulp)T2_WBASE1, *(vulp)T2_WMASK1, *(vulp)T2_TBASE1); in t2_direct_map_window1()
357 *(vulp)T2_WBASE2 = temp | 0xc0000UL; /* OR in ENABLE/SG bits */ in t2_sg_map_window2()
359 *(vulp)T2_WMASK2 = temp; in t2_sg_map_window2()
360 *(vulp)T2_TBASE2 = virt_to_phys(hose->sg_isa->ptes) >> 1; in t2_sg_map_window2()
367 __func__, *(vulp)T2_WBASE2, *(vulp)T2_WMASK2, *(vulp)T2_TBASE2); in t2_sg_map_window2()
376 printk("%s: HAE_2 was 0x%lx\n", __func__, *(vulp)T2_HAE_2); in t2_save_configuration()
377 printk("%s: HAE_3 was 0x%lx\n", __func__, *(vulp)T2_HAE_3); in t2_save_configuration()
378 printk("%s: HAE_4 was 0x%lx\n", __func__, *(vulp)T2_HAE_4); in t2_save_configuration()
379 printk("%s: HBASE was 0x%lx\n", __func__, *(vulp)T2_HBASE); in t2_save_configuration()
382 *(vulp)T2_WBASE1, *(vulp)T2_WMASK1, *(vulp)T2_TBASE1); in t2_save_configuration()
384 *(vulp)T2_WBASE2, *(vulp)T2_WMASK2, *(vulp)T2_TBASE2); in t2_save_configuration()
390 t2_saved_config.window[0].wbase = *(vulp)T2_WBASE1; in t2_save_configuration()
391 t2_saved_config.window[0].wmask = *(vulp)T2_WMASK1; in t2_save_configuration()
392 t2_saved_config.window[0].tbase = *(vulp)T2_TBASE1; in t2_save_configuration()
393 t2_saved_config.window[1].wbase = *(vulp)T2_WBASE2; in t2_save_configuration()
394 t2_saved_config.window[1].wmask = *(vulp)T2_WMASK2; in t2_save_configuration()
395 t2_saved_config.window[1].tbase = *(vulp)T2_TBASE2; in t2_save_configuration()
398 t2_saved_config.hae_2 = *(vulp)T2_HAE_2; in t2_save_configuration()
399 t2_saved_config.hae_3 = *(vulp)T2_HAE_3; in t2_save_configuration()
400 t2_saved_config.hae_4 = *(vulp)T2_HAE_4; in t2_save_configuration()
401 t2_saved_config.hbase = *(vulp)T2_HBASE; in t2_save_configuration()
420 temp = *(vulp)T2_IOCSR; in t2_init_arch()
424 *(vulp)T2_IOCSR = temp | (0x1UL << 26); in t2_init_arch()
426 *(vulp)T2_IOCSR; /* read it back to make sure */ in t2_init_arch()
462 *(vulp)T2_HBASE = 0x0; /* Disable HOLES. */ in t2_init_arch()
465 *(vulp)T2_HAE_1 = 0; mb(); /* Sparse MEM HAE */ in t2_init_arch()
466 *(vulp)T2_HAE_2 = 0; mb(); /* Sparse I/O HAE */ in t2_init_arch()
467 *(vulp)T2_HAE_3 = 0; mb(); /* Config Space HAE */ in t2_init_arch()
478 *(vulp)T2_HAE_4 = 0; mb(); in t2_init_arch()
487 *(vulp)T2_WBASE1 = t2_saved_config.window[0].wbase; in t2_kill_arch()
488 *(vulp)T2_WMASK1 = t2_saved_config.window[0].wmask; in t2_kill_arch()
489 *(vulp)T2_TBASE1 = t2_saved_config.window[0].tbase; in t2_kill_arch()
490 *(vulp)T2_WBASE2 = t2_saved_config.window[1].wbase; in t2_kill_arch()
491 *(vulp)T2_WMASK2 = t2_saved_config.window[1].wmask; in t2_kill_arch()
492 *(vulp)T2_TBASE2 = t2_saved_config.window[1].tbase; in t2_kill_arch()
495 *(vulp)T2_HAE_1 = srm_hae; in t2_kill_arch()
496 *(vulp)T2_HAE_2 = t2_saved_config.hae_2; in t2_kill_arch()
497 *(vulp)T2_HAE_3 = t2_saved_config.hae_3; in t2_kill_arch()
498 *(vulp)T2_HAE_4 = t2_saved_config.hae_4; in t2_kill_arch()
499 *(vulp)T2_HBASE = t2_saved_config.hbase; in t2_kill_arch()
501 *(vulp)T2_HBASE; /* READ it back to ensure WRITE occurred. */ in t2_kill_arch()
509 t2_iocsr = *(vulp)T2_IOCSR; in t2_pci_tbi()
512 *(vulp)T2_IOCSR = t2_iocsr | (0x1UL << 28); in t2_pci_tbi()
514 *(vulp)T2_IOCSR; /* read it back to make sure */ in t2_pci_tbi()
517 *(vulp)T2_IOCSR = t2_iocsr & ~(0x1UL << 28); in t2_pci_tbi()
519 *(vulp)T2_IOCSR; /* read it back to make sure */ in t2_pci_tbi()
539 *(vulp)T2_CERR1 |= *(vulp)T2_CERR1; in t2_clear_errors()
540 *(vulp)T2_PERR1 |= *(vulp)T2_PERR1; in t2_clear_errors()