Lines Matching refs:clks
54 clocks = <&clks IMX5_CLK_ARM>;
120 clocks = <&clks IMX5_CLK_SATA_GATE>,
121 <&clks IMX5_CLK_SATA_REF>,
122 <&clks IMX5_CLK_AHB>;
133 clocks = <&clks IMX5_CLK_IPU_GATE>,
134 <&clks IMX5_CLK_IPU_DI0_GATE>,
135 <&clks IMX5_CLK_IPU_DI1_GATE>;
193 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
194 <&clks IMX5_CLK_DUMMY>,
195 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
205 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
206 <&clks IMX5_CLK_DUMMY>,
207 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
217 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
218 <&clks IMX5_CLK_UART3_PER_GATE>;
229 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
230 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
242 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>,
243 <&clks IMX5_CLK_SSI2_ROOT_GATE>;
256 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
257 <&clks IMX5_CLK_DUMMY>,
258 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
268 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
269 <&clks IMX5_CLK_DUMMY>,
270 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
284 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
291 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
300 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
310 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
321 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
331 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
341 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
388 clocks = <&clks IMX5_CLK_DUMMY>;
396 clocks = <&clks IMX5_CLK_DUMMY>;
403 clocks = <&clks IMX5_CLK_DUMMY>;
411 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
412 <&clks IMX5_CLK_GPT_HF_GATE>;
432 clocks = <&clks IMX5_CLK_LDB_DI0_SEL>,
433 <&clks IMX5_CLK_LDB_DI1_SEL>,
434 <&clks IMX5_CLK_IPU_DI0_SEL>,
435 <&clks IMX5_CLK_IPU_DI1_SEL>,
436 <&clks IMX5_CLK_LDB_DI0_GATE>,
437 <&clks IMX5_CLK_LDB_DI1_GATE>;
478 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
479 <&clks IMX5_CLK_PWM1_HF_GATE>;
488 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
489 <&clks IMX5_CLK_PWM2_HF_GATE>;
498 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
499 <&clks IMX5_CLK_UART1_PER_GATE>;
508 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
509 <&clks IMX5_CLK_UART2_PER_GATE>;
518 clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>,
519 <&clks IMX5_CLK_CAN1_SERIAL_GATE>;
528 clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>,
529 <&clks IMX5_CLK_CAN2_SERIAL_GATE>;
540 clks: ccm@53fd4000{ label
583 clocks = <&clks IMX5_CLK_I2C3_GATE>;
591 clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
592 <&clks IMX5_CLK_UART4_PER_GATE>;
614 clocks = <&clks IMX5_CLK_IIM_GATE>;
621 clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
622 <&clks IMX5_CLK_UART5_PER_GATE>;
630 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
640 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
641 <&clks IMX5_CLK_ECSPI2_PER_GATE>;
650 clocks = <&clks IMX5_CLK_SDMA_GATE>,
651 <&clks IMX5_CLK_SDMA_GATE>;
663 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
664 <&clks IMX5_CLK_CSPI_IPG_GATE>;
675 clocks = <&clks IMX5_CLK_I2C2_GATE>;
685 clocks = <&clks IMX5_CLK_I2C1_GATE>;
695 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>,
696 <&clks IMX5_CLK_SSI1_ROOT_GATE>;
715 clocks = <&clks IMX5_CLK_NFC_GATE>;
725 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>,
726 <&clks IMX5_CLK_SSI3_ROOT_GATE>;
739 clocks = <&clks IMX5_CLK_FEC_GATE>,
740 <&clks IMX5_CLK_FEC_GATE>,
741 <&clks IMX5_CLK_FEC_GATE>;
750 clocks = <&clks IMX5_CLK_TVE_GATE>,
751 <&clks IMX5_CLK_IPU_DI1_SEL>;
766 clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>,
767 <&clks IMX5_CLK_VPU_GATE>;
777 clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>,
778 <&clks IMX5_CLK_SAHARA_IPG_GATE>;
786 clocks = <&clks IMX5_CLK_OCRAM>;