Lines Matching refs:rp
54 #define checkuart(rp, rv, lhu, bit, uart) \ argument
56 ldr rp, =TEGRA_CLK_RST_DEVICES_##lhu ; \
58 ldr rp, [rp, #0] ; \
60 tst rp, #(1 << bit) ; \
64 ldr rp, =TEGRA_CLK_OUT_ENB_##lhu ; \
66 ldr rp, [rp, #0] ; \
68 tst rp, #(1 << bit) ; \
72 ldr rp, =TEGRA_UART##uart##_BASE ; \
76 .macro addruart, rp, rv, tmp
77 adr \rp, 99f @ actual addr of 99f
78 ldr \rv, [\rp] @ linked addr is stored there
79 sub \rv, \rv, \rp @ offset between the two
80 ldr \rp, [\rp, #4] @ linked tegra_uart_config
81 sub \tmp, \rp, \rv @ actual tegra_uart_config
82 ldr \rp, [\tmp] @ Load tegra_uart_config
83 cmp \rp, #1 @ needs initialization?
90 10: ldr \rp, =TEGRA_PMC_SCRATCH20
91 ldr \rp, [\rp, #0] @ Load PMC_SCRATCH20
92 lsr \rv, \rp, #18 @ 19:18 are console type
98 11: lsr \rv, \rp, #15 @ 17:15 are UART ID
116 20: checkuart(\rp, \rv, L, 6, A)
122 21: checkuart(\rp, \rv, L, 7, B)
128 22: checkuart(\rp, \rv, H, 23, C)
134 23: checkuart(\rp, \rv, U, 1, D)
141 checkuart(\rp, \rv, U, 2, E)
145 90: mov \rp, #0
149 91: str \rp, [\tmp, #4] @ Store in tegra_uart_phys
150 cmp \rp, #0 @ Valid UART address?
152 str \rp, [\tmp, #8] @ Store 0 in tegra_uart_virt
154 92: and \rv, \rp, #0xffffff @ offset within 1MB section
165 100: ldr \rp, [\tmp, #4] @ Load tegra_uart_phys