Lines Matching refs:NR_IRQS_LEGACY

147 #define MX3x_INT_I2C3		(NR_IRQS_LEGACY + 3)
148 #define MX3x_INT_I2C2		(NR_IRQS_LEGACY + 4)
149 #define MX3x_INT_RTIC		(NR_IRQS_LEGACY + 6)
150 #define MX3x_INT_I2C		(NR_IRQS_LEGACY + 10)
151 #define MX3x_INT_CSPI2		(NR_IRQS_LEGACY + 13)
152 #define MX3x_INT_CSPI1		(NR_IRQS_LEGACY + 14)
153 #define MX3x_INT_ATA		(NR_IRQS_LEGACY + 15)
154 #define MX3x_INT_UART3		(NR_IRQS_LEGACY + 18)
155 #define MX3x_INT_IIM		(NR_IRQS_LEGACY + 19)
156 #define MX3x_INT_RNGA		(NR_IRQS_LEGACY + 22)
157 #define MX3x_INT_EVTMON		(NR_IRQS_LEGACY + 23)
158 #define MX3x_INT_KPP		(NR_IRQS_LEGACY + 24)
159 #define MX3x_INT_RTC		(NR_IRQS_LEGACY + 25)
160 #define MX3x_INT_PWM		(NR_IRQS_LEGACY + 26)
161 #define MX3x_INT_EPIT2		(NR_IRQS_LEGACY + 27)
162 #define MX3x_INT_EPIT1		(NR_IRQS_LEGACY + 28)
163 #define MX3x_INT_GPT		(NR_IRQS_LEGACY + 29)
164 #define MX3x_INT_POWER_FAIL	(NR_IRQS_LEGACY + 30)
165 #define MX3x_INT_UART2		(NR_IRQS_LEGACY + 32)
166 #define MX3x_INT_NANDFC		(NR_IRQS_LEGACY + 33)
167 #define MX3x_INT_SDMA		(NR_IRQS_LEGACY + 34)
168 #define MX3x_INT_MSHC1		(NR_IRQS_LEGACY + 39)
169 #define MX3x_INT_IPU_ERR	(NR_IRQS_LEGACY + 41)
170 #define MX3x_INT_IPU_SYN	(NR_IRQS_LEGACY + 42)
171 #define MX3x_INT_UART1		(NR_IRQS_LEGACY + 45)
172 #define MX3x_INT_ECT		(NR_IRQS_LEGACY + 48)
173 #define MX3x_INT_SCC_SCM	(NR_IRQS_LEGACY + 49)
174 #define MX3x_INT_SCC_SMN	(NR_IRQS_LEGACY + 50)
175 #define MX3x_INT_GPIO2		(NR_IRQS_LEGACY + 51)
176 #define MX3x_INT_GPIO1		(NR_IRQS_LEGACY + 52)
177 #define MX3x_INT_WDOG		(NR_IRQS_LEGACY + 55)
178 #define MX3x_INT_GPIO3		(NR_IRQS_LEGACY + 56)
179 #define MX3x_INT_EXT_POWER	(NR_IRQS_LEGACY + 58)
180 #define MX3x_INT_EXT_TEMPER	(NR_IRQS_LEGACY + 59)
181 #define MX3x_INT_EXT_SENSOR60	(NR_IRQS_LEGACY + 60)
182 #define MX3x_INT_EXT_SENSOR61	(NR_IRQS_LEGACY + 61)
183 #define MX3x_INT_EXT_WDOG	(NR_IRQS_LEGACY + 62)
184 #define MX3x_INT_EXT_TV		(NR_IRQS_LEGACY + 63)