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Lines Matching refs:mcr

67 	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
83 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
84 mcr p15, 0, ip, c7, c10, 4 @ drain WB
86 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
91 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
105 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
110 mcr p15, 0, r2, c1, c0, 0 @ Disable I cache
111 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
112 mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable
123 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
146 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
173 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
176 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
180 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
183 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
218 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
219 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
223 mcr p15, 0, r0, c7, c10, 4 @ drain WB
238 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
243 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
244 mcr p15, 0, r0, c7, c10, 4 @ drain WB
268 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
272 mcr p15, 0, r0, c7, c10, 4 @ drain WB
288 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
293 mcr p15, 0, r0, c7, c10, 4 @ drain WB
308 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
310 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
315 mcr p15, 0, r0, c7, c10, 4 @ drain WB
350 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
355 mcr p15, 0, r0, c7, c10, 4 @ drain WB
372 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
378 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
379 mcr p15, 0, ip, c7, c10, 4 @ drain WB
380 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
381 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
396 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
398 mcr p15, 0, r0, c7, c10, 4 @ drain WB
417 mcr p15, 0, ip, c8, c7, 0 @ invalidate I+D TLBs
418 mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches
420 mcr p15, 0, r4, c13, c0, 0 @ PID
421 mcr p15, 0, r5, c3, c0, 0 @ Domain ID
422 mcr p15, 0, r1, c2, c0, 0 @ TTB address
431 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
432 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
434 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
440 mcr p15, 7, r0, c15, c0, 0