Lines Matching refs:mcr
44 mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching
45 mcr p15, 0, r0, c9, c0, 5 @ Allow read-buffer operations from userland
56 mcr p15, 0, ip, c15, c2, 2 @ Disable clock switching
60 mcr p15, 0, r0, c1, c0, 0 @ disable caches
76 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
77 mcr p15, 0, ip, c7, c10, 4 @ drain WB
79 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
84 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
111 mcr p15, 0, r0, c15, c2, 2 @ disable clock switching
113 mcr p15, 0, r0, c15, c8, 2 @ wait for interrupt
115 mcr p15, 0, r0, c15, c1, 2 @ enable clock switching
130 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
150 mcr p15, 0, ip, c9, c0, 0 @ invalidate RB
151 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
152 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
168 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
169 mcr p15, 0, r0, c7, c10, 4 @ drain WB
188 mcr p15, 0, ip, c8, c7, 0 @ flush I+D TLBs
189 mcr p15, 0, ip, c7, c7, 0 @ flush I&D cache
190 mcr p15, 0, ip, c9, c0, 0 @ invalidate RB
191 mcr p15, 0, ip, c9, c0, 5 @ allow user space to use RB
193 mcr p15, 0, r4, c3, c0, 0 @ domain ID
194 mcr p15, 0, r1, c2, c0, 0 @ translation table base addr
195 mcr p15, 0, r5, c13, c0, 0 @ PID
204 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
205 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
207 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4