Lines Matching refs:x2
46 add x3, x2, #CPU_XREG_OFFSET(19)
65 str x22, [x2, #CPU_GP_REG_OFFSET(CPU_SP_EL1)]
66 str x23, [x2, #CPU_GP_REG_OFFSET(CPU_ELR_EL1)]
67 str x24, [x2, #CPU_SPSR_OFFSET(KVM_SPSR_EL1)]
74 ldr x22, [x2, #CPU_GP_REG_OFFSET(CPU_SP_EL1)]
75 ldr x23, [x2, #CPU_GP_REG_OFFSET(CPU_ELR_EL1)]
76 ldr x24, [x2, #CPU_SPSR_OFFSET(KVM_SPSR_EL1)]
82 add x3, x2, #CPU_XREG_OFFSET(31) // SP_EL0
90 add x3, x2, #CPU_XREG_OFFSET(19)
110 add x3, x2, #CPU_GP_REG_OFFSET(CPU_FP_REGS)
117 add x3, x2, #CPU_GP_REG_OFFSET(CPU_FP_REGS)
129 add x3, x2, #CPU_XREG_OFFSET(4)
142 add x3, x2, #CPU_XREG_OFFSET(0)
155 add x3, x2, #CPU_XREG_OFFSET(0)
175 pop x2, x3
195 add x3, x2, #CPU_SYSREG_OFFSET(MPIDR_EL1)
285 add x3, x2, #CPU_SYSREG_OFFSET(MPIDR_EL1)
423 add x3, x2, #CPU_SPSR_OFFSET(KVM_SPSR_ABT)
431 add x3, x2, #CPU_SYSREG_OFFSET(DACR32_EL2)
449 add x3, x2, #CPU_SPSR_OFFSET(KVM_SPSR_ABT)
457 add x3, x2, #CPU_SYSREG_OFFSET(DACR32_EL2)
469 ldr x2, [x0, #VCPU_HCR_EL2]
478 tbnz x2, #HCR_RW_SHIFT, 99f // open code skip_32bit_state
483 msr hcr_el2, x2
484 mov x2, #CPTR_EL2_TTA
485 orr x2, x2, #CPTR_EL2_TFP
486 msr cptr_el2, x2
488 mov x2, #(1 << 15) // Trap CP15 Cr=15
489 msr hstr_el2, x2
492 ldr x2, [x0, #VCPU_MDCR_EL2]
493 msr mdcr_el2, x2
497 mov_q x2, HCR_HOST_NVHE_FLAGS
498 msr hcr_el2, x2
501 mrs x2, mdcr_el2
502 and x2, x2, #MDCR_EL2_HPMN_MASK
503 msr mdcr_el2, x2
509 ldr x2, [x1, #KVM_VTTBR]
510 msr vttbr_el2, x2
551 ldr x2, [x0, #VCPU_KVM]
552 kern_hyp_va x2
553 ldr w3, [x2, #KVM_TIMER_ENABLED]
570 mrs x2, cnthctl_el2
571 orr x2, x2, #3
572 msr cnthctl_el2, x2
582 mrs x2, cnthctl_el2
583 orr x2, x2, #1
584 bic x2, x2, #2
585 msr cnthctl_el2, x2
587 ldr x2, [x0, #VCPU_KVM]
588 kern_hyp_va x2
589 ldr w3, [x2, #KVM_TIMER_ENABLED]
592 ldr x3, [x2, #KVM_TIMER_CNTVOFF]
594 ldr x2, [x0, #VCPU_TIMER_CNTV_CVAL]
595 msr cntv_cval_el0, x2
599 and x2, x2, #3
600 msr cntv_ctl_el0, x2
638 str x21, [x2, #CPU_SYSREG_OFFSET(MDCCINT_EL1)]
666 ldr x21, [x2, #CPU_SYSREG_OFFSET(MDCCINT_EL1)]
684 mrs x2, cptr_el2
685 bic x2, x2, #CPTR_EL2_TFP
686 msr cptr_el2, x2
691 ldr x2, [x0, #VCPU_HOST_CONTEXT]
692 kern_hyp_va x2
695 add x2, x0, #VCPU_CONTEXT
699 ldr x4, [x2, #CPU_SYSREG_OFFSET(FPEXC32_EL2)]
703 pop x2, x3
724 ldr x2, [x0, #VCPU_HOST_CONTEXT]
725 kern_hyp_va x2
741 add x2, x0, #VCPU_CONTEXT
763 add x2, x0, #VCPU_CONTEXT
783 ldr x2, [x0, #VCPU_HOST_CONTEXT]
784 kern_hyp_va x2
810 ldr x2, [x0, #KVM_VTTBR]
811 msr vttbr_el2, x2
846 ldr x2, [x0, #KVM_VTTBR]
847 msr vttbr_el2, x2
882 ldr x2, [x0, #VCPU_HOST_CONTEXT]
883 kern_hyp_va x2
891 ldr x22, [x2, #CPU_GP_REG_OFFSET(CPU_SP_EL1)]
897 ldp x2, x3, [x1]
898 sub x0, x0, x2
901 mrs x2, elr_el2
971 push x2, x3
974 lsr x2, x1, #ESR_ELx_EC_SHIFT
976 cmp x2, #ESR_ELx_EC_HVC64
983 pop x2, x3
999 mov x1, x2
1000 mov x2, x3
1013 cmp x2, #ESR_ELx_EC_FP_ASIMD
1016 cmp x2, #ESR_ELx_EC_DABT_LOW
1018 ccmp x2, x0, #4, ne
1023 and x2, x1, #ESR_ELx_FSC_TYPE
1024 cmp x2, #FSC_PERM
1049 mrs x2, far_el2
1050 at s1e1r, x2
1063 mrs x2, far_el2
1067 str x2, [x0, #VCPU_FAR_EL2]
1078 3: pop x2, x3
1085 push x2, x3