Lines Matching refs:BFIN_IRQ
14 #define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
15 #define IRQ_DMA1_ERROR BFIN_IRQ(1) /* DMA1 Error (general) */
17 #define IRQ_DMA2_ERROR BFIN_IRQ(2) /* DMA2 Error (general) */
18 #define IRQ_IMDMA_ERROR BFIN_IRQ(3) /* IMDMA Error Interrupt */
19 #define IRQ_PPI1_ERROR BFIN_IRQ(4) /* PPI1 Error Interrupt */
21 #define IRQ_PPI2_ERROR BFIN_IRQ(5) /* PPI2 Error Interrupt */
22 #define IRQ_SPORT0_ERROR BFIN_IRQ(6) /* SPORT0 Error Interrupt */
23 #define IRQ_SPORT1_ERROR BFIN_IRQ(7) /* SPORT1 Error Interrupt */
24 #define IRQ_SPI_ERROR BFIN_IRQ(8) /* SPI Error Interrupt */
25 #define IRQ_UART_ERROR BFIN_IRQ(9) /* UART Error Interrupt */
26 #define IRQ_RESERVED_ERROR BFIN_IRQ(10) /* Reversed */
27 #define IRQ_DMA1_0 BFIN_IRQ(11) /* DMA1 0 Interrupt(PPI1) */
30 #define IRQ_DMA1_1 BFIN_IRQ(12) /* DMA1 1 Interrupt(PPI2) */
32 #define IRQ_DMA1_2 BFIN_IRQ(13) /* DMA1 2 Interrupt */
33 #define IRQ_DMA1_3 BFIN_IRQ(14) /* DMA1 3 Interrupt */
34 #define IRQ_DMA1_4 BFIN_IRQ(15) /* DMA1 4 Interrupt */
35 #define IRQ_DMA1_5 BFIN_IRQ(16) /* DMA1 5 Interrupt */
36 #define IRQ_DMA1_6 BFIN_IRQ(17) /* DMA1 6 Interrupt */
37 #define IRQ_DMA1_7 BFIN_IRQ(18) /* DMA1 7 Interrupt */
38 #define IRQ_DMA1_8 BFIN_IRQ(19) /* DMA1 8 Interrupt */
39 #define IRQ_DMA1_9 BFIN_IRQ(20) /* DMA1 9 Interrupt */
40 #define IRQ_DMA1_10 BFIN_IRQ(21) /* DMA1 10 Interrupt */
41 #define IRQ_DMA1_11 BFIN_IRQ(22) /* DMA1 11 Interrupt */
42 #define IRQ_DMA2_0 BFIN_IRQ(23) /* DMA2 0 (SPORT0 RX) */
44 #define IRQ_DMA2_1 BFIN_IRQ(24) /* DMA2 1 (SPORT0 TX) */
46 #define IRQ_DMA2_2 BFIN_IRQ(25) /* DMA2 2 (SPORT1 RX) */
48 #define IRQ_DMA2_3 BFIN_IRQ(26) /* DMA2 3 (SPORT2 TX) */
50 #define IRQ_DMA2_4 BFIN_IRQ(27) /* DMA2 4 (SPI) */
52 #define IRQ_DMA2_5 BFIN_IRQ(28) /* DMA2 5 (UART RX) */
54 #define IRQ_DMA2_6 BFIN_IRQ(29) /* DMA2 6 (UART TX) */
56 #define IRQ_DMA2_7 BFIN_IRQ(30) /* DMA2 7 Interrupt */
57 #define IRQ_DMA2_8 BFIN_IRQ(31) /* DMA2 8 Interrupt */
58 #define IRQ_DMA2_9 BFIN_IRQ(32) /* DMA2 9 Interrupt */
59 #define IRQ_DMA2_10 BFIN_IRQ(33) /* DMA2 10 Interrupt */
60 #define IRQ_DMA2_11 BFIN_IRQ(34) /* DMA2 11 Interrupt */
61 #define IRQ_TIMER0 BFIN_IRQ(35) /* TIMER 0 Interrupt */
62 #define IRQ_TIMER1 BFIN_IRQ(36) /* TIMER 1 Interrupt */
63 #define IRQ_TIMER2 BFIN_IRQ(37) /* TIMER 2 Interrupt */
64 #define IRQ_TIMER3 BFIN_IRQ(38) /* TIMER 3 Interrupt */
65 #define IRQ_TIMER4 BFIN_IRQ(39) /* TIMER 4 Interrupt */
66 #define IRQ_TIMER5 BFIN_IRQ(40) /* TIMER 5 Interrupt */
67 #define IRQ_TIMER6 BFIN_IRQ(41) /* TIMER 6 Interrupt */
68 #define IRQ_TIMER7 BFIN_IRQ(42) /* TIMER 7 Interrupt */
69 #define IRQ_TIMER8 BFIN_IRQ(43) /* TIMER 8 Interrupt */
70 #define IRQ_TIMER9 BFIN_IRQ(44) /* TIMER 9 Interrupt */
71 #define IRQ_TIMER10 BFIN_IRQ(45) /* TIMER 10 Interrupt */
72 #define IRQ_TIMER11 BFIN_IRQ(46) /* TIMER 11 Interrupt */
73 #define IRQ_PROG0_INTA BFIN_IRQ(47) /* Programmable Flags0 A (8) */
75 #define IRQ_PROG0_INTB BFIN_IRQ(48) /* Programmable Flags0 B (8) */
77 #define IRQ_PROG1_INTA BFIN_IRQ(49) /* Programmable Flags1 A (8) */
78 #define IRQ_PROG1_INTB BFIN_IRQ(50) /* Programmable Flags1 B (8) */
79 #define IRQ_PROG2_INTA BFIN_IRQ(51) /* Programmable Flags2 A (8) */
80 #define IRQ_PROG2_INTB BFIN_IRQ(52) /* Programmable Flags2 B (8) */
81 #define IRQ_DMA1_WRRD0 BFIN_IRQ(53) /* MDMA1 0 write/read INT */
84 #define IRQ_DMA1_WRRD1 BFIN_IRQ(54) /* MDMA1 1 write/read INT */
87 #define IRQ_DMA2_WRRD0 BFIN_IRQ(55) /* MDMA2 0 write/read INT */
89 #define IRQ_DMA2_WRRD1 BFIN_IRQ(56) /* MDMA2 1 write/read INT */
91 #define IRQ_IMDMA_WRRD0 BFIN_IRQ(57) /* IMDMA 0 write/read INT */
93 #define IRQ_IMDMA_WRRD1 BFIN_IRQ(58) /* IMDMA 1 write/read INT */
95 #define IRQ_WATCH BFIN_IRQ(59) /* Watch Dog Timer */
96 #define IRQ_RESERVED_1 BFIN_IRQ(60) /* Reserved interrupt */
97 #define IRQ_RESERVED_2 BFIN_IRQ(61) /* Reserved interrupt */
98 #define IRQ_SUPPLE_0 BFIN_IRQ(62) /* Supplemental interrupt 0 */
99 #define IRQ_SUPPLE_1 BFIN_IRQ(63) /* supplemental interrupt 1 */