Lines Matching refs:IO_STATE
17 #define START_ETHERNET_CLOCK IO_STATE(R_NETWORK_GEN_CONFIG, enable, on) |\
18 IO_STATE(R_NETWORK_GEN_CONFIG, phy, mii_clk)
363 or.d IO_STATE (R_GEN_CONFIG, ser2, select),$r0
365 or.d IO_STATE (R_GEN_CONFIG, ser2, disable),$r0
369 or.d IO_STATE (R_GEN_CONFIG, scsi0, disable) \
370 | IO_STATE (R_GEN_CONFIG, ata, disable) \
371 | IO_STATE (R_GEN_CONFIG, par0, disable) \
372 | IO_STATE (R_GEN_CONFIG, mio, disable) \
373 | IO_STATE (R_GEN_CONFIG, scsi1, disable) \
374 | IO_STATE (R_GEN_CONFIG, scsi0w, disable) \
375 | IO_STATE (R_GEN_CONFIG, par1, disable) \
376 | IO_STATE (R_GEN_CONFIG, ser3, disable) \
377 | IO_STATE (R_GEN_CONFIG, mio_w, disable) \
378 | IO_STATE (R_GEN_CONFIG, usb1, disable) \
379 | IO_STATE (R_GEN_CONFIG, usb2, disable) \
380 | IO_STATE (R_GEN_CONFIG, par_w, disable),$r0
383 or.d IO_STATE (R_GEN_CONFIG, dma2, ata) \
384 | IO_STATE (R_GEN_CONFIG, dma3, ata) \
385 | IO_STATE (R_GEN_CONFIG, dma4, scsi1) \
386 | IO_STATE (R_GEN_CONFIG, dma5, scsi1) \
387 | IO_STATE (R_GEN_CONFIG, dma6, unused) \
388 | IO_STATE (R_GEN_CONFIG, dma7, unused) \
389 | IO_STATE (R_GEN_CONFIG, dma8, usb) \
390 | IO_STATE (R_GEN_CONFIG, dma9, usb),$r0
413 moveq IO_STATE (R_DMA_CH8_CMD, cmd, reset),$r0
418 cmpq IO_STATE (R_DMA_CH8_CMD, cmd, reset),$r0
423 cmpq IO_STATE (R_DMA_CH9_CMD, cmd, reset),$r0
457 moveq IO_STATE (R_SERIAL0_XOFF, tx_stop, enable) \
458 | IO_STATE (R_SERIAL0_XOFF, auto_xoff, disable) \
463 move.b IO_STATE (R_SERIAL0_BAUD, tr_baud, c115k2Hz) \
464 | IO_STATE (R_SERIAL0_BAUD, rec_baud, c115k2Hz),$r0
468 move.b IO_STATE (R_SERIAL0_REC_CTRL, dma_err, stop) \
469 | IO_STATE (R_SERIAL0_REC_CTRL, rec_enable, enable) \
470 | IO_STATE (R_SERIAL0_REC_CTRL, rts_, active) \
471 | IO_STATE (R_SERIAL0_REC_CTRL, sampling, middle) \
472 | IO_STATE (R_SERIAL0_REC_CTRL, rec_stick_par, normal) \
473 | IO_STATE (R_SERIAL0_REC_CTRL, rec_par, even) \
474 | IO_STATE (R_SERIAL0_REC_CTRL, rec_par_en, disable) \
475 | IO_STATE (R_SERIAL0_REC_CTRL, rec_bitnr, rec_8bit),$r0
480 | IO_STATE (R_SERIAL0_TR_CTRL, tr_enable, enable) \
481 | IO_STATE (R_SERIAL0_TR_CTRL, auto_cts, disabled) \
482 | IO_STATE (R_SERIAL0_TR_CTRL, stop_bits, one_bit) \
483 | IO_STATE (R_SERIAL0_TR_CTRL, tr_stick_par, normal) \
484 | IO_STATE (R_SERIAL0_TR_CTRL, tr_par, even) \
485 | IO_STATE (R_SERIAL0_TR_CTRL, tr_par_en, disable) \
486 | IO_STATE (R_SERIAL0_TR_CTRL, tr_bitnr, tr_8bit),$r0
491 moveq IO_STATE (R_SERIAL1_XOFF, tx_stop, enable) \
492 | IO_STATE (R_SERIAL1_XOFF, auto_xoff, disable) \
497 move.b IO_STATE (R_SERIAL1_BAUD, tr_baud, c115k2Hz) \
498 | IO_STATE (R_SERIAL1_BAUD, rec_baud, c115k2Hz),$r0
502 move.b IO_STATE (R_SERIAL1_REC_CTRL, dma_err, stop) \
503 | IO_STATE (R_SERIAL1_REC_CTRL, rec_enable, enable) \
504 | IO_STATE (R_SERIAL1_REC_CTRL, rts_, active) \
505 | IO_STATE (R_SERIAL1_REC_CTRL, sampling, middle) \
506 | IO_STATE (R_SERIAL1_REC_CTRL, rec_stick_par, normal) \
507 | IO_STATE (R_SERIAL1_REC_CTRL, rec_par, even) \
508 | IO_STATE (R_SERIAL1_REC_CTRL, rec_par_en, disable) \
509 | IO_STATE (R_SERIAL1_REC_CTRL, rec_bitnr, rec_8bit),$r0
514 | IO_STATE (R_SERIAL1_TR_CTRL, tr_enable, enable) \
515 | IO_STATE (R_SERIAL1_TR_CTRL, auto_cts, disabled) \
516 | IO_STATE (R_SERIAL1_TR_CTRL, stop_bits, one_bit) \
517 | IO_STATE (R_SERIAL1_TR_CTRL, tr_stick_par, normal) \
518 | IO_STATE (R_SERIAL1_TR_CTRL, tr_par, even) \
519 | IO_STATE (R_SERIAL1_TR_CTRL, tr_par_en, disable) \
520 | IO_STATE (R_SERIAL1_TR_CTRL, tr_bitnr, tr_8bit),$r0
526 moveq IO_STATE (R_SERIAL2_XOFF, tx_stop, enable) \
527 | IO_STATE (R_SERIAL2_XOFF, auto_xoff, disable) \
532 move.b IO_STATE (R_SERIAL2_BAUD, tr_baud, c115k2Hz) \
533 | IO_STATE (R_SERIAL2_BAUD, rec_baud, c115k2Hz),$r0
537 move.b IO_STATE (R_SERIAL2_REC_CTRL, dma_err, stop) \
538 | IO_STATE (R_SERIAL2_REC_CTRL, rec_enable, enable) \
539 | IO_STATE (R_SERIAL2_REC_CTRL, rts_, active) \
540 | IO_STATE (R_SERIAL2_REC_CTRL, sampling, middle) \
541 | IO_STATE (R_SERIAL2_REC_CTRL, rec_stick_par, normal) \
542 | IO_STATE (R_SERIAL2_REC_CTRL, rec_par, even) \
543 | IO_STATE (R_SERIAL2_REC_CTRL, rec_par_en, disable) \
544 | IO_STATE (R_SERIAL2_REC_CTRL, rec_bitnr, rec_8bit),$r0
549 | IO_STATE (R_SERIAL2_TR_CTRL, tr_enable, enable) \
550 | IO_STATE (R_SERIAL2_TR_CTRL, auto_cts, disabled) \
551 | IO_STATE (R_SERIAL2_TR_CTRL, stop_bits, one_bit) \
552 | IO_STATE (R_SERIAL2_TR_CTRL, tr_stick_par, normal) \
553 | IO_STATE (R_SERIAL2_TR_CTRL, tr_par, even) \
554 | IO_STATE (R_SERIAL2_TR_CTRL, tr_par_en, disable) \
555 | IO_STATE (R_SERIAL2_TR_CTRL, tr_bitnr, tr_8bit),$r0
562 moveq IO_STATE (R_SERIAL3_XOFF, tx_stop, enable) \
563 | IO_STATE (R_SERIAL3_XOFF, auto_xoff, disable) \
568 move.b IO_STATE (R_SERIAL3_BAUD, tr_baud, c115k2Hz) \
569 | IO_STATE (R_SERIAL3_BAUD, rec_baud, c115k2Hz),$r0
573 move.b IO_STATE (R_SERIAL3_REC_CTRL, dma_err, stop) \
574 | IO_STATE (R_SERIAL3_REC_CTRL, rec_enable, enable) \
575 | IO_STATE (R_SERIAL3_REC_CTRL, rts_, active) \
576 | IO_STATE (R_SERIAL3_REC_CTRL, sampling, middle) \
577 | IO_STATE (R_SERIAL3_REC_CTRL, rec_stick_par, normal) \
578 | IO_STATE (R_SERIAL3_REC_CTRL, rec_par, even) \
579 | IO_STATE (R_SERIAL3_REC_CTRL, rec_par_en, disable) \
580 | IO_STATE (R_SERIAL3_REC_CTRL, rec_bitnr, rec_8bit),$r0
585 | IO_STATE (R_SERIAL3_TR_CTRL, tr_enable, enable) \
586 | IO_STATE (R_SERIAL3_TR_CTRL, auto_cts, disabled) \
587 | IO_STATE (R_SERIAL3_TR_CTRL, stop_bits, one_bit) \
588 | IO_STATE (R_SERIAL3_TR_CTRL, tr_stick_par, normal) \
589 | IO_STATE (R_SERIAL3_TR_CTRL, tr_par, even) \
590 | IO_STATE (R_SERIAL3_TR_CTRL, tr_par_en, disable) \
591 | IO_STATE (R_SERIAL3_TR_CTRL, tr_bitnr, tr_8bit),$r0