Lines Matching refs:M32R_ICU_OFFSET
170 #define M32R_ICU_OFFSET (0x000FF000+M32R_SFR_OFFSET) macro
171 #define M32R_ICU_ISTS_PORTL (0x004+M32R_ICU_OFFSET)
172 #define M32R_ICU_IREQ0_PORTL (0x008+M32R_ICU_OFFSET)
173 #define M32R_ICU_IREQ1_PORTL (0x00C+M32R_ICU_OFFSET)
174 #define M32R_ICU_SBICR_PORTL (0x018+M32R_ICU_OFFSET)
175 #define M32R_ICU_IMASK_PORTL (0x01C+M32R_ICU_OFFSET)
176 #define M32R_ICU_CR1_PORTL (0x200+M32R_ICU_OFFSET) /* INT0 */
177 #define M32R_ICU_CR2_PORTL (0x204+M32R_ICU_OFFSET) /* INT1 */
178 #define M32R_ICU_CR3_PORTL (0x208+M32R_ICU_OFFSET) /* INT2 */
179 #define M32R_ICU_CR4_PORTL (0x20C+M32R_ICU_OFFSET) /* INT3 */
180 #define M32R_ICU_CR5_PORTL (0x210+M32R_ICU_OFFSET) /* INT4 */
181 #define M32R_ICU_CR6_PORTL (0x214+M32R_ICU_OFFSET) /* INT5 */
182 #define M32R_ICU_CR7_PORTL (0x218+M32R_ICU_OFFSET) /* INT6 */
183 #define M32R_ICU_CR8_PORTL (0x219+M32R_ICU_OFFSET) /* INT7 */
184 #define M32R_ICU_CR16_PORTL (0x23C+M32R_ICU_OFFSET) /* MFT0 */
185 #define M32R_ICU_CR17_PORTL (0x240+M32R_ICU_OFFSET) /* MFT1 */
186 #define M32R_ICU_CR18_PORTL (0x244+M32R_ICU_OFFSET) /* MFT2 */
187 #define M32R_ICU_CR19_PORTL (0x248+M32R_ICU_OFFSET) /* MFT3 */
188 #define M32R_ICU_CR20_PORTL (0x24C+M32R_ICU_OFFSET) /* MFT4 */
189 #define M32R_ICU_CR21_PORTL (0x250+M32R_ICU_OFFSET) /* MFT5 */
190 #define M32R_ICU_CR32_PORTL (0x27C+M32R_ICU_OFFSET) /* DMA0 */
191 #define M32R_ICU_CR33_PORTL (0x280+M32R_ICU_OFFSET) /* DMA1 */
192 #define M32R_ICU_CR48_PORTL (0x2BC+M32R_ICU_OFFSET) /* SIO0 */
193 #define M32R_ICU_CR49_PORTL (0x2C0+M32R_ICU_OFFSET) /* SIO0 */
194 #define M32R_ICU_CR50_PORTL (0x2C4+M32R_ICU_OFFSET) /* SIO1 */
195 #define M32R_ICU_CR51_PORTL (0x2C8+M32R_ICU_OFFSET) /* SIO1 */
196 #define M32R_ICU_CR52_PORTL (0x2CC+M32R_ICU_OFFSET) /* SIO2 */
197 #define M32R_ICU_CR53_PORTL (0x2D0+M32R_ICU_OFFSET) /* SIO2 */
198 #define M32R_ICU_CR54_PORTL (0x2D4+M32R_ICU_OFFSET) /* SIO3 */
199 #define M32R_ICU_CR55_PORTL (0x2D8+M32R_ICU_OFFSET) /* SIO3 */
200 #define M32R_ICU_CR56_PORTL (0x2DC+M32R_ICU_OFFSET) /* SIO4 */
201 #define M32R_ICU_CR57_PORTL (0x2E0+M32R_ICU_OFFSET) /* SIO4 */
204 #define M32R_ICU_IPICR0_PORTL (0x2dc+M32R_ICU_OFFSET) /* IPI0 */
205 #define M32R_ICU_IPICR1_PORTL (0x2e0+M32R_ICU_OFFSET) /* IPI1 */
206 #define M32R_ICU_IPICR2_PORTL (0x2e4+M32R_ICU_OFFSET) /* IPI2 */
207 #define M32R_ICU_IPICR3_PORTL (0x2e8+M32R_ICU_OFFSET) /* IPI3 */
208 #define M32R_ICU_IPICR4_PORTL (0x2ec+M32R_ICU_OFFSET) /* IPI4 */
209 #define M32R_ICU_IPICR5_PORTL (0x2f0+M32R_ICU_OFFSET) /* IPI5 */
210 #define M32R_ICU_IPICR6_PORTL (0x2f4+M32R_ICU_OFFSET) /* IPI6 */
211 #define M32R_ICU_IPICR7_PORTL (0x2f8+M32R_ICU_OFFSET) /* IPI7 */