Lines Matching refs:readl
160 didr1 = readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x18)); in tnetd7300_dsp_clock()
161 didr2 = readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x1c)); in tnetd7300_dsp_clock()
177 u32 ctrl = readl(&clock->ctrl); in tnetd7300_get_clock()
178 u32 pll = readl(&clock->pll); in tnetd7300_get_clock()
244 while (readl(&clock->pll) & PLL_STATUS) in tnetd7300_set_clock()
286 while (readl(&clock->status) & 0x1) in tnetd7200_set_clock()
291 writel(readl(&clock->cmden) | 1, &clock->cmden); in tnetd7200_set_clock()
292 writel(readl(&clock->cmd) | 1, &clock->cmd); in tnetd7200_set_clock()
294 while (readl(&clock->status) & 0x1) in tnetd7200_set_clock()
299 writel(readl(&clock->cmden) | 1, &clock->cmden); in tnetd7200_set_clock()
300 writel(readl(&clock->cmd) | 1, &clock->cmd); in tnetd7200_set_clock()
302 while (readl(&clock->status) & 0x1) in tnetd7200_set_clock()
305 writel(readl(&clock->ctrl) | 1, &clock->ctrl); in tnetd7200_set_clock()