Lines Matching refs:_ULCAST_
233 #define CM_GCR_CONFIG_NUMIOCU_MSK (_ULCAST_(0xf) << 8)
235 #define CM_GCR_CONFIG_PCORES_MSK (_ULCAST_(0xff) << 0)
239 #define CM_GCR_BASE_GCRBASE_MSK (_ULCAST_(0x1ffff) << 15)
241 #define CM_GCR_BASE_CMDEFTGT_MSK (_ULCAST_(0x3) << 0)
249 #define CM_GCR_ACCESS_ACCESSEN_MSK (_ULCAST_(0xff) << 0)
253 #define CM_GCR_REV_MAJOR_MSK (_ULCAST_(0xff) << 8)
255 #define CM_GCR_REV_MINOR_MSK (_ULCAST_(0xff) << 0)
267 #define CM_GCR_ERROR_CAUSE_ERRTYPE_MSK (_ULCAST_(0x1f) << 27)
271 #define CM_GCR_ERROR_CAUSE_ERRINGO_MSK (_ULCAST_(0x7ffffff) << 0)
275 #define CM_GCR_ERROR_MULT_ERR2ND_MSK (_ULCAST_(0x1f) << 0)
279 #define CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE_MSK (_ULCAST_(0xfffff) << 12)
281 #define CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN_MSK (_ULCAST_(0x1) << 0)
285 #define CM_GCR_GIC_BASE_GICBASE_MSK (_ULCAST_(0x7fff) << 17)
287 #define CM_GCR_GIC_BASE_GICEN_MSK (_ULCAST_(0x1) << 0)
291 #define CM_GCR_CPC_BASE_CPCBASE_MSK (_ULCAST_(0x7fff) << 17)
293 #define CM_GCR_CPC_BASE_CPCEN_MSK (_ULCAST_(0x1) << 0)
297 #define CM_GCR_GIC_STATUS_GICEX_MSK (_ULCAST_(0x1) << 0)
301 #define CM_GCR_REGn_BASE_BASEADDR_MSK (_ULCAST_(0xffff) << 16)
305 #define CM_GCR_REGn_MASK_ADDRMASK_MSK (_ULCAST_(0xffff) << 16)
307 #define CM_GCR_REGn_MASK_CCAOVR_MSK (_ULCAST_(0x3) << 5)
309 #define CM_GCR_REGn_MASK_CCAOVREN_MSK (_ULCAST_(0x1) << 4)
311 #define CM_GCR_REGn_MASK_DROPL2_MSK (_ULCAST_(0x1) << 2)
313 #define CM_GCR_REGn_MASK_CMTGT_MSK (_ULCAST_(0x3) << 0)
314 #define CM_GCR_REGn_MASK_CMTGT_DISABLED (_ULCAST_(0x0) << 0)
315 #define CM_GCR_REGn_MASK_CMTGT_MEM (_ULCAST_(0x1) << 0)
316 #define CM_GCR_REGn_MASK_CMTGT_IOCU0 (_ULCAST_(0x2) << 0)
317 #define CM_GCR_REGn_MASK_CMTGT_IOCU1 (_ULCAST_(0x3) << 0)
321 #define CM_GCR_GIC_STATUS_EX_MSK (_ULCAST_(0x1) << 0)
325 #define CM_GCR_CPC_STATUS_EX_MSK (_ULCAST_(0x1) << 0)
329 #define CM_GCR_L2_CONFIG_BYPASS_MSK (_ULCAST_(0x1) << 20)
331 #define CM_GCR_L2_CONFIG_SET_SIZE_MSK (_ULCAST_(0xf) << 12)
333 #define CM_GCR_L2_CONFIG_LINE_SIZE_MSK (_ULCAST_(0xf) << 8)
335 #define CM_GCR_L2_CONFIG_ASSOC_MSK (_ULCAST_(0xff) << 0)
339 #define CM_GCR_SYS_CONFIG2_MAXVPW_MSK (_ULCAST_(0xf) << 0)
343 #define CM_GCR_L2_PFT_CONTROL_PAGEMASK_MSK (_ULCAST_(0xfffff) << 12)
345 #define CM_GCR_L2_PFT_CONTROL_PFTEN_MSK (_ULCAST_(0x1) << 8)
347 #define CM_GCR_L2_PFT_CONTROL_NPFT_MSK (_ULCAST_(0xff) << 0)
351 #define CM_GCR_L2_PFT_CONTROL_B_CEN_MSK (_ULCAST_(0x1) << 8)
353 #define CM_GCR_L2_PFT_CONTROL_B_PORTID_MSK (_ULCAST_(0xff) << 0)
357 #define CM_GCR_Cx_COHERENCE_COHDOMAINEN_MSK (_ULCAST_(0xff) << 0)
361 #define CM_GCR_Cx_CONFIG_IOCUTYPE_MSK (_ULCAST_(0x3) << 10)
363 #define CM_GCR_Cx_CONFIG_PVPE_MSK (_ULCAST_(0x3ff) << 0)
367 #define CM_GCR_Cx_OTHER_CORENUM_MSK (_ULCAST_(0xffff) << 16)
369 #define CM3_GCR_Cx_OTHER_CORE_MSK (_ULCAST_(0x3f) << 8)
371 #define CM3_GCR_Cx_OTHER_VP_MSK (_ULCAST_(0x7) << 0)
375 #define CM_GCR_Cx_RESET_BASE_BEVEXCBASE_MSK (_ULCAST_(0xfffff) << 12)
379 #define CM_GCR_Cx_RESET_EXT_BASE_EVARESET_MSK (_ULCAST_(0x1) << 31)
381 #define CM_GCR_Cx_RESET_EXT_BASE_UEB_MSK (_ULCAST_(0x1) << 30)
383 #define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCMASK_MSK (_ULCAST_(0xff) << 20)
385 #define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCPA_MSK (_ULCAST_(0x7f) << 1)
387 #define CM_GCR_Cx_RESET_EXT_BASE_PRESENT_MSK (_ULCAST_(0x1) << 0)