39 		return CVMX_ADD_IO_SEG(0x0001180000001818ull) + (offset) * 256;  in CVMX_SMIX_CLK()
46 		return CVMX_ADD_IO_SEG(0x0001180000001818ull) + (offset) * 256;  in CVMX_SMIX_CLK()
48 		return CVMX_ADD_IO_SEG(0x0001180000003818ull) + (offset) * 128;  in CVMX_SMIX_CLK()
50 	return CVMX_ADD_IO_SEG(0x0001180000001818ull) + (offset) * 256;  in CVMX_SMIX_CLK()
61 		return CVMX_ADD_IO_SEG(0x0001180000001800ull) + (offset) * 256;  in CVMX_SMIX_CMD()
68 		return CVMX_ADD_IO_SEG(0x0001180000001800ull) + (offset) * 256;  in CVMX_SMIX_CMD()
70 		return CVMX_ADD_IO_SEG(0x0001180000003800ull) + (offset) * 128;  in CVMX_SMIX_CMD()
72 	return CVMX_ADD_IO_SEG(0x0001180000001800ull) + (offset) * 256;  in CVMX_SMIX_CMD()
83 		return CVMX_ADD_IO_SEG(0x0001180000001820ull) + (offset) * 256;  in CVMX_SMIX_EN()
90 		return CVMX_ADD_IO_SEG(0x0001180000001820ull) + (offset) * 256;  in CVMX_SMIX_EN()
92 		return CVMX_ADD_IO_SEG(0x0001180000003820ull) + (offset) * 128;  in CVMX_SMIX_EN()
94 	return CVMX_ADD_IO_SEG(0x0001180000001820ull) + (offset) * 256;  in CVMX_SMIX_EN()
105 		return CVMX_ADD_IO_SEG(0x0001180000001810ull) + (offset) * 256;  in CVMX_SMIX_RD_DAT()
112 		return CVMX_ADD_IO_SEG(0x0001180000001810ull) + (offset) * 256;  in CVMX_SMIX_RD_DAT()
114 		return CVMX_ADD_IO_SEG(0x0001180000003810ull) + (offset) * 128;  in CVMX_SMIX_RD_DAT()
116 	return CVMX_ADD_IO_SEG(0x0001180000001810ull) + (offset) * 256;  in CVMX_SMIX_RD_DAT()
127 		return CVMX_ADD_IO_SEG(0x0001180000001808ull) + (offset) * 256;  in CVMX_SMIX_WR_DAT()
134 		return CVMX_ADD_IO_SEG(0x0001180000001808ull) + (offset) * 256;  in CVMX_SMIX_WR_DAT()
136 		return CVMX_ADD_IO_SEG(0x0001180000003808ull) + (offset) * 128;  in CVMX_SMIX_WR_DAT()
138 	return CVMX_ADD_IO_SEG(0x0001180000001808ull) + (offset) * 256;  in CVMX_SMIX_WR_DAT()