Lines Matching refs:x2
38 0x2 0x0 0x0 0xf0000000 0x04000000
147 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
148 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */
149 0x2 0x0b 0x2 0x0 0x1 0x0 /* CLK12*/
152 0x0 0x2 0x1 0x0 0x1 0x0 /* ENET1_TXD2_SER1_TXD2 */
153 0x0 0x3 0x1 0x0 0x2 0x0 /* ENET1_TXD3_SER1_TXD3 */
154 0x0 0x6 0x2 0x0 0x3 0x0 /* ENET1_RXD0_SER1_RXD0 */
155 0x0 0x7 0x2 0x0 0x1 0x0 /* ENET1_RXD1_SER1_RXD1 */
156 0x0 0x8 0x2 0x0 0x2 0x0 /* ENET1_RXD2_SER1_RXD2 */
157 0x0 0x9 0x2 0x0 0x2 0x0 /* ENET1_RXD3_SER1_RXD3 */
158 0x0 0x4 0x1 0x0 0x2 0x0 /* ENET1_TX_EN_SER1_RTS_B */
159 0x0 0xc 0x2 0x0 0x3 0x0 /* ENET1_RX_DV_SER1_CTS_B */
160 0x2 0x8 0x2 0x0 0x1 0x0 /* ENET1_GRXCLK */
161 0x2 0x14 0x1 0x0 0x2 0x0>; /* ENET1_GTXCLK */
167 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
168 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */
169 0x2 0x10 0x2 0x0 0x3 0x0 /* CLK17 */
170 0x0 0xe 0x1 0x0 0x2 0x0 /* ENET2_TXD0_SER2_TXD0 */
171 0x0 0xf 0x1 0x0 0x2 0x0 /* ENET2_TXD1_SER2_TXD1 */
174 0x0 0x14 0x2 0x0 0x2 0x0 /* ENET2_RXD0_SER2_RXD0 */
175 0x0 0x15 0x2 0x0 0x1 0x0 /* ENET2_RXD1_SER2_RXD1 */
176 0x0 0x16 0x2 0x0 0x1 0x0 /* ENET2_RXD2_SER2_RXD2 */
177 0x0 0x17 0x2 0x0 0x1 0x0 /* ENET2_RXD3_SER2_RXD3 */
178 0x0 0x12 0x1 0x0 0x2 0x0 /* ENET2_TX_EN_SER2_RTS_B */
179 0x0 0x1a 0x2 0x0 0x3 0x0 /* ENET2_RX_DV_SER2_CTS_B */
180 0x2 0x3 0x2 0x0 0x1 0x0 /* ENET2_GRXCLK */
181 0x2 0x2 0x1 0x0 0x2 0x0>; /* ENET2_GTXCLK */
187 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
188 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */
189 0x2 0x0b 0x2 0x0 0x1 0x0 /* CLK12*/
190 0x0 0x1d 0x1 0x0 0x2 0x0 /* ENET3_TXD0_SER3_TXD0 */
192 0x0 0x1f 0x1 0x0 0x2 0x0 /* ENET3_TXD2_SER3_TXD2 */
194 0x1 0x3 0x2 0x0 0x3 0x0 /* ENET3_RXD0_SER3_RXD0 */
195 0x1 0x4 0x2 0x0 0x1 0x0 /* ENET3_RXD1_SER3_RXD1 */
196 0x1 0x5 0x2 0x0 0x2 0x0 /* ENET3_RXD2_SER3_RXD2 */
197 0x1 0x6 0x2 0x0 0x3 0x0 /* ENET3_RXD3_SER3_RXD3 */
199 0x1 0x9 0x2 0x0 0x3 0x0 /* ENET3_RX_DV_SER3_CTS_B */
200 0x2 0x9 0x2 0x0 0x2 0x0 /* ENET3_GRXCLK */
201 0x2 0x19 0x1 0x0 0x2 0x0>; /* ENET3_GTXCLK */
207 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
208 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */
209 0x2 0x10 0x2 0x0 0x3 0x0 /* CLK17 */
210 0x1 0xc 0x1 0x0 0x2 0x0 /* ENET4_TXD0_SER4_TXD0 */
211 0x1 0xd 0x1 0x0 0x2 0x0 /* ENET4_TXD1_SER4_TXD1 */
213 0x1 0xf 0x1 0x0 0x2 0x0 /* ENET4_TXD3_SER4_TXD3 */
214 0x1 0x12 0x2 0x0 0x2 0x0 /* ENET4_RXD0_SER4_RXD0 */
215 0x1 0x13 0x2 0x0 0x1 0x0 /* ENET4_RXD1_SER4_RXD1 */
216 0x1 0x14 0x2 0x0 0x1 0x0 /* ENET4_RXD2_SER4_RXD2 */
217 0x1 0x15 0x2 0x0 0x2 0x0 /* ENET4_RXD3_SER4_RXD3 */
218 0x1 0x10 0x1 0x0 0x2 0x0 /* ENET4_TX_EN_SER4_RTS_B */
219 0x1 0x18 0x2 0x0 0x3 0x0 /* ENET4_RX_DV_SER4_CTS_B */
220 0x2 0x11 0x2 0x0 0x2 0x0 /* ENET4_GRXCLK */
221 0x2 0x18 0x1 0x0 0x2 0x0>; /* ENET4_GTXCLK */
288 reg = <0x2>;