Lines Matching refs:mtdcri
749 mtdcri(SDR0, PESDR0_440SPE_RCSSET, 0x01010000); in ppc440spe_pciex_check_reset()
750 mtdcri(SDR0, PESDR1_440SPE_RCSSET, 0x01010000); in ppc440spe_pciex_check_reset()
751 mtdcri(SDR0, PESDR2_440SPE_RCSSET, 0x01010000); in ppc440spe_pciex_check_reset()
863 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val); in ppc440spe_pciex_init_port_hw()
864 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x20222222); in ppc440spe_pciex_init_port_hw()
866 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x11000000); in ppc440spe_pciex_init_port_hw()
867 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL0SET1, 0x35000000); in ppc440spe_pciex_init_port_hw()
868 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL1SET1, 0x35000000); in ppc440spe_pciex_init_port_hw()
869 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL2SET1, 0x35000000); in ppc440spe_pciex_init_port_hw()
870 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL3SET1, 0x35000000); in ppc440spe_pciex_init_port_hw()
872 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL4SET1, in ppc440spe_pciex_init_port_hw()
874 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL5SET1, in ppc440spe_pciex_init_port_hw()
876 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL6SET1, in ppc440spe_pciex_init_port_hw()
878 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL7SET1, in ppc440spe_pciex_init_port_hw()
971 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val); in ppc460ex_pciex_init_port_hw()
972 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, utlset1); in ppc460ex_pciex_init_port_hw()
973 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01210000); in ppc460ex_pciex_init_port_hw()
977 mtdcri(SDR0, PESDR0_460EX_L0CDRCTL, 0x00003230); in ppc460ex_pciex_init_port_hw()
978 mtdcri(SDR0, PESDR0_460EX_L0DRV, 0x00000130); in ppc460ex_pciex_init_port_hw()
979 mtdcri(SDR0, PESDR0_460EX_L0CLK, 0x00000006); in ppc460ex_pciex_init_port_hw()
981 mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST,0x10000000); in ppc460ex_pciex_init_port_hw()
985 mtdcri(SDR0, PESDR1_460EX_L0CDRCTL, 0x00003230); in ppc460ex_pciex_init_port_hw()
986 mtdcri(SDR0, PESDR1_460EX_L1CDRCTL, 0x00003230); in ppc460ex_pciex_init_port_hw()
987 mtdcri(SDR0, PESDR1_460EX_L2CDRCTL, 0x00003230); in ppc460ex_pciex_init_port_hw()
988 mtdcri(SDR0, PESDR1_460EX_L3CDRCTL, 0x00003230); in ppc460ex_pciex_init_port_hw()
989 mtdcri(SDR0, PESDR1_460EX_L0DRV, 0x00000130); in ppc460ex_pciex_init_port_hw()
990 mtdcri(SDR0, PESDR1_460EX_L1DRV, 0x00000130); in ppc460ex_pciex_init_port_hw()
991 mtdcri(SDR0, PESDR1_460EX_L2DRV, 0x00000130); in ppc460ex_pciex_init_port_hw()
992 mtdcri(SDR0, PESDR1_460EX_L3DRV, 0x00000130); in ppc460ex_pciex_init_port_hw()
993 mtdcri(SDR0, PESDR1_460EX_L0CLK, 0x00000006); in ppc460ex_pciex_init_port_hw()
994 mtdcri(SDR0, PESDR1_460EX_L1CLK, 0x00000006); in ppc460ex_pciex_init_port_hw()
995 mtdcri(SDR0, PESDR1_460EX_L2CLK, 0x00000006); in ppc460ex_pciex_init_port_hw()
996 mtdcri(SDR0, PESDR1_460EX_L3CLK, 0x00000006); in ppc460ex_pciex_init_port_hw()
998 mtdcri(SDR0, PESDR1_460EX_PHY_CTL_RST,0x10000000); in ppc460ex_pciex_init_port_hw()
1002 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, in ppc460ex_pciex_init_port_hw()
1019 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, in ppc460ex_pciex_init_port_hw()
1076 mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x0); in apm821xx_pciex_init_port_hw()
1086 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val); in apm821xx_pciex_init_port_hw()
1087 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x00000000); in apm821xx_pciex_init_port_hw()
1088 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01010000); in apm821xx_pciex_init_port_hw()
1090 mtdcri(SDR0, PESDR0_460EX_L0CDRCTL, 0x00003230); in apm821xx_pciex_init_port_hw()
1091 mtdcri(SDR0, PESDR0_460EX_L0DRV, 0x00000130); in apm821xx_pciex_init_port_hw()
1092 mtdcri(SDR0, PESDR0_460EX_L0CLK, 0x00000006); in apm821xx_pciex_init_port_hw()
1094 mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x10000000); in apm821xx_pciex_init_port_hw()
1096 mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x30000000); in apm821xx_pciex_init_port_hw()
1098 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, in apm821xx_pciex_init_port_hw()
1108 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, in apm821xx_pciex_init_port_hw()
1129 mtdcri(SDR0, PESDR0_460SX_HSSL0DAMP, 0xB9843211); in ppc460sx_pciex_core_init()
1130 mtdcri(SDR0, PESDR0_460SX_HSSL1DAMP, 0xB9843211); in ppc460sx_pciex_core_init()
1131 mtdcri(SDR0, PESDR0_460SX_HSSL2DAMP, 0xB9843211); in ppc460sx_pciex_core_init()
1132 mtdcri(SDR0, PESDR0_460SX_HSSL3DAMP, 0xB9843211); in ppc460sx_pciex_core_init()
1133 mtdcri(SDR0, PESDR0_460SX_HSSL4DAMP, 0xB9843211); in ppc460sx_pciex_core_init()
1134 mtdcri(SDR0, PESDR0_460SX_HSSL5DAMP, 0xB9843211); in ppc460sx_pciex_core_init()
1135 mtdcri(SDR0, PESDR0_460SX_HSSL6DAMP, 0xB9843211); in ppc460sx_pciex_core_init()
1136 mtdcri(SDR0, PESDR0_460SX_HSSL7DAMP, 0xB9843211); in ppc460sx_pciex_core_init()
1138 mtdcri(SDR0, PESDR1_460SX_HSSL0DAMP, 0xB9843211); in ppc460sx_pciex_core_init()
1139 mtdcri(SDR0, PESDR1_460SX_HSSL1DAMP, 0xB9843211); in ppc460sx_pciex_core_init()
1140 mtdcri(SDR0, PESDR1_460SX_HSSL2DAMP, 0xB9843211); in ppc460sx_pciex_core_init()
1141 mtdcri(SDR0, PESDR1_460SX_HSSL3DAMP, 0xB9843211); in ppc460sx_pciex_core_init()
1143 mtdcri(SDR0, PESDR2_460SX_HSSL0DAMP, 0xB9843211); in ppc460sx_pciex_core_init()
1144 mtdcri(SDR0, PESDR2_460SX_HSSL1DAMP, 0xB9843211); in ppc460sx_pciex_core_init()
1145 mtdcri(SDR0, PESDR2_460SX_HSSL2DAMP, 0xB9843211); in ppc460sx_pciex_core_init()
1146 mtdcri(SDR0, PESDR2_460SX_HSSL3DAMP, 0xB9843211); in ppc460sx_pciex_core_init()
1149 mtdcri(SDR0, PESDR0_460SX_HSSL0COEFA, 0xDCB98987); in ppc460sx_pciex_core_init()
1150 mtdcri(SDR0, PESDR0_460SX_HSSL1COEFA, 0xDCB98987); in ppc460sx_pciex_core_init()
1151 mtdcri(SDR0, PESDR0_460SX_HSSL2COEFA, 0xDCB98987); in ppc460sx_pciex_core_init()
1152 mtdcri(SDR0, PESDR0_460SX_HSSL3COEFA, 0xDCB98987); in ppc460sx_pciex_core_init()
1153 mtdcri(SDR0, PESDR0_460SX_HSSL4COEFA, 0xDCB98987); in ppc460sx_pciex_core_init()
1154 mtdcri(SDR0, PESDR0_460SX_HSSL5COEFA, 0xDCB98987); in ppc460sx_pciex_core_init()
1155 mtdcri(SDR0, PESDR0_460SX_HSSL6COEFA, 0xDCB98987); in ppc460sx_pciex_core_init()
1156 mtdcri(SDR0, PESDR0_460SX_HSSL7COEFA, 0xDCB98987); in ppc460sx_pciex_core_init()
1158 mtdcri(SDR0, PESDR1_460SX_HSSL0COEFA, 0xDCB98987); in ppc460sx_pciex_core_init()
1159 mtdcri(SDR0, PESDR1_460SX_HSSL1COEFA, 0xDCB98987); in ppc460sx_pciex_core_init()
1160 mtdcri(SDR0, PESDR1_460SX_HSSL2COEFA, 0xDCB98987); in ppc460sx_pciex_core_init()
1161 mtdcri(SDR0, PESDR1_460SX_HSSL3COEFA, 0xDCB98987); in ppc460sx_pciex_core_init()
1163 mtdcri(SDR0, PESDR2_460SX_HSSL0COEFA, 0xDCB98987); in ppc460sx_pciex_core_init()
1164 mtdcri(SDR0, PESDR2_460SX_HSSL1COEFA, 0xDCB98987); in ppc460sx_pciex_core_init()
1165 mtdcri(SDR0, PESDR2_460SX_HSSL2COEFA, 0xDCB98987); in ppc460sx_pciex_core_init()
1166 mtdcri(SDR0, PESDR2_460SX_HSSL3COEFA, 0xDCB98987); in ppc460sx_pciex_core_init()
1169 mtdcri(SDR0, PESDR0_460SX_HSSL1CALDRV, 0x22222222); in ppc460sx_pciex_core_init()
1170 mtdcri(SDR0, PESDR1_460SX_HSSL1CALDRV, 0x22220000); in ppc460sx_pciex_core_init()
1171 mtdcri(SDR0, PESDR2_460SX_HSSL1CALDRV, 0x22220000); in ppc460sx_pciex_core_init()
1174 mtdcri(SDR0, PESDR0_460SX_HSSSLEW, 0xFFFFFFFF); in ppc460sx_pciex_core_init()
1175 mtdcri(SDR0, PESDR1_460SX_HSSSLEW, 0xFFFF0000); in ppc460sx_pciex_core_init()
1176 mtdcri(SDR0, PESDR2_460SX_HSSSLEW, 0xFFFF0000); in ppc460sx_pciex_core_init()
1179 mtdcri(SDR0, PESDR0_460SX_HSSCTLSET, 0x00001130); in ppc460sx_pciex_core_init()
1180 mtdcri(SDR0, PESDR2_460SX_HSSCTLSET, 0x00001130); in ppc460sx_pciex_core_init()
1188 mtdcri(SDR0, PESDR0_460SX_RCSSET, in ppc460sx_pciex_core_init()
1190 mtdcri(SDR0, PESDR1_460SX_RCSSET, in ppc460sx_pciex_core_init()
1192 mtdcri(SDR0, PESDR2_460SX_RCSSET, in ppc460sx_pciex_core_init()
1287 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01010000); in ppc405ex_pcie_phy_reset()
1292 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01111000); in ppc405ex_pcie_phy_reset()
1294 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01101000); in ppc405ex_pcie_phy_reset()
1302 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x00101000); in ppc405ex_pcie_phy_reset()
1314 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, in ppc405ex_pciex_init_port_hw()
1317 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x00000000); in ppc405ex_pciex_init_port_hw()
1318 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01010000); in ppc405ex_pciex_init_port_hw()
1319 mtdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSET1, 0x720F0000); in ppc405ex_pciex_init_port_hw()
1320 mtdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSET2, 0x70600003); in ppc405ex_pciex_init_port_hw()