Lines Matching refs:OP
1523 #define OP(x) ((((unsigned long)(x)) & 0x3f) << 26) macro
1524 #define OP_MASK OP (0x3f)
1529 #define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
1535 #define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
1539 #define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) &…
1555 #define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
1587 #define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7))
1591 #define UCTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
1598 #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
1602 #define DEO(op, xop) (OP (op) | ((xop) & 0xf))
1606 #define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
1610 #define M(op, rc) (OP (op) | ((rc) & 1))
1623 #define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
1633 #define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
1640 #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
1644 #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
1650 #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
1656 #define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
1662 #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1665 #define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1))
1735 #define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)…
1739 #define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
1743 #define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1783 …(OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsi…
1790 #define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc))…
1818 #define XUC(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
1950 { "tdi", OP(2), OP_MASK, PPC64, { TO, RA, SI } },
1980 { "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } },
1981 { "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } },
2508 { "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } },
2509 { "muli", OP(7), OP_MASK, PWRCOM, { RT, RA, SI } },
2511 { "subfic", OP(8), OP_MASK, PPCCOM, { RT, RA, SI } },
2512 { "sfi", OP(8), OP_MASK, PWRCOM, { RT, RA, SI } },
2514 { "dozi", OP(9), OP_MASK, M601, { RT, RA, SI } },
2523 { "cmpli", OP(10), OP_MASK, PPC, { BF, L, RA, UI } },
2524 { "cmpli", OP(10), OP_MASK, PWRCOM, { BF, RA, UI } },
2528 { "cmpi", OP(11), OP_MASK, PPC, { BF, L, RA, SI } },
2529 { "cmpi", OP(11), OP_MASK, PWRCOM, { BF, RA, SI } },
2531 { "addic", OP(12), OP_MASK, PPCCOM, { RT, RA, SI } },
2532 { "ai", OP(12), OP_MASK, PWRCOM, { RT, RA, SI } },
2533 { "subic", OP(12), OP_MASK, PPCCOM, { RT, RA, NSI } },
2535 { "addic.", OP(13), OP_MASK, PPCCOM, { RT, RA, SI } },
2536 { "ai.", OP(13), OP_MASK, PWRCOM, { RT, RA, SI } },
2537 { "subic.", OP(13), OP_MASK, PPCCOM, { RT, RA, NSI } },
2539 { "li", OP(14), DRA_MASK, PPCCOM, { RT, SI } },
2540 { "lil", OP(14), DRA_MASK, PWRCOM, { RT, SI } },
2541 { "addi", OP(14), OP_MASK, PPCCOM, { RT, RA0, SI } },
2542 { "cal", OP(14), OP_MASK, PWRCOM, { RT, D, RA0 } },
2543 { "subi", OP(14), OP_MASK, PPCCOM, { RT, RA0, NSI } },
2544 { "la", OP(14), OP_MASK, PPCCOM, { RT, D, RA0 } },
2546 { "lis", OP(15), DRA_MASK, PPCCOM, { RT, SISIGNOPT } },
2547 { "liu", OP(15), DRA_MASK, PWRCOM, { RT, SISIGNOPT } },
2548 { "addis", OP(15), OP_MASK, PPCCOM, { RT,RA0,SISIGNOPT } },
2549 { "cau", OP(15), OP_MASK, PWRCOM, { RT,RA0,SISIGNOPT } },
2550 { "subis", OP(15), OP_MASK, PPCCOM, { RT, RA0, NSI } },
3276 { "nop", OP(24), 0xffffffff, PPCCOM, { 0 } },
3277 { "ori", OP(24), OP_MASK, PPCCOM, { RA, RS, UI } },
3278 { "oril", OP(24), OP_MASK, PWRCOM, { RA, RS, UI } },
3280 { "oris", OP(25), OP_MASK, PPCCOM, { RA, RS, UI } },
3281 { "oriu", OP(25), OP_MASK, PWRCOM, { RA, RS, UI } },
3283 { "xori", OP(26), OP_MASK, PPCCOM, { RA, RS, UI } },
3284 { "xoril", OP(26), OP_MASK, PWRCOM, { RA, RS, UI } },
3286 { "xoris", OP(27), OP_MASK, PPCCOM, { RA, RS, UI } },
3287 { "xoriu", OP(27), OP_MASK, PWRCOM, { RA, RS, UI } },
3289 { "andi.", OP(28), OP_MASK, PPCCOM, { RA, RS, UI } },
3290 { "andil.", OP(28), OP_MASK, PWRCOM, { RA, RS, UI } },
3292 { "andis.", OP(29), OP_MASK, PPCCOM, { RA, RS, UI } },
3293 { "andiu.", OP(29), OP_MASK, PWRCOM, { RA, RS, UI } },
4541 { "lwz", OP(32), OP_MASK, PPCCOM, { RT, D, RA0 } },
4542 { "l", OP(32), OP_MASK, PWRCOM, { RT, D, RA0 } },
4544 { "lwzu", OP(33), OP_MASK, PPCCOM, { RT, D, RAL } },
4545 { "lu", OP(33), OP_MASK, PWRCOM, { RT, D, RA0 } },
4547 { "lbz", OP(34), OP_MASK, COM, { RT, D, RA0 } },
4549 { "lbzu", OP(35), OP_MASK, COM, { RT, D, RAL } },
4551 { "stw", OP(36), OP_MASK, PPCCOM, { RS, D, RA0 } },
4552 { "st", OP(36), OP_MASK, PWRCOM, { RS, D, RA0 } },
4554 { "stwu", OP(37), OP_MASK, PPCCOM, { RS, D, RAS } },
4555 { "stu", OP(37), OP_MASK, PWRCOM, { RS, D, RA0 } },
4557 { "stb", OP(38), OP_MASK, COM, { RS, D, RA0 } },
4559 { "stbu", OP(39), OP_MASK, COM, { RS, D, RAS } },
4561 { "lhz", OP(40), OP_MASK, COM, { RT, D, RA0 } },
4563 { "lhzu", OP(41), OP_MASK, COM, { RT, D, RAL } },
4565 { "lha", OP(42), OP_MASK, COM, { RT, D, RA0 } },
4567 { "lhau", OP(43), OP_MASK, COM, { RT, D, RAL } },
4569 { "sth", OP(44), OP_MASK, COM, { RS, D, RA0 } },
4571 { "sthu", OP(45), OP_MASK, COM, { RS, D, RAS } },
4573 { "lmw", OP(46), OP_MASK, PPCCOM, { RT, D, RAM } },
4574 { "lm", OP(46), OP_MASK, PWRCOM, { RT, D, RA0 } },
4576 { "stmw", OP(47), OP_MASK, PPCCOM, { RS, D, RA0 } },
4577 { "stm", OP(47), OP_MASK, PWRCOM, { RS, D, RA0 } },
4579 { "lfs", OP(48), OP_MASK, COM, { FRT, D, RA0 } },
4581 { "lfsu", OP(49), OP_MASK, COM, { FRT, D, RAS } },
4583 { "lfd", OP(50), OP_MASK, COM, { FRT, D, RA0 } },
4585 { "lfdu", OP(51), OP_MASK, COM, { FRT, D, RAS } },
4587 { "stfs", OP(52), OP_MASK, COM, { FRS, D, RA0 } },
4589 { "stfsu", OP(53), OP_MASK, COM, { FRS, D, RAS } },
4591 { "stfd", OP(54), OP_MASK, COM, { FRS, D, RA0 } },
4593 { "stfdu", OP(55), OP_MASK, COM, { FRS, D, RAS } },
4595 { "lq", OP(56), OP_MASK, POWER4, { RTQ, DQ, RAQ } },
4597 { "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA0 } },
4599 { "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA0 } },
4601 { "lfdp", OP(57), OP_MASK, POWER6, { FRT, D, RA0 } },
4724 { "stfq", OP(60), OP_MASK, POWER2, { FRS, D, RA } },
4726 { "stfqu", OP(61), OP_MASK, POWER2, { FRS, D, RA } },
4728 { "stfdp", OP(61), OP_MASK, POWER6, { FRT, D, RA0 } },