Lines Matching refs:RA
374 #define RA NSI + 1 macro
379 #define RA0 RA + 1
1936 { "tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, { RA, SI } },
1937 { "tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, { RA, SI } },
1938 { "tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, { RA, SI } },
1939 { "tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, { RA, SI } },
1940 { "tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, { RA, SI } },
1941 { "tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, { RA, SI } },
1942 { "tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, { RA, SI } },
1943 { "tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, { RA, SI } },
1944 { "tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, { RA, SI } },
1945 { "tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, { RA, SI } },
1946 { "tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, { RA, SI } },
1947 { "tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, { RA, SI } },
1948 { "tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, { RA, SI } },
1949 { "tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, { RA, SI } },
1950 { "tdi", OP(2), OP_MASK, PPC64, { TO, RA, SI } },
1952 { "twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, { RA, SI } },
1953 { "tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, { RA, SI } },
1954 { "twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, { RA, SI } },
1955 { "tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, { RA, SI } },
1956 { "tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, { RA, SI } },
1957 { "teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, { RA, SI } },
1958 { "twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, { RA, SI } },
1959 { "tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, { RA, SI } },
1960 { "twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, { RA, SI } },
1961 { "tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, { RA, SI } },
1962 { "twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, { RA, SI } },
1963 { "tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, { RA, SI } },
1964 { "twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, { RA, SI } },
1965 { "tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, { RA, SI } },
1966 { "twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, { RA, SI } },
1967 { "tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, { RA, SI } },
1968 { "twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, { RA, SI } },
1969 { "tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, { RA, SI } },
1970 { "twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, { RA, SI } },
1971 { "tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, { RA, SI } },
1972 { "twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, { RA, SI } },
1973 { "tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, { RA, SI } },
1974 { "twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, { RA, SI } },
1975 { "tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, { RA, SI } },
1976 { "twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, { RA, SI } },
1977 { "tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, { RA, SI } },
1978 { "twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, { RA, SI } },
1979 { "tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, { RA, SI } },
1980 { "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } },
1981 { "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } },
1983 { "macchw", XO(4,172,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1984 { "macchw.", XO(4,172,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1985 { "macchwo", XO(4,172,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1986 { "macchwo.", XO(4,172,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1987 { "macchws", XO(4,236,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1988 { "macchws.", XO(4,236,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1989 { "macchwso", XO(4,236,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1990 { "macchwso.", XO(4,236,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1991 { "macchwsu", XO(4,204,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1992 { "macchwsu.", XO(4,204,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1993 { "macchwsuo", XO(4,204,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1994 { "macchwsuo.", XO(4,204,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1995 { "macchwu", XO(4,140,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1996 { "macchwu.", XO(4,140,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1997 { "macchwuo", XO(4,140,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1998 { "macchwuo.", XO(4,140,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1999 { "machhw", XO(4,44,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2000 { "machhw.", XO(4,44,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2001 { "machhwo", XO(4,44,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2002 { "machhwo.", XO(4,44,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2003 { "machhws", XO(4,108,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2004 { "machhws.", XO(4,108,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2005 { "machhwso", XO(4,108,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2006 { "machhwso.", XO(4,108,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2007 { "machhwsu", XO(4,76,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2008 { "machhwsu.", XO(4,76,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2009 { "machhwsuo", XO(4,76,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2010 { "machhwsuo.", XO(4,76,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2011 { "machhwu", XO(4,12,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2012 { "machhwu.", XO(4,12,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2013 { "machhwuo", XO(4,12,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2014 { "machhwuo.", XO(4,12,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2015 { "maclhw", XO(4,428,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2016 { "maclhw.", XO(4,428,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2017 { "maclhwo", XO(4,428,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2018 { "maclhwo.", XO(4,428,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2019 { "maclhws", XO(4,492,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2020 { "maclhws.", XO(4,492,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2021 { "maclhwso", XO(4,492,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2022 { "maclhwso.", XO(4,492,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2023 { "maclhwsu", XO(4,460,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2024 { "maclhwsu.", XO(4,460,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2025 { "maclhwsuo", XO(4,460,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2026 { "maclhwsuo.", XO(4,460,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2027 { "maclhwu", XO(4,396,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2028 { "maclhwu.", XO(4,396,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2029 { "maclhwuo", XO(4,396,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2030 { "maclhwuo.", XO(4,396,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2031 { "mulchw", XRC(4,168,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2032 { "mulchw.", XRC(4,168,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2033 { "mulchwu", XRC(4,136,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2034 { "mulchwu.", XRC(4,136,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2035 { "mulhhw", XRC(4,40,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2036 { "mulhhw.", XRC(4,40,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2037 { "mulhhwu", XRC(4,8,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2038 { "mulhhwu.", XRC(4,8,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2039 { "mullhw", XRC(4,424,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2040 { "mullhw.", XRC(4,424,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2041 { "mullhwu", XRC(4,392,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2042 { "mullhwu.", XRC(4,392,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2043 { "nmacchw", XO(4,174,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2044 { "nmacchw.", XO(4,174,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2045 { "nmacchwo", XO(4,174,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2046 { "nmacchwo.", XO(4,174,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2047 { "nmacchws", XO(4,238,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2048 { "nmacchws.", XO(4,238,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2049 { "nmacchwso", XO(4,238,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2050 { "nmacchwso.", XO(4,238,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2051 { "nmachhw", XO(4,46,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2052 { "nmachhw.", XO(4,46,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2053 { "nmachhwo", XO(4,46,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2054 { "nmachhwo.", XO(4,46,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2055 { "nmachhws", XO(4,110,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2056 { "nmachhws.", XO(4,110,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2057 { "nmachhwso", XO(4,110,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2058 { "nmachhwso.", XO(4,110,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2059 { "nmaclhw", XO(4,430,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2060 { "nmaclhw.", XO(4,430,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2061 { "nmaclhwo", XO(4,430,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2062 { "nmaclhwo.", XO(4,430,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2063 { "nmaclhws", XO(4,494,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2064 { "nmaclhws.", XO(4,494,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2065 { "nmaclhwso", XO(4,494,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2066 { "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2074 { "efdabs", VX(4, 740), VX_MASK, PPCEFS, { RS, RA } },
2075 { "efdnabs", VX(4, 741), VX_MASK, PPCEFS, { RS, RA } },
2076 { "efdneg", VX(4, 742), VX_MASK, PPCEFS, { RS, RA } },
2077 { "efdadd", VX(4, 736), VX_MASK, PPCEFS, { RS, RA, RB } },
2078 { "efdsub", VX(4, 737), VX_MASK, PPCEFS, { RS, RA, RB } },
2079 { "efdmul", VX(4, 744), VX_MASK, PPCEFS, { RS, RA, RB } },
2080 { "efddiv", VX(4, 745), VX_MASK, PPCEFS, { RS, RA, RB } },
2081 { "efdcmpgt", VX(4, 748), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2082 { "efdcmplt", VX(4, 749), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2083 { "efdcmpeq", VX(4, 750), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2084 { "efdtstgt", VX(4, 764), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2085 { "efdtstlt", VX(4, 765), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2086 { "efdtsteq", VX(4, 766), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2260 { "evaddw", VX(4, 512), VX_MASK, PPCSPE, { RS, RA, RB } },
2262 { "evsubfw", VX(4, 516), VX_MASK, PPCSPE, { RS, RA, RB } },
2263 { "evsubw", VX(4, 516), VX_MASK, PPCSPE, { RS, RB, RA } },
2266 { "evabs", VX(4, 520), VX_MASK, PPCSPE, { RS, RA } },
2267 { "evneg", VX(4, 521), VX_MASK, PPCSPE, { RS, RA } },
2268 { "evextsb", VX(4, 522), VX_MASK, PPCSPE, { RS, RA } },
2269 { "evextsh", VX(4, 523), VX_MASK, PPCSPE, { RS, RA } },
2270 { "evrndw", VX(4, 524), VX_MASK, PPCSPE, { RS, RA } },
2271 { "evcntlzw", VX(4, 525), VX_MASK, PPCSPE, { RS, RA } },
2272 { "evcntlsw", VX(4, 526), VX_MASK, PPCSPE, { RS, RA } },
2274 { "brinc", VX(4, 527), VX_MASK, PPCSPE, { RS, RA, RB } },
2276 { "evand", VX(4, 529), VX_MASK, PPCSPE, { RS, RA, RB } },
2277 { "evandc", VX(4, 530), VX_MASK, PPCSPE, { RS, RA, RB } },
2278 { "evmr", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, BBA } },
2279 { "evor", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, RB } },
2280 { "evorc", VX(4, 539), VX_MASK, PPCSPE, { RS, RA, RB } },
2281 { "evxor", VX(4, 534), VX_MASK, PPCSPE, { RS, RA, RB } },
2282 { "eveqv", VX(4, 537), VX_MASK, PPCSPE, { RS, RA, RB } },
2283 { "evnand", VX(4, 542), VX_MASK, PPCSPE, { RS, RA, RB } },
2284 { "evnot", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, BBA } },
2285 { "evnor", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, RB } },
2287 { "evrlw", VX(4, 552), VX_MASK, PPCSPE, { RS, RA, RB } },
2288 { "evrlwi", VX(4, 554), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2289 { "evslw", VX(4, 548), VX_MASK, PPCSPE, { RS, RA, RB } },
2290 { "evslwi", VX(4, 550), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2291 { "evsrws", VX(4, 545), VX_MASK, PPCSPE, { RS, RA, RB } },
2292 { "evsrwu", VX(4, 544), VX_MASK, PPCSPE, { RS, RA, RB } },
2293 { "evsrwis", VX(4, 547), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2294 { "evsrwiu", VX(4, 546), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2297 { "evmergehi", VX(4, 556), VX_MASK, PPCSPE, { RS, RA, RB } },
2298 { "evmergelo", VX(4, 557), VX_MASK, PPCSPE, { RS, RA, RB } },
2299 { "evmergehilo",VX(4,558), VX_MASK, PPCSPE, { RS, RA, RB } },
2300 { "evmergelohi",VX(4,559), VX_MASK, PPCSPE, { RS, RA, RB } },
2302 { "evcmpgts", VX(4, 561), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2303 { "evcmpgtu", VX(4, 560), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2304 { "evcmplts", VX(4, 563), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2305 { "evcmpltu", VX(4, 562), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2306 { "evcmpeq", VX(4, 564), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2307 { "evsel", EVSEL(4,79),EVSEL_MASK, PPCSPE, { RS, RA, RB, CRFS } },
2309 { "evldd", VX(4, 769), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2310 { "evlddx", VX(4, 768), VX_MASK, PPCSPE, { RS, RA, RB } },
2311 { "evldw", VX(4, 771), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2312 { "evldwx", VX(4, 770), VX_MASK, PPCSPE, { RS, RA, RB } },
2313 { "evldh", VX(4, 773), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2314 { "evldhx", VX(4, 772), VX_MASK, PPCSPE, { RS, RA, RB } },
2315 { "evlwhe", VX(4, 785), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2316 { "evlwhex", VX(4, 784), VX_MASK, PPCSPE, { RS, RA, RB } },
2317 { "evlwhou", VX(4, 789), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2318 { "evlwhoux", VX(4, 788), VX_MASK, PPCSPE, { RS, RA, RB } },
2319 { "evlwhos", VX(4, 791), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2320 { "evlwhosx", VX(4, 790), VX_MASK, PPCSPE, { RS, RA, RB } },
2321 { "evlwwsplat",VX(4, 793), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2322 { "evlwwsplatx",VX(4, 792), VX_MASK, PPCSPE, { RS, RA, RB } },
2323 { "evlwhsplat",VX(4, 797), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2324 { "evlwhsplatx",VX(4, 796), VX_MASK, PPCSPE, { RS, RA, RB } },
2325 { "evlhhesplat",VX(4, 777), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2326 { "evlhhesplatx",VX(4, 776), VX_MASK, PPCSPE, { RS, RA, RB } },
2327 { "evlhhousplat",VX(4, 781), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2328 { "evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, { RS, RA, RB } },
2329 { "evlhhossplat",VX(4, 783), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2330 { "evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, { RS, RA, RB } },
2332 { "evstdd", VX(4, 801), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2333 { "evstddx", VX(4, 800), VX_MASK, PPCSPE, { RS, RA, RB } },
2334 { "evstdw", VX(4, 803), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2335 { "evstdwx", VX(4, 802), VX_MASK, PPCSPE, { RS, RA, RB } },
2336 { "evstdh", VX(4, 805), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2337 { "evstdhx", VX(4, 804), VX_MASK, PPCSPE, { RS, RA, RB } },
2338 { "evstwwe", VX(4, 825), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2339 { "evstwwex", VX(4, 824), VX_MASK, PPCSPE, { RS, RA, RB } },
2340 { "evstwwo", VX(4, 829), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2341 { "evstwwox", VX(4, 828), VX_MASK, PPCSPE, { RS, RA, RB } },
2342 { "evstwhe", VX(4, 817), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2343 { "evstwhex", VX(4, 816), VX_MASK, PPCSPE, { RS, RA, RB } },
2344 { "evstwho", VX(4, 821), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2345 { "evstwhox", VX(4, 820), VX_MASK, PPCSPE, { RS, RA, RB } },
2347 { "evfsabs", VX(4, 644), VX_MASK, PPCSPE, { RS, RA } },
2348 { "evfsnabs", VX(4, 645), VX_MASK, PPCSPE, { RS, RA } },
2349 { "evfsneg", VX(4, 646), VX_MASK, PPCSPE, { RS, RA } },
2350 { "evfsadd", VX(4, 640), VX_MASK, PPCSPE, { RS, RA, RB } },
2351 { "evfssub", VX(4, 641), VX_MASK, PPCSPE, { RS, RA, RB } },
2352 { "evfsmul", VX(4, 648), VX_MASK, PPCSPE, { RS, RA, RB } },
2353 { "evfsdiv", VX(4, 649), VX_MASK, PPCSPE, { RS, RA, RB } },
2354 { "evfscmpgt", VX(4, 652), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2355 { "evfscmplt", VX(4, 653), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2356 { "evfscmpeq", VX(4, 654), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2357 { "evfststgt", VX(4, 668), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2358 { "evfststlt", VX(4, 669), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2359 { "evfststeq", VX(4, 670), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2371 { "efsabs", VX(4, 708), VX_MASK, PPCEFS, { RS, RA } },
2372 { "efsnabs", VX(4, 709), VX_MASK, PPCEFS, { RS, RA } },
2373 { "efsneg", VX(4, 710), VX_MASK, PPCEFS, { RS, RA } },
2374 { "efsadd", VX(4, 704), VX_MASK, PPCEFS, { RS, RA, RB } },
2375 { "efssub", VX(4, 705), VX_MASK, PPCEFS, { RS, RA, RB } },
2376 { "efsmul", VX(4, 712), VX_MASK, PPCEFS, { RS, RA, RB } },
2377 { "efsdiv", VX(4, 713), VX_MASK, PPCEFS, { RS, RA, RB } },
2378 { "efscmpgt", VX(4, 716), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2379 { "efscmplt", VX(4, 717), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2380 { "efscmpeq", VX(4, 718), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2381 { "efststgt", VX(4, 732), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2382 { "efststlt", VX(4, 733), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2383 { "efststeq", VX(4, 734), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2395 { "evmhossf", VX(4, 1031), VX_MASK, PPCSPE, { RS, RA, RB } },
2396 { "evmhossfa", VX(4, 1063), VX_MASK, PPCSPE, { RS, RA, RB } },
2397 { "evmhosmf", VX(4, 1039), VX_MASK, PPCSPE, { RS, RA, RB } },
2398 { "evmhosmfa", VX(4, 1071), VX_MASK, PPCSPE, { RS, RA, RB } },
2399 { "evmhosmi", VX(4, 1037), VX_MASK, PPCSPE, { RS, RA, RB } },
2400 { "evmhosmia", VX(4, 1069), VX_MASK, PPCSPE, { RS, RA, RB } },
2401 { "evmhoumi", VX(4, 1036), VX_MASK, PPCSPE, { RS, RA, RB } },
2402 { "evmhoumia", VX(4, 1068), VX_MASK, PPCSPE, { RS, RA, RB } },
2403 { "evmhessf", VX(4, 1027), VX_MASK, PPCSPE, { RS, RA, RB } },
2404 { "evmhessfa", VX(4, 1059), VX_MASK, PPCSPE, { RS, RA, RB } },
2405 { "evmhesmf", VX(4, 1035), VX_MASK, PPCSPE, { RS, RA, RB } },
2406 { "evmhesmfa", VX(4, 1067), VX_MASK, PPCSPE, { RS, RA, RB } },
2407 { "evmhesmi", VX(4, 1033), VX_MASK, PPCSPE, { RS, RA, RB } },
2408 { "evmhesmia", VX(4, 1065), VX_MASK, PPCSPE, { RS, RA, RB } },
2409 { "evmheumi", VX(4, 1032), VX_MASK, PPCSPE, { RS, RA, RB } },
2410 { "evmheumia", VX(4, 1064), VX_MASK, PPCSPE, { RS, RA, RB } },
2412 { "evmhossfaaw",VX(4, 1287), VX_MASK, PPCSPE, { RS, RA, RB } },
2413 { "evmhossiaaw",VX(4, 1285), VX_MASK, PPCSPE, { RS, RA, RB } },
2414 { "evmhosmfaaw",VX(4, 1295), VX_MASK, PPCSPE, { RS, RA, RB } },
2415 { "evmhosmiaaw",VX(4, 1293), VX_MASK, PPCSPE, { RS, RA, RB } },
2416 { "evmhousiaaw",VX(4, 1284), VX_MASK, PPCSPE, { RS, RA, RB } },
2417 { "evmhoumiaaw",VX(4, 1292), VX_MASK, PPCSPE, { RS, RA, RB } },
2418 { "evmhessfaaw",VX(4, 1283), VX_MASK, PPCSPE, { RS, RA, RB } },
2419 { "evmhessiaaw",VX(4, 1281), VX_MASK, PPCSPE, { RS, RA, RB } },
2420 { "evmhesmfaaw",VX(4, 1291), VX_MASK, PPCSPE, { RS, RA, RB } },
2421 { "evmhesmiaaw",VX(4, 1289), VX_MASK, PPCSPE, { RS, RA, RB } },
2422 { "evmheusiaaw",VX(4, 1280), VX_MASK, PPCSPE, { RS, RA, RB } },
2423 { "evmheumiaaw",VX(4, 1288), VX_MASK, PPCSPE, { RS, RA, RB } },
2425 { "evmhossfanw",VX(4, 1415), VX_MASK, PPCSPE, { RS, RA, RB } },
2426 { "evmhossianw",VX(4, 1413), VX_MASK, PPCSPE, { RS, RA, RB } },
2427 { "evmhosmfanw",VX(4, 1423), VX_MASK, PPCSPE, { RS, RA, RB } },
2428 { "evmhosmianw",VX(4, 1421), VX_MASK, PPCSPE, { RS, RA, RB } },
2429 { "evmhousianw",VX(4, 1412), VX_MASK, PPCSPE, { RS, RA, RB } },
2430 { "evmhoumianw",VX(4, 1420), VX_MASK, PPCSPE, { RS, RA, RB } },
2431 { "evmhessfanw",VX(4, 1411), VX_MASK, PPCSPE, { RS, RA, RB } },
2432 { "evmhessianw",VX(4, 1409), VX_MASK, PPCSPE, { RS, RA, RB } },
2433 { "evmhesmfanw",VX(4, 1419), VX_MASK, PPCSPE, { RS, RA, RB } },
2434 { "evmhesmianw",VX(4, 1417), VX_MASK, PPCSPE, { RS, RA, RB } },
2435 { "evmheusianw",VX(4, 1408), VX_MASK, PPCSPE, { RS, RA, RB } },
2436 { "evmheumianw",VX(4, 1416), VX_MASK, PPCSPE, { RS, RA, RB } },
2438 { "evmhogsmfaa",VX(4, 1327), VX_MASK, PPCSPE, { RS, RA, RB } },
2439 { "evmhogsmiaa",VX(4, 1325), VX_MASK, PPCSPE, { RS, RA, RB } },
2440 { "evmhogumiaa",VX(4, 1324), VX_MASK, PPCSPE, { RS, RA, RB } },
2441 { "evmhegsmfaa",VX(4, 1323), VX_MASK, PPCSPE, { RS, RA, RB } },
2442 { "evmhegsmiaa",VX(4, 1321), VX_MASK, PPCSPE, { RS, RA, RB } },
2443 { "evmhegumiaa",VX(4, 1320), VX_MASK, PPCSPE, { RS, RA, RB } },
2445 { "evmhogsmfan",VX(4, 1455), VX_MASK, PPCSPE, { RS, RA, RB } },
2446 { "evmhogsmian",VX(4, 1453), VX_MASK, PPCSPE, { RS, RA, RB } },
2447 { "evmhogumian",VX(4, 1452), VX_MASK, PPCSPE, { RS, RA, RB } },
2448 { "evmhegsmfan",VX(4, 1451), VX_MASK, PPCSPE, { RS, RA, RB } },
2449 { "evmhegsmian",VX(4, 1449), VX_MASK, PPCSPE, { RS, RA, RB } },
2450 { "evmhegumian",VX(4, 1448), VX_MASK, PPCSPE, { RS, RA, RB } },
2452 { "evmwhssf", VX(4, 1095), VX_MASK, PPCSPE, { RS, RA, RB } },
2453 { "evmwhssfa", VX(4, 1127), VX_MASK, PPCSPE, { RS, RA, RB } },
2454 { "evmwhsmf", VX(4, 1103), VX_MASK, PPCSPE, { RS, RA, RB } },
2455 { "evmwhsmfa", VX(4, 1135), VX_MASK, PPCSPE, { RS, RA, RB } },
2456 { "evmwhsmi", VX(4, 1101), VX_MASK, PPCSPE, { RS, RA, RB } },
2457 { "evmwhsmia", VX(4, 1133), VX_MASK, PPCSPE, { RS, RA, RB } },
2458 { "evmwhumi", VX(4, 1100), VX_MASK, PPCSPE, { RS, RA, RB } },
2459 { "evmwhumia", VX(4, 1132), VX_MASK, PPCSPE, { RS, RA, RB } },
2461 { "evmwlumi", VX(4, 1096), VX_MASK, PPCSPE, { RS, RA, RB } },
2462 { "evmwlumia", VX(4, 1128), VX_MASK, PPCSPE, { RS, RA, RB } },
2464 { "evmwlssiaaw",VX(4, 1345), VX_MASK, PPCSPE, { RS, RA, RB } },
2465 { "evmwlsmiaaw",VX(4, 1353), VX_MASK, PPCSPE, { RS, RA, RB } },
2466 { "evmwlusiaaw",VX(4, 1344), VX_MASK, PPCSPE, { RS, RA, RB } },
2467 { "evmwlumiaaw",VX(4, 1352), VX_MASK, PPCSPE, { RS, RA, RB } },
2469 { "evmwlssianw",VX(4, 1473), VX_MASK, PPCSPE, { RS, RA, RB } },
2470 { "evmwlsmianw",VX(4, 1481), VX_MASK, PPCSPE, { RS, RA, RB } },
2471 { "evmwlusianw",VX(4, 1472), VX_MASK, PPCSPE, { RS, RA, RB } },
2472 { "evmwlumianw",VX(4, 1480), VX_MASK, PPCSPE, { RS, RA, RB } },
2474 { "evmwssf", VX(4, 1107), VX_MASK, PPCSPE, { RS, RA, RB } },
2475 { "evmwssfa", VX(4, 1139), VX_MASK, PPCSPE, { RS, RA, RB } },
2476 { "evmwsmf", VX(4, 1115), VX_MASK, PPCSPE, { RS, RA, RB } },
2477 { "evmwsmfa", VX(4, 1147), VX_MASK, PPCSPE, { RS, RA, RB } },
2478 { "evmwsmi", VX(4, 1113), VX_MASK, PPCSPE, { RS, RA, RB } },
2479 { "evmwsmia", VX(4, 1145), VX_MASK, PPCSPE, { RS, RA, RB } },
2480 { "evmwumi", VX(4, 1112), VX_MASK, PPCSPE, { RS, RA, RB } },
2481 { "evmwumia", VX(4, 1144), VX_MASK, PPCSPE, { RS, RA, RB } },
2483 { "evmwssfaa", VX(4, 1363), VX_MASK, PPCSPE, { RS, RA, RB } },
2484 { "evmwsmfaa", VX(4, 1371), VX_MASK, PPCSPE, { RS, RA, RB } },
2485 { "evmwsmiaa", VX(4, 1369), VX_MASK, PPCSPE, { RS, RA, RB } },
2486 { "evmwumiaa", VX(4, 1368), VX_MASK, PPCSPE, { RS, RA, RB } },
2488 { "evmwssfan", VX(4, 1491), VX_MASK, PPCSPE, { RS, RA, RB } },
2489 { "evmwsmfan", VX(4, 1499), VX_MASK, PPCSPE, { RS, RA, RB } },
2490 { "evmwsmian", VX(4, 1497), VX_MASK, PPCSPE, { RS, RA, RB } },
2491 { "evmwumian", VX(4, 1496), VX_MASK, PPCSPE, { RS, RA, RB } },
2493 { "evaddssiaaw",VX(4, 1217), VX_MASK, PPCSPE, { RS, RA } },
2494 { "evaddsmiaaw",VX(4, 1225), VX_MASK, PPCSPE, { RS, RA } },
2495 { "evaddusiaaw",VX(4, 1216), VX_MASK, PPCSPE, { RS, RA } },
2496 { "evaddumiaaw",VX(4, 1224), VX_MASK, PPCSPE, { RS, RA } },
2498 { "evsubfssiaaw",VX(4, 1219), VX_MASK, PPCSPE, { RS, RA } },
2499 { "evsubfsmiaaw",VX(4, 1227), VX_MASK, PPCSPE, { RS, RA } },
2500 { "evsubfusiaaw",VX(4, 1218), VX_MASK, PPCSPE, { RS, RA } },
2501 { "evsubfumiaaw",VX(4, 1226), VX_MASK, PPCSPE, { RS, RA } },
2503 { "evmra", VX(4, 1220), VX_MASK, PPCSPE, { RS, RA } },
2505 { "evdivws", VX(4, 1222), VX_MASK, PPCSPE, { RS, RA, RB } },
2506 { "evdivwu", VX(4, 1223), VX_MASK, PPCSPE, { RS, RA, RB } },
2508 { "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } },
2509 { "muli", OP(7), OP_MASK, PWRCOM, { RT, RA, SI } },
2511 { "subfic", OP(8), OP_MASK, PPCCOM, { RT, RA, SI } },
2512 { "sfi", OP(8), OP_MASK, PWRCOM, { RT, RA, SI } },
2514 { "dozi", OP(9), OP_MASK, M601, { RT, RA, SI } },
2521 { "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } },
2522 { "cmpldi", OPL(10,1), OPL_MASK, PPC64, { OBF, RA, UI } },
2523 { "cmpli", OP(10), OP_MASK, PPC, { BF, L, RA, UI } },
2524 { "cmpli", OP(10), OP_MASK, PWRCOM, { BF, RA, UI } },
2526 { "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } },
2527 { "cmpdi", OPL(11,1), OPL_MASK, PPC64, { OBF, RA, SI } },
2528 { "cmpi", OP(11), OP_MASK, PPC, { BF, L, RA, SI } },
2529 { "cmpi", OP(11), OP_MASK, PWRCOM, { BF, RA, SI } },
2531 { "addic", OP(12), OP_MASK, PPCCOM, { RT, RA, SI } },
2532 { "ai", OP(12), OP_MASK, PWRCOM, { RT, RA, SI } },
2533 { "subic", OP(12), OP_MASK, PPCCOM, { RT, RA, NSI } },
2535 { "addic.", OP(13), OP_MASK, PPCCOM, { RT, RA, SI } },
2536 { "ai.", OP(13), OP_MASK, PWRCOM, { RT, RA, SI } },
2537 { "subic.", OP(13), OP_MASK, PPCCOM, { RT, RA, NSI } },
3246 { "rlwimi", M(20,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3247 { "rlimi", M(20,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3249 { "rlwimi.", M(20,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3250 { "rlimi.", M(20,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3252 { "rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, { RA, RS, SH } },
3253 { "clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, { RA, RS, MB } },
3254 { "rlwinm", M(21,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3255 { "rlinm", M(21,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3256 { "rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, { RA,RS,SH } },
3257 { "clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, { RA, RS, MB } },
3258 { "rlwinm.", M(21,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3259 { "rlinm.", M(21,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3261 { "rlmi", M(22,0), M_MASK, M601, { RA,RS,RB,MBE,ME } },
3262 { "rlmi.", M(22,1), M_MASK, M601, { RA,RS,RB,MBE,ME } },
3269 { "rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, { RA, RS, RB } },
3270 { "rlwnm", M(23,0), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
3271 { "rlnm", M(23,0), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } },
3272 { "rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, { RA, RS, RB } },
3273 { "rlwnm.", M(23,1), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
3274 { "rlnm.", M(23,1), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } },
3277 { "ori", OP(24), OP_MASK, PPCCOM, { RA, RS, UI } },
3278 { "oril", OP(24), OP_MASK, PWRCOM, { RA, RS, UI } },
3280 { "oris", OP(25), OP_MASK, PPCCOM, { RA, RS, UI } },
3281 { "oriu", OP(25), OP_MASK, PWRCOM, { RA, RS, UI } },
3283 { "xori", OP(26), OP_MASK, PPCCOM, { RA, RS, UI } },
3284 { "xoril", OP(26), OP_MASK, PWRCOM, { RA, RS, UI } },
3286 { "xoris", OP(27), OP_MASK, PPCCOM, { RA, RS, UI } },
3287 { "xoriu", OP(27), OP_MASK, PWRCOM, { RA, RS, UI } },
3289 { "andi.", OP(28), OP_MASK, PPCCOM, { RA, RS, UI } },
3290 { "andil.", OP(28), OP_MASK, PWRCOM, { RA, RS, UI } },
3292 { "andis.", OP(29), OP_MASK, PPCCOM, { RA, RS, UI } },
3293 { "andiu.", OP(29), OP_MASK, PWRCOM, { RA, RS, UI } },
3295 { "rotldi", MD(30,0,0), MDMB_MASK, PPC64, { RA, RS, SH6 } },
3296 { "clrldi", MD(30,0,0), MDSH_MASK, PPC64, { RA, RS, MB6 } },
3297 { "rldicl", MD(30,0,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3298 { "rotldi.", MD(30,0,1), MDMB_MASK, PPC64, { RA, RS, SH6 } },
3299 { "clrldi.", MD(30,0,1), MDSH_MASK, PPC64, { RA, RS, MB6 } },
3300 { "rldicl.", MD(30,0,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3302 { "rldicr", MD(30,1,0), MD_MASK, PPC64, { RA, RS, SH6, ME6 } },
3303 { "rldicr.", MD(30,1,1), MD_MASK, PPC64, { RA, RS, SH6, ME6 } },
3305 { "rldic", MD(30,2,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3306 { "rldic.", MD(30,2,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3308 { "rldimi", MD(30,3,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3309 { "rldimi.", MD(30,3,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3311 { "rotld", MDS(30,8,0), MDSMB_MASK, PPC64, { RA, RS, RB } },
3312 { "rldcl", MDS(30,8,0), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
3313 { "rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, { RA, RS, RB } },
3314 { "rldcl.", MDS(30,8,1), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
3316 { "rldcr", MDS(30,9,0), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
3317 { "rldcr.", MDS(30,9,1), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
3319 { "cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
3320 { "cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
3321 { "cmp", X(31,0), XCMP_MASK, PPC, { BF, L, RA, RB } },
3322 { "cmp", X(31,0), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
3324 { "twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, { RA, RB } },
3325 { "tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, { RA, RB } },
3326 { "twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, { RA, RB } },
3327 { "tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, { RA, RB } },
3328 { "tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, { RA, RB } },
3329 { "teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, { RA, RB } },
3330 { "twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, { RA, RB } },
3331 { "tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, { RA, RB } },
3332 { "twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, { RA, RB } },
3333 { "tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, { RA, RB } },
3334 { "twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, { RA, RB } },
3335 { "tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, { RA, RB } },
3336 { "twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, { RA, RB } },
3337 { "tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, { RA, RB } },
3338 { "twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, { RA, RB } },
3339 { "tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, { RA, RB } },
3340 { "twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, { RA, RB } },
3341 { "tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, { RA, RB } },
3342 { "twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, { RA, RB } },
3343 { "tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, { RA, RB } },
3344 { "twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, { RA, RB } },
3345 { "tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, { RA, RB } },
3346 { "twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, { RA, RB } },
3347 { "tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, { RA, RB } },
3348 { "twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, { RA, RB } },
3349 { "tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, { RA, RB } },
3350 { "twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, { RA, RB } },
3351 { "tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, { RA, RB } },
3353 { "tw", X(31,4), X_MASK, PPCCOM, { TO, RA, RB } },
3354 { "t", X(31,4), X_MASK, PWRCOM, { TO, RA, RB } },
3356 { "subfc", XO(31,8,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3357 { "sf", XO(31,8,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3358 { "subc", XO(31,8,0,0), XO_MASK, PPC, { RT, RB, RA } },
3359 { "subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3360 { "sf.", XO(31,8,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3361 { "subc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RB, RA } },
3362 { "subfco", XO(31,8,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3363 { "sfo", XO(31,8,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3364 { "subco", XO(31,8,1,0), XO_MASK, PPC, { RT, RB, RA } },
3365 { "subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3366 { "sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3367 { "subco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RB, RA } },
3369 { "mulhdu", XO(31,9,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3370 { "mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3372 { "addc", XO(31,10,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3373 { "a", XO(31,10,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3374 { "addc.", XO(31,10,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3375 { "a.", XO(31,10,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3376 { "addco", XO(31,10,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3377 { "ao", XO(31,10,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3378 { "addco.", XO(31,10,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3379 { "ao.", XO(31,10,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3381 { "mulhwu", XO(31,11,0,0), XO_MASK, PPC, { RT, RA, RB } },
3382 { "mulhwu.", XO(31,11,0,1), XO_MASK, PPC, { RT, RA, RB } },
3384 { "isellt", X(31,15), X_MASK, PPCISEL, { RT, RA, RB } },
3385 { "iselgt", X(31,47), X_MASK, PPCISEL, { RT, RA, RB } },
3386 { "iseleq", X(31,79), X_MASK, PPCISEL, { RT, RA, RB } },
3387 { "isel", XISEL(31,15), XISEL_MASK, PPCISEL, { RT, RA, RB, CRB } },
3397 { "icbt", X(31,22), X_MASK, BOOKE|PPCE300, { CT, RA, RB } },
3398 { "icbt", X(31,262), XRT_MASK, PPC403, { RA, RB } },
3401 { "lx", X(31,23), X_MASK, PWRCOM, { RT, RA, RB } },
3403 { "slw", XRC(31,24,0), X_MASK, PPCCOM, { RA, RS, RB } },
3404 { "sl", XRC(31,24,0), X_MASK, PWRCOM, { RA, RS, RB } },
3405 { "slw.", XRC(31,24,1), X_MASK, PPCCOM, { RA, RS, RB } },
3406 { "sl.", XRC(31,24,1), X_MASK, PWRCOM, { RA, RS, RB } },
3408 { "cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, { RA, RS } },
3409 { "cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, { RA, RS } },
3410 { "cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, { RA, RS } },
3411 { "cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, { RA, RS } },
3413 { "sld", XRC(31,27,0), X_MASK, PPC64, { RA, RS, RB } },
3414 { "sld.", XRC(31,27,1), X_MASK, PPC64, { RA, RS, RB } },
3416 { "and", XRC(31,28,0), X_MASK, COM, { RA, RS, RB } },
3417 { "and.", XRC(31,28,1), X_MASK, COM, { RA, RS, RB } },
3419 { "maskg", XRC(31,29,0), X_MASK, M601, { RA, RS, RB } },
3420 { "maskg.", XRC(31,29,1), X_MASK, M601, { RA, RS, RB } },
3422 { "icbte", X(31,30), X_MASK, BOOKE64, { CT, RA, RB } },
3426 { "cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
3427 { "cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
3428 { "cmpl", X(31,32), XCMP_MASK, PPC, { BF, L, RA, RB } },
3429 { "cmpl", X(31,32), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
3431 { "subf", XO(31,40,0,0), XO_MASK, PPC, { RT, RA, RB } },
3432 { "sub", XO(31,40,0,0), XO_MASK, PPC, { RT, RB, RA } },
3433 { "subf.", XO(31,40,0,1), XO_MASK, PPC, { RT, RA, RB } },
3434 { "sub.", XO(31,40,0,1), XO_MASK, PPC, { RT, RB, RA } },
3435 { "subfo", XO(31,40,1,0), XO_MASK, PPC, { RT, RA, RB } },
3436 { "subo", XO(31,40,1,0), XO_MASK, PPC, { RT, RB, RA } },
3437 { "subfo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RA, RB } },
3438 { "subo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RB, RA } },
3442 { "dcbst", X(31,54), XRT_MASK, PPC, { RA, RB } },
3445 { "lux", X(31,55), X_MASK, PWRCOM, { RT, RA, RB } },
3447 { "dcbste", X(31,62), XRT_MASK, BOOKE64, { RA, RB } },
3451 { "cntlzd", XRC(31,58,0), XRB_MASK, PPC64, { RA, RS } },
3452 { "cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, { RA, RS } },
3454 { "andc", XRC(31,60,0), X_MASK, COM, { RA, RS, RB } },
3455 { "andc.", XRC(31,60,1), X_MASK, COM, { RA, RS, RB } },
3457 { "tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, { RA, RB } },
3458 { "tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, { RA, RB } },
3459 { "tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, { RA, RB } },
3460 { "tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, { RA, RB } },
3461 { "tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, { RA, RB } },
3462 { "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, { RA, RB } },
3463 { "tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, { RA, RB } },
3464 { "tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, { RA, RB } },
3465 { "tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, { RA, RB } },
3466 { "tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, { RA, RB } },
3467 { "tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, { RA, RB } },
3468 { "tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, { RA, RB } },
3469 { "tdng", XTO(31,68,TONG), XTO_MASK, PPC64, { RA, RB } },
3470 { "tdne", XTO(31,68,TONE), XTO_MASK, PPC64, { RA, RB } },
3471 { "td", X(31,68), X_MASK, PPC64, { TO, RA, RB } },
3473 { "mulhd", XO(31,73,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3474 { "mulhd.", XO(31,73,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3476 { "mulhw", XO(31,75,0,0), XO_MASK, PPC, { RT, RA, RB } },
3477 { "mulhw.", XO(31,75,0,1), XO_MASK, PPC, { RT, RA, RB } },
3479 { "dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440, { RA, RS, RB } },
3480 { "dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440, { RA, RS, RB } },
3488 { "dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, { RA, RB } },
3489 { "dcbf", X(31,86), XLRT_MASK, PPC, { RA, RB, XRT_L } },
3493 { "dcbfe", X(31,94), XRT_MASK, BOOKE64, { RA, RB } },
3497 { "neg", XO(31,104,0,0), XORB_MASK, COM, { RT, RA } },
3498 { "neg.", XO(31,104,0,1), XORB_MASK, COM, { RT, RA } },
3499 { "nego", XO(31,104,1,0), XORB_MASK, COM, { RT, RA } },
3500 { "nego.", XO(31,104,1,1), XORB_MASK, COM, { RT, RA } },
3502 { "mul", XO(31,107,0,0), XO_MASK, M601, { RT, RA, RB } },
3503 { "mul.", XO(31,107,0,1), XO_MASK, M601, { RT, RA, RB } },
3504 { "mulo", XO(31,107,1,0), XO_MASK, M601, { RT, RA, RB } },
3505 { "mulo.", XO(31,107,1,1), XO_MASK, M601, { RT, RA, RB } },
3509 { "clf", X(31,118), XTO_MASK, POWER, { RA, RB } },
3513 { "popcntb", X(31,122), XRB_MASK, POWER5, { RA, RS } },
3515 { "not", XRC(31,124,0), X_MASK, COM, { RA, RS, RBS } },
3516 { "nor", XRC(31,124,0), X_MASK, COM, { RA, RS, RB } },
3517 { "not.", XRC(31,124,1), X_MASK, COM, { RA, RS, RBS } },
3518 { "nor.", XRC(31,124,1), X_MASK, COM, { RA, RS, RB } },
3526 { "dcbtstls",X(31,134), X_MASK, PPCCHLK, { CT, RA, RB }},
3528 { "subfe", XO(31,136,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3529 { "sfe", XO(31,136,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3530 { "subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3531 { "sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3532 { "subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3533 { "sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3534 { "subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3535 { "sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3537 { "adde", XO(31,138,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3538 { "ae", XO(31,138,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3539 { "adde.", XO(31,138,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3540 { "ae.", XO(31,138,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3541 { "addeo", XO(31,138,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3542 { "aeo", XO(31,138,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3543 { "addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3544 { "aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3546 { "dcbtstlse",X(31,142),X_MASK, PPCCHLK64, { CT, RA, RB }},
3559 { "stx", X(31,151), X_MASK, PWRCOM, { RS, RA, RB } },
3565 { "slq", XRC(31,152,0), X_MASK, M601, { RA, RS, RB } },
3566 { "slq.", XRC(31,152,1), X_MASK, M601, { RA, RS, RB } },
3568 { "sle", XRC(31,153,0), X_MASK, M601, { RA, RS, RB } },
3569 { "sle.", XRC(31,153,1), X_MASK, M601, { RA, RS, RB } },
3571 { "prtyw", X(31,154), XRB_MASK, POWER6, { RA, RS } },
3575 { "dcbtls", X(31,166), X_MASK, PPCCHLK, { CT, RA, RB }},
3576 { "dcbtlse", X(31,174), X_MASK, PPCCHLK64, { CT, RA, RB }},
3585 { "sliq", XRC(31,184,0), X_MASK, M601, { RA, RS, SH } },
3586 { "sliq.", XRC(31,184,1), X_MASK, M601, { RA, RS, SH } },
3588 { "prtyd", X(31,186), XRB_MASK, POWER6, { RA, RS } },
3592 { "subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3593 { "sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3594 { "subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3595 { "sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3596 { "subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3597 { "sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3598 { "subfzeo.",XO(31,200,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3599 { "sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3601 { "addze", XO(31,202,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3602 { "aze", XO(31,202,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3603 { "addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3604 { "aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3605 { "addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3606 { "azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3607 { "addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3608 { "azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3616 { "sllq", XRC(31,216,0), X_MASK, M601, { RA, RS, RB } },
3617 { "sllq.", XRC(31,216,1), X_MASK, M601, { RA, RS, RB } },
3619 { "sleq", XRC(31,217,0), X_MASK, M601, { RA, RS, RB } },
3620 { "sleq.", XRC(31,217,1), X_MASK, M601, { RA, RS, RB } },
3624 { "icblc", X(31,230), X_MASK, PPCCHLK, { CT, RA, RB }},
3626 { "subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3627 { "sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3628 { "subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3629 { "sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3630 { "subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3631 { "sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3632 { "subfmeo.",XO(31,232,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3633 { "sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3635 { "mulld", XO(31,233,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3636 { "mulld.", XO(31,233,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3637 { "mulldo", XO(31,233,1,0), XO_MASK, PPC64, { RT, RA, RB } },
3638 { "mulldo.", XO(31,233,1,1), XO_MASK, PPC64, { RT, RA, RB } },
3640 { "addme", XO(31,234,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3641 { "ame", XO(31,234,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3642 { "addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3643 { "ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3644 { "addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3645 { "ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3646 { "addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3647 { "ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3649 { "mullw", XO(31,235,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3650 { "muls", XO(31,235,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3651 { "mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3652 { "muls.", XO(31,235,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3653 { "mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3654 { "mulso", XO(31,235,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3655 { "mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3656 { "mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3658 { "icblce", X(31,238), X_MASK, PPCCHLK64, { CT, RA, RB }},
3662 { "dcbtst", X(31,246), X_MASK, PPC, { CT, RA, RB } },
3666 { "slliq", XRC(31,248,0), X_MASK, M601, { RA, RS, SH } },
3667 { "slliq.", XRC(31,248,1), X_MASK, M601, { RA, RS, SH } },
3669 { "dcbtste", X(31,253), X_MASK, BOOKE64, { CT, RA, RB } },
3673 { "mfdcrx", X(31,259), X_MASK, BOOKE, { RS, RA } },
3675 { "doz", XO(31,264,0,0), XO_MASK, M601, { RT, RA, RB } },
3676 { "doz.", XO(31,264,0,1), XO_MASK, M601, { RT, RA, RB } },
3677 { "dozo", XO(31,264,1,0), XO_MASK, M601, { RT, RA, RB } },
3678 { "dozo.", XO(31,264,1,1), XO_MASK, M601, { RT, RA, RB } },
3680 { "add", XO(31,266,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3681 { "cax", XO(31,266,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3682 { "add.", XO(31,266,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3683 { "cax.", XO(31,266,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3684 { "addo", XO(31,266,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3685 { "caxo", XO(31,266,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3686 { "addo.", XO(31,266,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3687 { "caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3691 { "mfapidi", X(31,275), X_MASK, BOOKE, { RT, RA } },
3693 { "lscbx", XRC(31,277,0), X_MASK, M601, { RT, RA, RB } },
3694 { "lscbx.", XRC(31,277,1), X_MASK, M601, { RT, RA, RB } },
3696 { "dcbt", X(31,278), X_MASK, PPC, { CT, RA, RB } },
3700 { "eqv", XRC(31,284,0), X_MASK, COM, { RA, RS, RB } },
3701 { "eqv.", XRC(31,284,1), X_MASK, COM, { RA, RS, RB } },
3703 { "dcbte", X(31,286), X_MASK, BOOKE64, { CT, RA, RB } },
3710 { "eciwx", X(31,310), X_MASK, PPC, { RT, RA, RB } },
3714 { "xor", XRC(31,316,0), X_MASK, COM, { RA, RS, RB } },
3715 { "xor.", XRC(31,316,1), X_MASK, COM, { RA, RS, RB } },
3755 { "div", XO(31,331,0,0), XO_MASK, M601, { RT, RA, RB } },
3756 { "div.", XO(31,331,0,1), XO_MASK, M601, { RT, RA, RB } },
3757 { "divo", XO(31,331,1,0), XO_MASK, M601, { RT, RA, RB } },
3758 { "divo.", XO(31,331,1,1), XO_MASK, M601, { RT, RA, RB } },
3953 { "dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3954 { "dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3960 { "dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3961 { "dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3963 { "dccci", X(31,454), XRT_MASK, PPC403|PPC440, { RA, RB } },
3965 { "abs", XO(31,360,0,0), XORB_MASK, M601, { RT, RA } },
3966 { "abs.", XO(31,360,0,1), XORB_MASK, M601, { RT, RA } },
3967 { "abso", XO(31,360,1,0), XORB_MASK, M601, { RT, RA } },
3968 { "abso.", XO(31,360,1,1), XORB_MASK, M601, { RT, RA } },
3970 { "divs", XO(31,363,0,0), XO_MASK, M601, { RT, RA, RB } },
3971 { "divs.", XO(31,363,0,1), XO_MASK, M601, { RT, RA, RB } },
3972 { "divso", XO(31,363,1,0), XO_MASK, M601, { RT, RA, RB } },
3973 { "divso.", XO(31,363,1,1), XO_MASK, M601, { RT, RA, RB } },
3983 { "mtdcrx", X(31,387), X_MASK, BOOKE, { RA, RS } },
3985 { "dcblc", X(31,390), X_MASK, PPCCHLK, { CT, RA, RB }},
3987 { "subfe64", XO(31,392,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3988 { "subfe64o",XO(31,392,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3990 { "adde64", XO(31,394,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3991 { "adde64o", XO(31,394,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3993 { "dcblce", X(31,398), X_MASK, PPCCHLK64, { CT, RA, RB }},
3999 { "cmpb", X(31,508), X_MASK, POWER6, { RA, RS, RB } },
4001 { "lfqx", X(31,791), X_MASK, POWER2, { FRT, RA, RB } },
4003 { "lfdpx", X(31,791), X_MASK, POWER6, { FRT, RA, RB } },
4005 { "lfqux", X(31,823), X_MASK, POWER2, { FRT, RA, RB } },
4007 { "stfqx", X(31,919), X_MASK, POWER2, { FRS, RA, RB } },
4009 { "stfdpx", X(31,919), X_MASK, POWER6, { FRS, RA, RB } },
4011 { "stfqux", X(31,951), X_MASK, POWER2, { FRS, RA, RB } },
4013 { "orc", XRC(31,412,0), X_MASK, COM, { RA, RS, RB } },
4014 { "orc.", XRC(31,412,1), X_MASK, COM, { RA, RS, RB } },
4016 { "sradi", XS(31,413,0), XS_MASK, PPC64, { RA, RS, SH6 } },
4017 { "sradi.", XS(31,413,1), XS_MASK, PPC64, { RA, RS, SH6 } },
4023 { "ecowx", X(31,438), X_MASK, PPC, { RT, RA, RB } },
4029 { "mr", XRC(31,444,0), X_MASK, COM, { RA, RS, RBS } },
4030 { "or", XRC(31,444,0), X_MASK, COM, { RA, RS, RB } },
4031 { "mr.", XRC(31,444,1), X_MASK, COM, { RA, RS, RBS } },
4032 { "or.", XRC(31,444,1), X_MASK, COM, { RA, RS, RB } },
4070 { "subfze64",XO(31,456,0,0), XORB_MASK, BOOKE64, { RT, RA } },
4071 { "subfze64o",XO(31,456,1,0), XORB_MASK, BOOKE64, { RT, RA } },
4073 { "divdu", XO(31,457,0,0), XO_MASK, PPC64, { RT, RA, RB } },
4074 { "divdu.", XO(31,457,0,1), XO_MASK, PPC64, { RT, RA, RB } },
4075 { "divduo", XO(31,457,1,0), XO_MASK, PPC64, { RT, RA, RB } },
4076 { "divduo.", XO(31,457,1,1), XO_MASK, PPC64, { RT, RA, RB } },
4078 { "addze64", XO(31,458,0,0), XORB_MASK, BOOKE64, { RT, RA } },
4079 { "addze64o",XO(31,458,1,0), XORB_MASK, BOOKE64, { RT, RA } },
4081 { "divwu", XO(31,459,0,0), XO_MASK, PPC, { RT, RA, RB } },
4082 { "divwu.", XO(31,459,0,1), XO_MASK, PPC, { RT, RA, RB } },
4083 { "divwuo", XO(31,459,1,0), XO_MASK, PPC, { RT, RA, RB } },
4084 { "divwuo.", XO(31,459,1,1), XO_MASK, PPC, { RT, RA, RB } },
4240 { "dcbi", X(31,470), XRT_MASK, PPC, { RA, RB } },
4242 { "nand", XRC(31,476,0), X_MASK, COM, { RA, RS, RB } },
4243 { "nand.", XRC(31,476,1), X_MASK, COM, { RA, RS, RB } },
4245 { "dcbie", X(31,478), XRT_MASK, BOOKE64, { RA, RB } },
4247 { "dcread", X(31,486), X_MASK, PPC403|PPC440, { RT, RA, RB }},
4251 { "icbtls", X(31,486), X_MASK, PPCCHLK, { CT, RA, RB }},
4253 { "nabs", XO(31,488,0,0), XORB_MASK, M601, { RT, RA } },
4254 { "subfme64",XO(31,488,0,0), XORB_MASK, BOOKE64, { RT, RA } },
4255 { "nabs.", XO(31,488,0,1), XORB_MASK, M601, { RT, RA } },
4256 { "nabso", XO(31,488,1,0), XORB_MASK, M601, { RT, RA } },
4257 { "subfme64o",XO(31,488,1,0), XORB_MASK, BOOKE64, { RT, RA } },
4258 { "nabso.", XO(31,488,1,1), XORB_MASK, M601, { RT, RA } },
4260 { "divd", XO(31,489,0,0), XO_MASK, PPC64, { RT, RA, RB } },
4261 { "divd.", XO(31,489,0,1), XO_MASK, PPC64, { RT, RA, RB } },
4262 { "divdo", XO(31,489,1,0), XO_MASK, PPC64, { RT, RA, RB } },
4263 { "divdo.", XO(31,489,1,1), XO_MASK, PPC64, { RT, RA, RB } },
4265 { "addme64", XO(31,490,0,0), XORB_MASK, BOOKE64, { RT, RA } },
4266 { "addme64o",XO(31,490,1,0), XORB_MASK, BOOKE64, { RT, RA } },
4268 { "divw", XO(31,491,0,0), XO_MASK, PPC, { RT, RA, RB } },
4269 { "divw.", XO(31,491,0,1), XO_MASK, PPC, { RT, RA, RB } },
4270 { "divwo", XO(31,491,1,0), XO_MASK, PPC, { RT, RA, RB } },
4271 { "divwo.", XO(31,491,1,1), XO_MASK, PPC, { RT, RA, RB } },
4273 { "icbtlse", X(31,494), X_MASK, PPCCHLK64, { CT, RA, RB }},
4277 { "cli", X(31,502), XRB_MASK, POWER, { RT, RA } },
4279 { "stdcxe.", XRC(31,511,1), X_MASK, BOOKE64, { RS, RA, RB } },
4286 { "clcs", X(31,531), XRB_MASK, M601, { RT, RA } },
4291 { "lsx", X(31,533), X_MASK, PWRCOM, { RT, RA, RB } },
4294 { "lbrx", X(31,534), X_MASK, PWRCOM, { RT, RA, RB } },
4298 { "srw", XRC(31,536,0), X_MASK, PPCCOM, { RA, RS, RB } },
4299 { "sr", XRC(31,536,0), X_MASK, PWRCOM, { RA, RS, RB } },
4300 { "srw.", XRC(31,536,1), X_MASK, PPCCOM, { RA, RS, RB } },
4301 { "sr.", XRC(31,536,1), X_MASK, PWRCOM, { RA, RS, RB } },
4303 { "rrib", XRC(31,537,0), X_MASK, M601, { RA, RS, RB } },
4304 { "rrib.", XRC(31,537,1), X_MASK, M601, { RA, RS, RB } },
4306 { "srd", XRC(31,539,0), X_MASK, PPC64, { RA, RS, RB } },
4307 { "srd.", XRC(31,539,1), X_MASK, PPC64, { RA, RS, RB } },
4309 { "maskir", XRC(31,541,0), X_MASK, M601, { RA, RS, RB } },
4310 { "maskir.", XRC(31,541,1), X_MASK, M601, { RA, RS, RB } },
4341 { "mfsri", X(31,627), X_MASK, PWRCOM, { RT, RA, RB } },
4343 { "dclst", X(31,630), XRB_MASK, PWRCOM, { RS, RA } },
4361 { "srq", XRC(31,664,0), X_MASK, M601, { RA, RS, RB } },
4362 { "srq.", XRC(31,664,1), X_MASK, M601, { RA, RS, RB } },
4364 { "sre", XRC(31,665,0), X_MASK, M601, { RA, RS, RB } },
4365 { "sre.", XRC(31,665,1), X_MASK, M601, { RA, RS, RB } },
4373 { "sriq", XRC(31,696,0), X_MASK, M601, { RA, RS, SH } },
4374 { "sriq.", XRC(31,696,1), X_MASK, M601, { RA, RS, SH } },
4383 { "srlq", XRC(31,728,0), X_MASK, M601, { RA, RS, RB } },
4384 { "srlq.", XRC(31,728,1), X_MASK, M601, { RA, RS, RB } },
4386 { "sreq", XRC(31,729,0), X_MASK, M601, { RA, RS, RB } },
4387 { "sreq.", XRC(31,729,1), X_MASK, M601, { RA, RS, RB } },
4393 { "dcba", X(31,758), XRT_MASK, PPC405 | BOOKE, { RA, RB } },
4397 { "srliq", XRC(31,760,0), X_MASK, M601, { RA, RS, SH } },
4398 { "srliq.", XRC(31,760,1), X_MASK, M601, { RA, RS, SH } },
4400 { "dcbae", X(31,766), XRT_MASK, BOOKE64, { RA, RB } },
4404 { "tlbivax", X(31,786), XRT_MASK, BOOKE, { RA, RB } },
4405 { "tlbivaxe",X(31,787), XRT_MASK, BOOKE64, { RA, RB } },
4411 { "sraw", XRC(31,792,0), X_MASK, PPCCOM, { RA, RS, RB } },
4412 { "sra", XRC(31,792,0), X_MASK, PWRCOM, { RA, RS, RB } },
4413 { "sraw.", XRC(31,792,1), X_MASK, PPCCOM, { RA, RS, RB } },
4414 { "sra.", XRC(31,792,1), X_MASK, PWRCOM, { RA, RS, RB } },
4416 { "srad", XRC(31,794,0), X_MASK, PPC64, { RA, RS, RB } },
4417 { "srad.", XRC(31,794,1), X_MASK, PPC64, { RA, RS, RB } },
4424 { "rac", X(31,818), X_MASK, PWRCOM, { RT, RA, RB } },
4431 { "srawi", XRC(31,824,0), X_MASK, PPCCOM, { RA, RS, SH } },
4432 { "srai", XRC(31,824,0), X_MASK, PWRCOM, { RA, RS, SH } },
4433 { "srawi.", XRC(31,824,1), X_MASK, PPCCOM, { RA, RS, SH } },
4434 { "srai.", XRC(31,824,1), X_MASK, PWRCOM, { RA, RS, SH } },
4447 { "tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE, { RTO, RA, RB } },
4448 { "tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE, { RTO, RA, RB } },
4449 { "tlbsxe", XRC(31,915,0), X_MASK, BOOKE64, { RA, RB } },
4450 { "tlbsxe.", XRC(31,915,1), X_MASK, BOOKE64, { RA, RB } },
4458 { "sraq", XRC(31,920,0), X_MASK, M601, { RA, RS, RB } },
4459 { "sraq.", XRC(31,920,1), X_MASK, M601, { RA, RS, RB } },
4461 { "srea", XRC(31,921,0), X_MASK, M601, { RA, RS, RB } },
4462 { "srea.", XRC(31,921,1), X_MASK, M601, { RA, RS, RB } },
4464 { "extsh", XRC(31,922,0), XRB_MASK, PPCCOM, { RA, RS } },
4465 { "exts", XRC(31,922,0), XRB_MASK, PWRCOM, { RA, RS } },
4466 { "extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, { RA, RS } },
4467 { "exts.", XRC(31,922,1), XRB_MASK, PWRCOM, { RA, RS } },
4473 { "tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, { RT, RA } },
4474 { "tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, { RT, RA } },
4479 { "sraiq", XRC(31,952,0), X_MASK, M601, { RA, RS, SH } },
4480 { "sraiq.", XRC(31,952,1), X_MASK, M601, { RA, RS, SH } },
4482 { "extsb", XRC(31,954,0), XRB_MASK, PPC, { RA, RS} },
4483 { "extsb.", XRC(31,954,1), XRB_MASK, PPC, { RA, RS} },
4487 { "iccci", X(31,966), XRT_MASK, PPC403|PPC440, { RA, RB } },
4489 { "tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, { RT, RA } },
4490 { "tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, { RT, RA } },
4496 { "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } },
4500 { "extsw", XRC(31,986,0), XRB_MASK, PPC64 | BOOKE64,{ RA, RS } },
4501 { "extsw.", XRC(31,986,1), XRB_MASK, PPC64, { RA, RS } },
4503 { "icread", X(31,998), XRT_MASK, PPC403|PPC440, { RA, RB } },
4505 { "icbie", X(31,990), XRT_MASK, BOOKE64, { RA, RB } },
4512 { "dcbzl", XOPL(31,1014,1), XRT_MASK,POWER4, { RA, RB } },
4513 { "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
4514 { "dclz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
4516 { "dcbze", X(31,1022), XRT_MASK, BOOKE64, { RA, RB } },
4518 { "lvebx", X(31, 7), X_MASK, PPCVEC, { VD, RA, RB } },
4519 { "lvehx", X(31, 39), X_MASK, PPCVEC, { VD, RA, RB } },
4520 { "lvewx", X(31, 71), X_MASK, PPCVEC, { VD, RA, RB } },
4521 { "lvsl", X(31, 6), X_MASK, PPCVEC, { VD, RA, RB } },
4522 { "lvsr", X(31, 38), X_MASK, PPCVEC, { VD, RA, RB } },
4523 { "lvx", X(31, 103), X_MASK, PPCVEC, { VD, RA, RB } },
4524 { "lvxl", X(31, 359), X_MASK, PPCVEC, { VD, RA, RB } },
4525 { "stvebx", X(31, 135), X_MASK, PPCVEC, { VS, RA, RB } },
4526 { "stvehx", X(31, 167), X_MASK, PPCVEC, { VS, RA, RB } },
4527 { "stvewx", X(31, 199), X_MASK, PPCVEC, { VS, RA, RB } },
4528 { "stvx", X(31, 231), X_MASK, PPCVEC, { VS, RA, RB } },
4529 { "stvxl", X(31, 487), X_MASK, PPCVEC, { VS, RA, RB } },
4724 { "stfq", OP(60), OP_MASK, POWER2, { FRS, D, RA } },
4726 { "stfqu", OP(61), OP_MASK, POWER2, { FRS, D, RA } },