Lines Matching refs:srcreg
247 int srcreg; in misaligned_store() local
255 srcreg = (opcode >> 4) & 0x3f; in misaligned_store()
265 *(__u16 *) &buffer = (__u16) regs->regs[srcreg]; in misaligned_store()
268 *(__u32 *) &buffer = (__u32) regs->regs[srcreg]; in misaligned_store()
271 buffer = regs->regs[srcreg]; in misaligned_store()
284 __u64 val = regs->regs[srcreg]; in misaligned_store()
391 int srcreg; in misaligned_fpu_store() local
399 srcreg = (opcode >> 4) & 0x3f; in misaligned_fpu_store()
422 buflo = current->thread.xstate->hardfpu.fp_regs[srcreg]; in misaligned_fpu_store()
426 buflo = current->thread.xstate->hardfpu.fp_regs[srcreg]; in misaligned_fpu_store()
427 bufhi = current->thread.xstate->hardfpu.fp_regs[srcreg+1]; in misaligned_fpu_store()
430 bufhi = current->thread.xstate->hardfpu.fp_regs[srcreg]; in misaligned_fpu_store()
431 buflo = current->thread.xstate->hardfpu.fp_regs[srcreg+1]; in misaligned_fpu_store()
433 buflo = current->thread.xstate->hardfpu.fp_regs[srcreg]; in misaligned_fpu_store()
434 bufhi = current->thread.xstate->hardfpu.fp_regs[srcreg+1]; in misaligned_fpu_store()