78 static int imx_phy_crbit_assert(void __iomem *mmio, u32 bit, bool assert)  in imx_phy_crbit_assert()  argument
85 	crval = readl(mmio + IMX_P0PHYCR);  in imx_phy_crbit_assert()
90 	writel(crval, mmio + IMX_P0PHYCR);  in imx_phy_crbit_assert()
94 		srval = readl(mmio + IMX_P0PHYSR);  in imx_phy_crbit_assert()
103 static int imx_phy_reg_addressing(u16 addr, void __iomem *mmio)  in imx_phy_reg_addressing()  argument
109 	writel(crval, mmio + IMX_P0PHYCR);  in imx_phy_reg_addressing()
112 	ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_ADDR, true);  in imx_phy_reg_addressing()
117 	ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_ADDR, false);  in imx_phy_reg_addressing()
124 static int imx_phy_reg_write(u16 val, void __iomem *mmio)  in imx_phy_reg_write()  argument
130 	writel(crval, mmio + IMX_P0PHYCR);  in imx_phy_reg_write()
133 	ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_DATA, true);  in imx_phy_reg_write()
138 	ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_DATA, false);  in imx_phy_reg_write()
148 		writel(crval, mmio + IMX_P0PHYCR);  in imx_phy_reg_write()
153 	ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_WRITE, true);  in imx_phy_reg_write()
158 	ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_WRITE, false);  in imx_phy_reg_write()
166 static int imx_phy_reg_read(u16 *val, void __iomem *mmio)  in imx_phy_reg_read()  argument
171 	ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_READ, true);  in imx_phy_reg_read()
176 	*val = readl(mmio + IMX_P0PHYSR) & IMX_P0PHYSR_CR_DATA_OUT;  in imx_phy_reg_read()
179 	ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_READ, false);  in imx_phy_reg_read()
188 	void __iomem *mmio = hpriv->mmio;  in imx_sata_phy_reset()  local
194 	ret = imx_phy_reg_addressing(IMX_CLOCK_RESET, mmio);  in imx_sata_phy_reset()
197 	ret = imx_phy_reg_write(IMX_CLOCK_RESET_RESET, mmio);  in imx_sata_phy_reset()
204 		ret = imx_phy_reg_addressing(IMX_LANE0_OUT_STAT, mmio);  in imx_sata_phy_reset()
207 		ret = imx_phy_reg_read(&val, mmio);  in imx_sata_phy_reset()
302 	void __iomem *mmio = hpriv->mmio;  in ahci_imx_error_handler()  local
319 	reg_val = readl(mmio + IMX_P0PHYCR);  in ahci_imx_error_handler()
320 	writel(reg_val | IMX_P0PHYCR_TEST_PDDQ, mmio + IMX_P0PHYCR);  in ahci_imx_error_handler()
611 	reg_val = readl(hpriv->mmio + HOST_CAP);  in imx_ahci_probe()
614 		writel(reg_val, hpriv->mmio + HOST_CAP);  in imx_ahci_probe()
616 	reg_val = readl(hpriv->mmio + HOST_PORTS_IMPL);  in imx_ahci_probe()
619 		writel(reg_val, hpriv->mmio + HOST_PORTS_IMPL);  in imx_ahci_probe()
623 	writel(reg_val, hpriv->mmio + IMX_TIMER1MS);  in imx_ahci_probe()