Lines Matching refs:rreg_t
640 typedef u_int rreg_t; typedef
718 rreg_t mode_reg_0; /* Mode register 0 */
719 rreg_t protocol_id; /* Protocol ID */
720 rreg_t mask_reg; /* Mask Register */
721 rreg_t intr_status_reg;/* Interrupt status register */
722 rreg_t drp_pkt_cntr; /* Dropped packet cntr (clear on read) */
723 rreg_t err_cntr; /* Error Counter (cleared on read) */
725 rreg_t raw_base_adr; /* Base addr for raw cell Q */
727 rreg_t cell_ctr0; /* Cell Counter 0 (cleared when read) */
728 rreg_t cell_ctr1; /* Cell Counter 1 (cleared when read) */
730 rreg_t cmd_reg; /* Command register */
731 rreg_t desc_base; /* Base address for description table */
732 rreg_t vc_lkup_base; /* Base address for VC lookup table */
733 rreg_t reass_base; /* Base address for reassembler table */
734 rreg_t queue_base; /* Base address for Communication queue */
736 rreg_t pkt_tm_cnt; /* Packet Timeout and count register */
737 rreg_t tmout_range; /* Range of reassembley IDs for timeout */
738 rreg_t intrvl_cntr; /* Packet aging interval counter */
739 rreg_t tmout_indx; /* index of pkt being tested for aging */
741 rreg_t vp_lkup_base; /* Base address for VP lookup table */
742 rreg_t vp_filter; /* VP filter register */
743 rreg_t abr_lkup_base; /* Base address of ABR VC Table */
745 rreg_t fdq_st_adr; /* Free desc queue start address */
746 rreg_t fdq_ed_adr; /* Free desc queue end address */
747 rreg_t fdq_rd_ptr; /* Free desc queue read pointer */
748 rreg_t fdq_wr_ptr; /* Free desc queue write pointer */
749 rreg_t pcq_st_adr; /* Packet Complete queue start address */
750 rreg_t pcq_ed_adr; /* Packet Complete queue end address */
751 rreg_t pcq_rd_ptr; /* Packet Complete queue read pointer */
752 rreg_t pcq_wr_ptr; /* Packet Complete queue write pointer */
753 rreg_t excp_st_adr; /* Exception queue start address */
754 rreg_t excp_ed_adr; /* Exception queue end address */
755 rreg_t excp_rd_ptr; /* Exception queue read pointer */
756 rreg_t excp_wr_ptr; /* Exception queue write pointer */
758 rreg_t raw_st_adr; /* Raw Cell start address */
759 rreg_t raw_ed_adr; /* Raw Cell end address */
760 rreg_t raw_rd_ptr; /* Raw Cell read pointer */
761 rreg_t raw_wr_ptr; /* Raw Cell write pointer */
762 rreg_t state_reg; /* State Register */
764 rreg_t buf_size; /* Buffer size */
766 rreg_t xtra_rm_offset; /* Offset of the additional turnaround RM */
768 rreg_t drp_pkt_cntr_nc;/* Dropped Packet cntr, Not clear on rd */
769 rreg_t err_cntr_nc; /* Error Counter, Not clear on read */
771 rreg_t cell_ctr0_nc; /* Cell Counter 0, Not clear on read */
772 rreg_t cell_ctr1_nc; /* Cell Counter 1, Not clear on read */