104 static void malformed_message(struct xilly_endpoint *endpoint, u32 *buf)  in malformed_message()  argument
115 	dev_warn(endpoint->dev,  in malformed_message()
477 		channel->endpoint = ep;  in xilly_setupchannels()
565 static int xilly_scan_idt(struct xilly_endpoint *endpoint,  in xilly_scan_idt()  argument
569 	unsigned char *idt = endpoint->channels[1]->wr_buffers[0]->addr;  in xilly_scan_idt()
570 	unsigned char *end_of_idt = idt + endpoint->idtlen - 4;  in xilly_scan_idt()
588 		dev_err(endpoint->dev,  in xilly_scan_idt()
594 	len = endpoint->idtlen - (3 + ((int) (scan - idt)));  in xilly_scan_idt()
597 		dev_err(endpoint->dev,  in xilly_scan_idt()
603 	endpoint->num_channels = count;  in xilly_scan_idt()
608 static int xilly_obtain_idt(struct xilly_endpoint *endpoint)  in xilly_obtain_idt()  argument
614 	channel = endpoint->channels[1]; /* This should be generated ad-hoc */  in xilly_obtain_idt()
620 		  endpoint->registers + fpga_buf_ctrl_reg);  in xilly_obtain_idt()
627 		dev_err(endpoint->dev, "Failed to obtain IDT. Aborting.\n");  in xilly_obtain_idt()
629 		if (endpoint->fatal_error)  in xilly_obtain_idt()
635 	endpoint->ephw->hw_sync_sgl_for_cpu(  in xilly_obtain_idt()
636 		channel->endpoint,  in xilly_obtain_idt()
641 	if (channel->wr_buffers[0]->end_offset != endpoint->idtlen) {  in xilly_obtain_idt()
642 		dev_err(endpoint->dev,  in xilly_obtain_idt()
644 			channel->wr_buffers[0]->end_offset, endpoint->idtlen);  in xilly_obtain_idt()
649 		     endpoint->idtlen+1) != 0) {  in xilly_obtain_idt()
650 		dev_err(endpoint->dev, "IDT failed CRC check. Aborting.\n");  in xilly_obtain_idt()
658 		dev_err(endpoint->dev,  in xilly_obtain_idt()
683 	if (channel->endpoint->fatal_error)  in xillybus_read()
750 				channel->endpoint->ephw->hw_sync_sgl_for_cpu(  in xillybus_read()
751 					channel->endpoint,  in xillybus_read()
766 				channel->endpoint->ephw->hw_sync_sgl_for_device(  in xillybus_read()
767 					channel->endpoint,  in xillybus_read()
782 					  channel->endpoint->registers +  in xillybus_read()
864 				mutex_lock(&channel->endpoint->register_mutex);  in xillybus_read()
867 					  channel->endpoint->registers +  in xillybus_read()
873 					  channel->endpoint->registers +  in xillybus_read()
876 				mutex_unlock(&channel->endpoint->  in xillybus_read()
911 			if (channel->endpoint->fatal_error)  in xillybus_read()
940 				if (channel->endpoint->fatal_error)  in xillybus_read()
962 				  channel->endpoint->registers +  in xillybus_read()
977 	if (channel->endpoint->fatal_error)  in xillybus_read()
1004 	if (channel->endpoint->fatal_error)  in xillybus_myflush()
1070 		channel->endpoint->ephw->hw_sync_sgl_for_device(  in xillybus_myflush()
1071 			channel->endpoint,  in xillybus_myflush()
1076 		mutex_lock(&channel->endpoint->register_mutex);  in xillybus_myflush()
1079 			  channel->endpoint->registers + fpga_buf_offset_reg);  in xillybus_myflush()
1084 			  channel->endpoint->registers + fpga_buf_ctrl_reg);  in xillybus_myflush()
1086 		mutex_unlock(&channel->endpoint->register_mutex);  in xillybus_myflush()
1135 			dev_warn(channel->endpoint->dev,  in xillybus_myflush()
1151 	if (channel->endpoint->fatal_error)  in xillybus_myflush()
1175 		dev_warn(channel->endpoint->dev,  in xillybus_autoflush()
1178 		dev_err(channel->endpoint->dev,  in xillybus_autoflush()
1196 	if (channel->endpoint->fatal_error)  in xillybus_write()
1290 				channel->endpoint->ephw->hw_sync_sgl_for_cpu(  in xillybus_write()
1291 					channel->endpoint,  in xillybus_write()
1312 				channel->endpoint->ephw->hw_sync_sgl_for_device(  in xillybus_write()
1313 					channel->endpoint,  in xillybus_write()
1318 				mutex_lock(&channel->endpoint->register_mutex);  in xillybus_write()
1321 					  channel->endpoint->registers +  in xillybus_write()
1327 					  channel->endpoint->registers +  in xillybus_write()
1330 				mutex_unlock(&channel->endpoint->  in xillybus_write()
1340 				if (channel->endpoint->fatal_error)  in xillybus_write()
1377 			if (channel->endpoint->fatal_error)  in xillybus_write()
1393 	if (channel->endpoint->fatal_error)  in xillybus_write()
1415 	struct xilly_endpoint *ep_iter, *endpoint = NULL;  in xillybus_open()  local
1425 			endpoint = ep_iter;  in xillybus_open()
1431 	if (!endpoint) {  in xillybus_open()
1437 	if (endpoint->fatal_error)  in xillybus_open()
1440 	channel = endpoint->channels[1 + minor - endpoint->lowest_minor];  in xillybus_open()
1458 		dev_err(endpoint->dev,  in xillybus_open()
1465 		dev_err(endpoint->dev,  in xillybus_open()
1521 				  channel->endpoint->registers +  in xillybus_open()
1542 				  channel->endpoint->registers +  in xillybus_open()
1570 	if (channel->endpoint->fatal_error)  in xillybus_release()
1586 				  channel->endpoint->registers +  in xillybus_release()
1600 				  channel->endpoint->registers +  in xillybus_release()
1650 					dev_warn(channel->endpoint->dev,  in xillybus_release()
1676 	if (channel->endpoint->fatal_error)  in xillybus_llseek()
1703 	mutex_lock(&channel->endpoint->register_mutex);  in xillybus_llseek()
1706 		  channel->endpoint->registers + fpga_buf_offset_reg);  in xillybus_llseek()
1710 		  channel->endpoint->registers + fpga_buf_ctrl_reg);  in xillybus_llseek()
1712 	mutex_unlock(&channel->endpoint->register_mutex);  in xillybus_llseek()
1743 	poll_wait(filp, &channel->endpoint->ep_wait, wait);  in xillybus_poll()
1786 	if (channel->endpoint->fatal_error)  in xillybus_poll()
1803 static int xillybus_init_chrdev(struct xilly_endpoint *endpoint,  in xillybus_init_chrdev()  argument
1813 				 endpoint->num_channels,  in xillybus_init_chrdev()
1816 		dev_warn(endpoint->dev, "Failed to obtain major/minors");  in xillybus_init_chrdev()
1820 	endpoint->major = major = MAJOR(dev);  in xillybus_init_chrdev()
1821 	endpoint->lowest_minor = minor = MINOR(dev);  in xillybus_init_chrdev()
1823 	cdev_init(&endpoint->cdev, &xillybus_fops);  in xillybus_init_chrdev()
1824 	endpoint->cdev.owner = endpoint->ephw->owner;  in xillybus_init_chrdev()
1825 	rc = cdev_add(&endpoint->cdev, MKDEV(major, minor),  in xillybus_init_chrdev()
1826 		      endpoint->num_channels);  in xillybus_init_chrdev()
1828 		dev_warn(endpoint->dev, "Failed to add cdev. Aborting.\n");  in xillybus_init_chrdev()
1835 	     devnum < endpoint->num_channels;  in xillybus_init_chrdev()
1851 			dev_warn(endpoint->dev,  in xillybus_init_chrdev()
1859 	dev_info(endpoint->dev, "Created %d device files.\n",  in xillybus_init_chrdev()
1860 		 endpoint->num_channels);  in xillybus_init_chrdev()
1868 	cdev_del(&endpoint->cdev);  in xillybus_init_chrdev()
1870 	unregister_chrdev_region(MKDEV(major, minor), endpoint->num_channels);  in xillybus_init_chrdev()
1875 static void xillybus_cleanup_chrdev(struct xilly_endpoint *endpoint)  in xillybus_cleanup_chrdev()  argument
1879 	for (minor = endpoint->lowest_minor;  in xillybus_cleanup_chrdev()
1880 	     minor < (endpoint->lowest_minor + endpoint->num_channels);  in xillybus_cleanup_chrdev()
1882 		device_destroy(xillybus_class, MKDEV(endpoint->major, minor));  in xillybus_cleanup_chrdev()
1883 	cdev_del(&endpoint->cdev);  in xillybus_cleanup_chrdev()
1884 	unregister_chrdev_region(MKDEV(endpoint->major,  in xillybus_cleanup_chrdev()
1885 				       endpoint->lowest_minor),  in xillybus_cleanup_chrdev()
1886 				 endpoint->num_channels);  in xillybus_cleanup_chrdev()
1888 	dev_info(endpoint->dev, "Removed %d device files.\n",  in xillybus_cleanup_chrdev()
1889 		 endpoint->num_channels);  in xillybus_cleanup_chrdev()
1897 	struct xilly_endpoint *endpoint;  in xillybus_init_endpoint()  local
1899 	endpoint = devm_kzalloc(dev, sizeof(*endpoint), GFP_KERNEL);  in xillybus_init_endpoint()
1900 	if (!endpoint)  in xillybus_init_endpoint()
1903 	endpoint->pdev = pdev;  in xillybus_init_endpoint()
1904 	endpoint->dev = dev;  in xillybus_init_endpoint()
1905 	endpoint->ephw = ephw;  in xillybus_init_endpoint()
1906 	endpoint->msg_counter = 0x0b;  in xillybus_init_endpoint()
1907 	endpoint->failed_messages = 0;  in xillybus_init_endpoint()
1908 	endpoint->fatal_error = 0;  in xillybus_init_endpoint()
1910 	init_waitqueue_head(&endpoint->ep_wait);  in xillybus_init_endpoint()
1911 	mutex_init(&endpoint->register_mutex);  in xillybus_init_endpoint()
1913 	return endpoint;  in xillybus_init_endpoint()
1917 static int xilly_quiesce(struct xilly_endpoint *endpoint)  in xilly_quiesce()  argument
1921 	endpoint->idtlen = -1;  in xilly_quiesce()
1923 	iowrite32((u32) (endpoint->dma_using_dac & 0x0001),  in xilly_quiesce()
1924 		  endpoint->registers + fpga_dma_control_reg);  in xilly_quiesce()
1926 	t = wait_event_interruptible_timeout(endpoint->ep_wait,  in xilly_quiesce()
1927 					     (endpoint->idtlen >= 0),  in xilly_quiesce()
1930 		dev_err(endpoint->dev,  in xilly_quiesce()
1937 int xillybus_endpoint_discovery(struct xilly_endpoint *endpoint)  in xillybus_endpoint_discovery()  argument
1944 	struct device *dev = endpoint->dev;  in xillybus_endpoint_discovery()
1963 	iowrite32(1, endpoint->registers + fpga_endian_reg);  in xillybus_endpoint_discovery()
1971 	endpoint->num_channels = 0;  in xillybus_endpoint_discovery()
1973 	rc = xilly_setupchannels(endpoint, bogus_idt, 1);  in xillybus_endpoint_discovery()
1978 	iowrite32(0x04, endpoint->registers + fpga_msg_ctrl_reg);  in xillybus_endpoint_discovery()
1980 	endpoint->idtlen = -1;  in xillybus_endpoint_discovery()
1986 	iowrite32((u32) (endpoint->dma_using_dac & 0x0001),  in xillybus_endpoint_discovery()
1987 		  endpoint->registers + fpga_dma_control_reg);  in xillybus_endpoint_discovery()
1989 	t = wait_event_interruptible_timeout(endpoint->ep_wait,  in xillybus_endpoint_discovery()
1990 					     (endpoint->idtlen >= 0),  in xillybus_endpoint_discovery()
1993 		dev_err(endpoint->dev, "No response from FPGA. Aborting.\n");  in xillybus_endpoint_discovery()
1998 	iowrite32((u32) (0x0002 | (endpoint->dma_using_dac & 0x0001)),  in xillybus_endpoint_discovery()
1999 		  endpoint->registers + fpga_dma_control_reg);  in xillybus_endpoint_discovery()
2002 	while (endpoint->idtlen >= idtbuffersize) {  in xillybus_endpoint_discovery()
2007 	endpoint->num_channels = 1;  in xillybus_endpoint_discovery()
2009 	rc = xilly_setupchannels(endpoint, bogus_idt, 2);  in xillybus_endpoint_discovery()
2013 	rc = xilly_obtain_idt(endpoint);  in xillybus_endpoint_discovery()
2017 	rc = xilly_scan_idt(endpoint, &idt_handle);  in xillybus_endpoint_discovery()
2025 	rc = xilly_setupchannels(endpoint,  in xillybus_endpoint_discovery()
2037 	list_add_tail(&endpoint->ep_list, &list_of_endpoints);  in xillybus_endpoint_discovery()
2040 	rc = xillybus_init_chrdev(endpoint, idt_handle.idt);  in xillybus_endpoint_discovery()
2050 	list_del(&endpoint->ep_list);  in xillybus_endpoint_discovery()
2054 	xilly_quiesce(endpoint);  in xillybus_endpoint_discovery()
2061 void xillybus_endpoint_remove(struct xilly_endpoint *endpoint)  in xillybus_endpoint_remove()  argument
2063 	xillybus_cleanup_chrdev(endpoint);  in xillybus_endpoint_remove()
2066 	list_del(&endpoint->ep_list);  in xillybus_endpoint_remove()
2069 	xilly_quiesce(endpoint);  in xillybus_endpoint_remove()