Lines Matching refs:clks
166 static struct clk **clks; variable
642 clks[TEGRA20_CLK_PLL_C] = clk; in tegra20_pll_init()
651 clks[TEGRA20_CLK_PLL_C_OUT1] = clk; in tegra20_pll_init()
657 clks[TEGRA20_CLK_PLL_M] = clk; in tegra20_pll_init()
666 clks[TEGRA20_CLK_PLL_M_OUT1] = clk; in tegra20_pll_init()
671 clks[TEGRA20_CLK_PLL_X] = clk; in tegra20_pll_init()
676 clks[TEGRA20_CLK_PLL_U] = clk; in tegra20_pll_init()
681 clks[TEGRA20_CLK_PLL_D] = clk; in tegra20_pll_init()
686 clks[TEGRA20_CLK_PLL_D_OUT0] = clk; in tegra20_pll_init()
691 clks[TEGRA20_CLK_PLL_A] = clk; in tegra20_pll_init()
700 clks[TEGRA20_CLK_PLL_A_OUT0] = clk; in tegra20_pll_init()
705 clks[TEGRA20_CLK_PLL_E] = clk; in tegra20_pll_init()
723 clks[TEGRA20_CLK_CCLK] = clk; in tegra20_super_clk_init()
729 clks[TEGRA20_CLK_SCLK] = clk; in tegra20_super_clk_init()
733 clks[TEGRA20_CLK_TWD] = clk; in tegra20_super_clk_init()
752 clks[TEGRA20_CLK_AUDIO] = clk; in tegra20_audio_clk_init()
761 clks[TEGRA20_CLK_AUDIO_2X] = clk; in tegra20_audio_clk_init()
811 clks[TEGRA20_CLK_AC97] = clk; in tegra20_periph_clk_init()
816 clks[TEGRA20_CLK_APBDMA] = clk; in tegra20_periph_clk_init()
826 clks[TEGRA20_CLK_EMC] = clk; in tegra20_periph_clk_init()
830 clks[TEGRA20_CLK_MC] = clk; in tegra20_periph_clk_init()
836 clks[TEGRA20_CLK_DSI] = clk; in tegra20_periph_clk_init()
841 clks[TEGRA20_CLK_PEX] = clk; in tegra20_periph_clk_init()
848 clks[TEGRA20_CLK_CDEV1] = clk; in tegra20_periph_clk_init()
855 clks[TEGRA20_CLK_CDEV2] = clk; in tegra20_periph_clk_init()
862 clks[data->clk_id] = clk; in tegra20_periph_clk_init()
871 clks[data->clk_id] = clk; in tegra20_periph_clk_init()
888 clks[TEGRA20_CLK_CLK_M] = clk; in tegra20_osc_clk_init()
894 clks[TEGRA20_CLK_PLL_REF] = clk; in tegra20_osc_clk_init()
1070 tegra_init_from_table(init_table, clks, TEGRA20_CLK_CLK_MAX); in tegra20_clock_apply_init_table()
1113 clks = tegra_clk_init(clk_base, TEGRA20_CLK_CLK_MAX, in tegra20_clock_init()
1115 if (!clks) in tegra20_clock_init()
1127 tegra_init_dup_clks(tegra_clk_duplicates, clks, TEGRA20_CLK_CLK_MAX); in tegra20_clock_init()