45 static u32 pmbase;  variable
69 	pci_read_config_dword(speedstep_chipset_dev, 0x40, &pmbase);  in speedstep_find_register()
70 	if (!(pmbase & 0x01)) {  in speedstep_find_register()
75 	pmbase &= 0xFFFFFFFE;  in speedstep_find_register()
76 	if (!pmbase) {  in speedstep_find_register()
81 	pr_debug("pmbase is 0x%x\n", pmbase);  in speedstep_find_register()
105 	value = inb(pmbase + 0x50);  in speedstep_set_state()
107 	pr_debug("read at pmbase 0x%x + 0x50 returned 0x%x\n", pmbase, value);  in speedstep_set_state()
113 	pr_debug("writing 0x%x to pmbase 0x%x + 0x50\n", value, pmbase);  in speedstep_set_state()
116 	pm2_blk = inb(pmbase + 0x20);  in speedstep_set_state()
118 	outb(pm2_blk, (pmbase + 0x20));  in speedstep_set_state()
121 	outb(value, (pmbase + 0x50));  in speedstep_set_state()
125 	outb(pm2_blk, (pmbase + 0x20));  in speedstep_set_state()
128 	value = inb(pmbase + 0x50);  in speedstep_set_state()
133 	pr_debug("read at pmbase 0x%x + 0x50 returned 0x%x\n", pmbase, value);  in speedstep_set_state()