Lines Matching refs:tdma
193 struct tegra_dma *tdma; member
236 static inline void tdma_write(struct tegra_dma *tdma, u32 reg, u32 val) in tdma_write() argument
238 writel(val, tdma->base_addr + reg); in tdma_write()
241 static inline u32 tdma_read(struct tegra_dma *tdma, u32 reg) in tdma_read() argument
243 return readl(tdma->base_addr + reg); in tdma_read()
365 struct tegra_dma *tdma = tdc->tdma; in tegra_dma_global_pause() local
367 spin_lock(&tdma->global_lock); in tegra_dma_global_pause()
369 if (tdc->tdma->global_pause_count == 0) { in tegra_dma_global_pause()
370 tdma_write(tdma, TEGRA_APBDMA_GENERAL, 0); in tegra_dma_global_pause()
375 tdc->tdma->global_pause_count++; in tegra_dma_global_pause()
377 spin_unlock(&tdma->global_lock); in tegra_dma_global_pause()
382 struct tegra_dma *tdma = tdc->tdma; in tegra_dma_global_resume() local
384 spin_lock(&tdma->global_lock); in tegra_dma_global_resume()
386 if (WARN_ON(tdc->tdma->global_pause_count == 0)) in tegra_dma_global_resume()
389 if (--tdc->tdma->global_pause_count == 0) in tegra_dma_global_resume()
390 tdma_write(tdma, TEGRA_APBDMA_GENERAL, in tegra_dma_global_resume()
394 spin_unlock(&tdma->global_lock); in tegra_dma_global_resume()
400 struct tegra_dma *tdma = tdc->tdma; in tegra_dma_pause() local
402 if (tdma->chip_data->support_channel_pause) { in tegra_dma_pause()
414 struct tegra_dma *tdma = tdc->tdma; in tegra_dma_resume() local
416 if (tdma->chip_data->support_channel_pause) { in tegra_dma_resume()
456 if (tdc->tdma->chip_data->support_separate_wcount_reg) in tegra_dma_start()
497 if (tdc->tdma->chip_data->support_separate_wcount_reg) in tegra_dma_configure_for_next()
770 if (tdc->tdma->chip_data->support_separate_wcount_reg) in tegra_dma_terminate_all()
931 if (tdc->tdma->chip_data->support_separate_wcount_reg) in tegra_dma_prep_wcount()
999 (len > tdc->tdma->chip_data->max_dma_count)) { in tegra_dma_prep_slave_sg()
1098 (len > tdc->tdma->chip_data->max_dma_count)) { in tegra_dma_prep_dma_cyclic()
1183 struct tegra_dma *tdma = tdc->tdma; in tegra_dma_alloc_chan_resources() local
1188 ret = clk_prepare_enable(tdma->dma_clk); in tegra_dma_alloc_chan_resources()
1197 struct tegra_dma *tdma = tdc->tdma; in tegra_dma_free_chan_resources() local
1233 clk_disable_unprepare(tdma->dma_clk); in tegra_dma_free_chan_resources()
1241 struct tegra_dma *tdma = ofdma->of_dma_data; in tegra_dma_of_xlate() local
1245 chan = dma_get_any_slave_channel(&tdma->dma_dev); in tegra_dma_of_xlate()
1313 struct tegra_dma *tdma; in tegra_dma_probe() local
1326 tdma = devm_kzalloc(&pdev->dev, sizeof(*tdma) + cdata->nr_channels * in tegra_dma_probe()
1328 if (!tdma) { in tegra_dma_probe()
1333 tdma->dev = &pdev->dev; in tegra_dma_probe()
1334 tdma->chip_data = cdata; in tegra_dma_probe()
1335 platform_set_drvdata(pdev, tdma); in tegra_dma_probe()
1338 tdma->base_addr = devm_ioremap_resource(&pdev->dev, res); in tegra_dma_probe()
1339 if (IS_ERR(tdma->base_addr)) in tegra_dma_probe()
1340 return PTR_ERR(tdma->base_addr); in tegra_dma_probe()
1342 tdma->dma_clk = devm_clk_get(&pdev->dev, NULL); in tegra_dma_probe()
1343 if (IS_ERR(tdma->dma_clk)) { in tegra_dma_probe()
1345 return PTR_ERR(tdma->dma_clk); in tegra_dma_probe()
1348 tdma->rst = devm_reset_control_get(&pdev->dev, "dma"); in tegra_dma_probe()
1349 if (IS_ERR(tdma->rst)) { in tegra_dma_probe()
1351 return PTR_ERR(tdma->rst); in tegra_dma_probe()
1354 spin_lock_init(&tdma->global_lock); in tegra_dma_probe()
1367 ret = clk_prepare_enable(tdma->dma_clk); in tegra_dma_probe()
1374 reset_control_assert(tdma->rst); in tegra_dma_probe()
1376 reset_control_deassert(tdma->rst); in tegra_dma_probe()
1379 tdma_write(tdma, TEGRA_APBDMA_GENERAL, TEGRA_APBDMA_GENERAL_ENABLE); in tegra_dma_probe()
1380 tdma_write(tdma, TEGRA_APBDMA_CONTROL, 0); in tegra_dma_probe()
1381 tdma_write(tdma, TEGRA_APBDMA_IRQ_MASK_SET, 0xFFFFFFFFul); in tegra_dma_probe()
1383 clk_disable_unprepare(tdma->dma_clk); in tegra_dma_probe()
1385 INIT_LIST_HEAD(&tdma->dma_dev.channels); in tegra_dma_probe()
1387 struct tegra_dma_channel *tdc = &tdma->channels[i]; in tegra_dma_probe()
1389 tdc->chan_addr = tdma->base_addr + in tegra_dma_probe()
1410 tdc->dma_chan.device = &tdma->dma_dev; in tegra_dma_probe()
1413 &tdma->dma_dev.channels); in tegra_dma_probe()
1414 tdc->tdma = tdma; in tegra_dma_probe()
1427 dma_cap_set(DMA_SLAVE, tdma->dma_dev.cap_mask); in tegra_dma_probe()
1428 dma_cap_set(DMA_PRIVATE, tdma->dma_dev.cap_mask); in tegra_dma_probe()
1429 dma_cap_set(DMA_CYCLIC, tdma->dma_dev.cap_mask); in tegra_dma_probe()
1431 tdma->global_pause_count = 0; in tegra_dma_probe()
1432 tdma->dma_dev.dev = &pdev->dev; in tegra_dma_probe()
1433 tdma->dma_dev.device_alloc_chan_resources = in tegra_dma_probe()
1435 tdma->dma_dev.device_free_chan_resources = in tegra_dma_probe()
1437 tdma->dma_dev.device_prep_slave_sg = tegra_dma_prep_slave_sg; in tegra_dma_probe()
1438 tdma->dma_dev.device_prep_dma_cyclic = tegra_dma_prep_dma_cyclic; in tegra_dma_probe()
1439 tdma->dma_dev.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | in tegra_dma_probe()
1443 tdma->dma_dev.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | in tegra_dma_probe()
1447 tdma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); in tegra_dma_probe()
1453 tdma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT; in tegra_dma_probe()
1454 tdma->dma_dev.device_config = tegra_dma_slave_config; in tegra_dma_probe()
1455 tdma->dma_dev.device_terminate_all = tegra_dma_terminate_all; in tegra_dma_probe()
1456 tdma->dma_dev.device_tx_status = tegra_dma_tx_status; in tegra_dma_probe()
1457 tdma->dma_dev.device_issue_pending = tegra_dma_issue_pending; in tegra_dma_probe()
1459 ret = dma_async_device_register(&tdma->dma_dev); in tegra_dma_probe()
1467 tegra_dma_of_xlate, tdma); in tegra_dma_probe()
1479 dma_async_device_unregister(&tdma->dma_dev); in tegra_dma_probe()
1482 struct tegra_dma_channel *tdc = &tdma->channels[i]; in tegra_dma_probe()
1495 struct tegra_dma *tdma = platform_get_drvdata(pdev); in tegra_dma_remove() local
1499 dma_async_device_unregister(&tdma->dma_dev); in tegra_dma_remove()
1501 for (i = 0; i < tdma->chip_data->nr_channels; ++i) { in tegra_dma_remove()
1502 tdc = &tdma->channels[i]; in tegra_dma_remove()
1516 struct tegra_dma *tdma = platform_get_drvdata(pdev); in tegra_dma_runtime_suspend() local
1518 clk_disable_unprepare(tdma->dma_clk); in tegra_dma_runtime_suspend()
1525 struct tegra_dma *tdma = platform_get_drvdata(pdev); in tegra_dma_runtime_resume() local
1528 ret = clk_prepare_enable(tdma->dma_clk); in tegra_dma_runtime_resume()
1539 struct tegra_dma *tdma = dev_get_drvdata(dev); in tegra_dma_pm_suspend() local
1548 tdma->reg_gen = tdma_read(tdma, TEGRA_APBDMA_GENERAL); in tegra_dma_pm_suspend()
1549 for (i = 0; i < tdma->chip_data->nr_channels; i++) { in tegra_dma_pm_suspend()
1550 struct tegra_dma_channel *tdc = &tdma->channels[i]; in tegra_dma_pm_suspend()
1567 struct tegra_dma *tdma = dev_get_drvdata(dev); in tegra_dma_pm_resume() local
1576 tdma_write(tdma, TEGRA_APBDMA_GENERAL, tdma->reg_gen); in tegra_dma_pm_resume()
1577 tdma_write(tdma, TEGRA_APBDMA_CONTROL, 0); in tegra_dma_pm_resume()
1578 tdma_write(tdma, TEGRA_APBDMA_IRQ_MASK_SET, 0xFFFFFFFFul); in tegra_dma_pm_resume()
1580 for (i = 0; i < tdma->chip_data->nr_channels; i++) { in tegra_dma_pm_resume()
1581 struct tegra_dma_channel *tdc = &tdma->channels[i]; in tegra_dma_pm_resume()