Lines Matching refs:dpm
313 struct ci_power_info *pi = adev->pm.dpm.priv; in ci_get_pi()
398 if (adev->pm.dpm.dyn_state.cac_leakage_table.entries == NULL) in ci_populate_bapm_vddc_vid_sidd()
400 if (adev->pm.dpm.dyn_state.cac_leakage_table.count > 8) in ci_populate_bapm_vddc_vid_sidd()
402 if (adev->pm.dpm.dyn_state.cac_leakage_table.count != in ci_populate_bapm_vddc_vid_sidd()
403 adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count) in ci_populate_bapm_vddc_vid_sidd()
406 for (i = 0; i < adev->pm.dpm.dyn_state.cac_leakage_table.count; i++) { in ci_populate_bapm_vddc_vid_sidd()
407 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) { in ci_populate_bapm_vddc_vid_sidd()
408 lo_vid[i] = ci_convert_to_vid(adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1); in ci_populate_bapm_vddc_vid_sidd()
409 hi_vid[i] = ci_convert_to_vid(adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2); in ci_populate_bapm_vddc_vid_sidd()
410 hi2_vid[i] = ci_convert_to_vid(adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3); in ci_populate_bapm_vddc_vid_sidd()
412 lo_vid[i] = ci_convert_to_vid(adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc); in ci_populate_bapm_vddc_vid_sidd()
413 hi_vid[i] = ci_convert_to_vid((u16)adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage); in ci_populate_bapm_vddc_vid_sidd()
453 tdc_limit = adev->pm.dpm.dyn_state.cac_tdp_table->tdc * 256; in ci_populate_tdc_limit()
486 if ((adev->pm.dpm.fan.fan_output_sensitivity & (1 << 15)) || in ci_populate_fuzzy_fan()
487 (adev->pm.dpm.fan.fan_output_sensitivity == 0)) in ci_populate_fuzzy_fan()
488 adev->pm.dpm.fan.fan_output_sensitivity = in ci_populate_fuzzy_fan()
489 adev->pm.dpm.fan.default_fan_output_sensitivity; in ci_populate_fuzzy_fan()
492 cpu_to_be16(adev->pm.dpm.fan.fan_output_sensitivity); in ci_populate_fuzzy_fan()
535 adev->pm.dpm.dyn_state.cac_tdp_table; in ci_populate_bapm_vddc_base_leakage_sidd()
552 adev->pm.dpm.dyn_state.cac_tdp_table; in ci_populate_bapm_parameters_in_dpm_table()
553 struct amdgpu_ppm_table *ppm = adev->pm.dpm.dyn_state.ppm_table; in ci_populate_bapm_parameters_in_dpm_table()
787 adev->pm.dpm.dyn_state.cac_tdp_table; in ci_enable_power_containment()
861 adev->pm.dpm.dyn_state.cac_tdp_table; in ci_power_control_set_level()
869 adev->pm.dpm.tdp_adjustment : (-1 * adev->pm.dpm.tdp_adjustment); in ci_power_control_set_level()
920 rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk; in ci_apply_state_adjust_rules()
921 rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk; in ci_apply_state_adjust_rules()
927 if ((adev->pm.dpm.new_active_crtc_count > 1) || in ci_apply_state_adjust_rules()
938 if (adev->pm.dpm.ac_power) in ci_apply_state_adjust_rules()
939 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in ci_apply_state_adjust_rules()
941 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc; in ci_apply_state_adjust_rules()
943 if (adev->pm.dpm.ac_power == false) { in ci_apply_state_adjust_rules()
963 if (sclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk) in ci_apply_state_adjust_rules()
964 sclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk; in ci_apply_state_adjust_rules()
965 if (mclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk) in ci_apply_state_adjust_rules()
966 mclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk; in ci_apply_state_adjust_rules()
1014 adev->pm.dpm.thermal.min_temp = low_temp; in ci_thermal_set_temperature_range()
1015 adev->pm.dpm.thermal.max_temp = high_temp; in ci_thermal_set_temperature_range()
1084 adev->pm.dpm.fan.ucode_fan_control = false; in ci_thermal_setup_fan_table()
1092 adev->pm.dpm.fan.ucode_fan_control = false; in ci_thermal_setup_fan_table()
1096 tmp64 = (u64)adev->pm.dpm.fan.pwm_min * duty100; in ci_thermal_setup_fan_table()
1100 t_diff1 = adev->pm.dpm.fan.t_med - adev->pm.dpm.fan.t_min; in ci_thermal_setup_fan_table()
1101 t_diff2 = adev->pm.dpm.fan.t_high - adev->pm.dpm.fan.t_med; in ci_thermal_setup_fan_table()
1103 pwm_diff1 = adev->pm.dpm.fan.pwm_med - adev->pm.dpm.fan.pwm_min; in ci_thermal_setup_fan_table()
1104 pwm_diff2 = adev->pm.dpm.fan.pwm_high - adev->pm.dpm.fan.pwm_med; in ci_thermal_setup_fan_table()
1109 fan_table.TempMin = cpu_to_be16((50 + adev->pm.dpm.fan.t_min) / 100); in ci_thermal_setup_fan_table()
1110 fan_table.TempMed = cpu_to_be16((50 + adev->pm.dpm.fan.t_med) / 100); in ci_thermal_setup_fan_table()
1111 fan_table.TempMax = cpu_to_be16((50 + adev->pm.dpm.fan.t_max) / 100); in ci_thermal_setup_fan_table()
1118 fan_table.HystDown = cpu_to_be16(adev->pm.dpm.fan.t_hyst); in ci_thermal_setup_fan_table()
1128 fan_table.RefreshPeriod = cpu_to_be32((adev->pm.dpm.fan.cycle_delay * in ci_thermal_setup_fan_table()
1145 adev->pm.dpm.fan.ucode_fan_control = false; in ci_thermal_setup_fan_table()
1164 adev->pm.dpm.fan.default_max_fan_pwm); in ci_fan_ctrl_start_smc_fan_control()
1259 if (adev->pm.dpm.fan.ucode_fan_control) in ci_dpm_set_fan_control_mode()
1264 if (adev->pm.dpm.fan.ucode_fan_control) in ci_dpm_set_fan_control_mode()
1322 if (adev->pm.dpm.fan.ucode_fan_control)
1355 if (adev->pm.dpm.fan.ucode_fan_control) { in ci_thermal_start_smc_fan_control()
1388 if (adev->pm.dpm.fan.ucode_fan_control) { in ci_thermal_start_thermal_controller()
1472 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) { in ci_get_leakage_voltages()
1574 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) in ci_enable_vr_hot_gpio_interrupt()
1761 adev->pm.dpm.dyn_state.cac_tdp_table;
2099 if (adev->pm.dpm.new_active_crtc_count > 0) in ci_program_display_gap()
2119 ci_notify_smc_display_change(adev, (adev->pm.dpm.new_active_crtc_count == 1)); in ci_program_display_gap()
2254 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in ci_construct_voltage_tables()
2272 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk, in ci_construct_voltage_tables()
2290 &adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk, in ci_construct_voltage_tables()
2421 for (i = 0; i < adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count; i++) { in ci_populate_mvdd_value()
2422 if (mclk <= adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries[i].clk) { in ci_populate_mvdd_value()
2428 if (i >= adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count) in ci_populate_mvdd_value()
2444 if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) in ci_get_std_voltage_value_sidd()
2447 if (adev->pm.dpm.dyn_state.cac_leakage_table.entries) { in ci_get_std_voltage_value_sidd()
2448 …for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { in ci_get_std_voltage_value_sidd()
2450 adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { in ci_get_std_voltage_value_sidd()
2452 if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count) in ci_get_std_voltage_value_sidd()
2455 idx = adev->pm.dpm.dyn_state.cac_leakage_table.count - 1; in ci_get_std_voltage_value_sidd()
2457 adev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE; in ci_get_std_voltage_value_sidd()
2459 adev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE; in ci_get_std_voltage_value_sidd()
2465 …for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { in ci_get_std_voltage_value_sidd()
2467 adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { in ci_get_std_voltage_value_sidd()
2469 if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count) in ci_get_std_voltage_value_sidd()
2472 idx = adev->pm.dpm.dyn_state.cac_leakage_table.count - 1; in ci_get_std_voltage_value_sidd()
2474 adev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE; in ci_get_std_voltage_value_sidd()
2476 adev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE; in ci_get_std_voltage_value_sidd()
2699 for (level = 0; level < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; level++) { in ci_populate_smc_initial_state()
2700 if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[level].clk >= in ci_populate_smc_initial_state()
2707 for (level = 0; level < adev->pm.dpm.dyn_state.vddc_dependency_on_mclk.count; level++) { in ci_populate_smc_initial_state()
2708 if (adev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries[level].clk >= in ci_populate_smc_initial_state()
2762 adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count; in ci_populate_smc_uvd_level()
2766 adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].vclk; in ci_populate_smc_uvd_level()
2768 adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].dclk; in ci_populate_smc_uvd_level()
2770 adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE; in ci_populate_smc_uvd_level()
2805 adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count; in ci_populate_smc_vce_level()
2809 adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].evclk; in ci_populate_smc_vce_level()
2811 (u16)adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE; in ci_populate_smc_vce_level()
2838 (adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count); in ci_populate_smc_acp_level()
2842 adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].clk; in ci_populate_smc_acp_level()
2844 adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].v; in ci_populate_smc_acp_level()
2870 adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count; in ci_populate_smc_samu_level()
2874 adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].clk; in ci_populate_smc_samu_level()
2876 adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE; in ci_populate_smc_samu_level()
2994 if (adev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries) { in ci_populate_single_memory_level()
2996 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in ci_populate_single_memory_level()
3002 if (adev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries) { in ci_populate_single_memory_level()
3004 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk, in ci_populate_single_memory_level()
3010 if (adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries) { in ci_populate_single_memory_level()
3012 &adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk, in ci_populate_single_memory_level()
3022 &adev->pm.dpm.dyn_state.phase_shedding_limits_table, in ci_populate_single_memory_level()
3045 (adev->pm.dpm.new_active_crtc_count <= 2)) in ci_populate_single_memory_level()
3240 u16 ulv_voltage = adev->pm.dpm.backbias_response_time; in ci_populate_ulv_level()
3251 if (ulv_voltage > adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v) in ci_populate_ulv_level()
3255 adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage; in ci_populate_ulv_level()
3257 if (ulv_voltage > adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v) in ci_populate_ulv_level()
3261 ((adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage) * in ci_populate_ulv_level()
3342 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in ci_populate_single_graphic_level()
3354 &adev->pm.dpm.dyn_state.phase_shedding_limits_table, in ci_populate_single_graphic_level()
3557 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in ci_setup_default_dpm_tables()
3559 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk; in ci_setup_default_dpm_tables()
3561 &adev->pm.dpm.dyn_state.cac_leakage_table; in ci_setup_default_dpm_tables()
3626 allowed_mclk_table = &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk; in ci_setup_default_dpm_tables()
3636 allowed_mclk_table = &adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk; in ci_setup_default_dpm_tables()
3671 struct amdgpu_ps *amdgpu_boot_state = adev->pm.dpm.boot_ps; in ci_init_smc_table()
3684 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) in ci_init_smc_table()
3687 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) in ci_init_smc_table()
3898 &adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk; in ci_apply_disp_minimum_voltage_request()
3900 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in ci_apply_disp_minimum_voltage_request()
4003 if (adev->pm.dpm.current_active_crtc_count != in ci_find_dpm_states_clocks_in_dpm_table()
4004 adev->pm.dpm.new_active_crtc_count) in ci_find_dpm_states_clocks_in_dpm_table()
4048 if (adev->pm.dpm.ac_power) in ci_enable_uvd_dpm()
4049 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in ci_enable_uvd_dpm()
4051 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc; in ci_enable_uvd_dpm()
4056 for (i = adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1; i >= 0; i--) { in ci_enable_uvd_dpm()
4057 if (adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) { in ci_enable_uvd_dpm()
4097 if (adev->pm.dpm.ac_power) in ci_enable_vce_dpm()
4098 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in ci_enable_vce_dpm()
4100 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc; in ci_enable_vce_dpm()
4104 for (i = adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count - 1; i >= 0; i--) { in ci_enable_vce_dpm()
4105 if (adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) { in ci_enable_vce_dpm()
4130 if (adev->pm.dpm.ac_power)
4131 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
4133 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
4137 for (i = adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
4138 … if (adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
4161 if (adev->pm.dpm.ac_power)
4162 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
4164 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
4168 for (i = adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
4169 if (adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
4195 (adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count <= 0)) in ci_update_uvd_dpm()
4199 adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1; in ci_update_uvd_dpm()
4215 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in ci_get_vce_boot_level()
4474 adev->pm.dpm.forced_level = level; in ci_dpm_force_performance_level()
5060 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in ci_set_private_data_variables_based_on_pptable()
5062 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk; in ci_set_private_data_variables_based_on_pptable()
5064 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk; in ci_set_private_data_variables_based_on_pptable()
5087 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = in ci_set_private_data_variables_based_on_pptable()
5089 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = in ci_set_private_data_variables_based_on_pptable()
5091 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = in ci_set_private_data_variables_based_on_pptable()
5093 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = in ci_set_private_data_variables_based_on_pptable()
5206 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk); in ci_patch_dependency_tables_with_leakage()
5208 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk); in ci_patch_dependency_tables_with_leakage()
5210 &adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk); in ci_patch_dependency_tables_with_leakage()
5212 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk); in ci_patch_dependency_tables_with_leakage()
5214 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table); in ci_patch_dependency_tables_with_leakage()
5216 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table); in ci_patch_dependency_tables_with_leakage()
5218 &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table); in ci_patch_dependency_tables_with_leakage()
5220 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table); in ci_patch_dependency_tables_with_leakage()
5222 &adev->pm.dpm.dyn_state.phase_shedding_limits_table); in ci_patch_dependency_tables_with_leakage()
5224 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac); in ci_patch_dependency_tables_with_leakage()
5226 &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc); in ci_patch_dependency_tables_with_leakage()
5228 &adev->pm.dpm.dyn_state.cac_leakage_table); in ci_patch_dependency_tables_with_leakage()
5257 struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps; in ci_dpm_pre_set_power_state()
5286 struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps; in ci_dpm_enable()
5416 amdgpu_irq_get(adev, &adev->pm.dpm.thermal.irq, in ci_dpm_enable()
5418 amdgpu_irq_get(adev, &adev->pm.dpm.thermal.irq, in ci_dpm_enable()
5435 struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps; in ci_dpm_disable()
5437 amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq, in ci_dpm_disable()
5439 amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq, in ci_dpm_disable()
5586 adev->pm.dpm.boot_ps = rps; in ci_parse_pplib_non_clock_info()
5588 adev->pm.dpm.uvd_ps = rps; in ci_parse_pplib_non_clock_info()
5694 adev->pm.dpm.ps = kzalloc(sizeof(struct amdgpu_ps) * in ci_parse_power_table()
5696 if (!adev->pm.dpm.ps) in ci_parse_power_table()
5707 kfree(adev->pm.dpm.ps); in ci_parse_power_table()
5710 adev->pm.dpm.ps[i].ps_priv = ps; in ci_parse_power_table()
5711 ci_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i], in ci_parse_power_table()
5726 &adev->pm.dpm.ps[i], k, in ci_parse_power_table()
5732 adev->pm.dpm.num_ps = state_array->ucNumEntries; in ci_parse_power_table()
5737 clock_array_index = adev->pm.dpm.vce_states[i].clk_idx; in ci_parse_power_table()
5744 adev->pm.dpm.vce_states[i].sclk = sclk; in ci_parse_power_table()
5745 adev->pm.dpm.vce_states[i].mclk = mclk; in ci_parse_power_table()
5782 for (i = 0; i < adev->pm.dpm.num_ps; i++) { in ci_dpm_fini()
5783 kfree(adev->pm.dpm.ps[i].ps_priv); in ci_dpm_fini()
5785 kfree(adev->pm.dpm.ps); in ci_dpm_fini()
5786 kfree(adev->pm.dpm.priv); in ci_dpm_fini()
5787 kfree(adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries); in ci_dpm_fini()
5851 adev->pm.dpm.priv = pi; in ci_dpm_init()
5933 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries = in ci_dpm_init()
5935 if (!adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) { in ci_dpm_init()
5939 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4; in ci_dpm_init()
5940 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; in ci_dpm_init()
5941 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; in ci_dpm_init()
5942 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000; in ci_dpm_init()
5943 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720; in ci_dpm_init()
5944 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000; in ci_dpm_init()
5945 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810; in ci_dpm_init()
5946 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000; in ci_dpm_init()
5947 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900; in ci_dpm_init()
5949 adev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; in ci_dpm_init()
5950 adev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; in ci_dpm_init()
5951 adev->pm.dpm.dyn_state.vddc_vddci_delta = 200; in ci_dpm_init()
5953 adev->pm.dpm.dyn_state.valid_sclk_values.count = 0; in ci_dpm_init()
5954 adev->pm.dpm.dyn_state.valid_sclk_values.values = NULL; in ci_dpm_init()
5955 adev->pm.dpm.dyn_state.valid_mclk_values.count = 0; in ci_dpm_init()
5956 adev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; in ci_dpm_init()
5975 adev->pm.dpm.platform_caps |= ATOM_PP_PLATFORM_CAP_REGULATOR_HOT; in ci_dpm_init()
5978 adev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_REGULATOR_HOT; in ci_dpm_init()
5984 adev->pm.dpm.platform_caps |= ATOM_PP_PLATFORM_CAP_HARDWAREDC; in ci_dpm_init()
5987 adev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_HARDWAREDC; in ci_dpm_init()
6027 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL) { in ci_dpm_init()
6033 adev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL; in ci_dpm_init()
6036 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_MVDDCONTROL) { in ci_dpm_init()
6042 adev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_MVDDCONTROL; in ci_dpm_init()
6075 if ((adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || in ci_dpm_init()
6076 (adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) in ci_dpm_init()
6077 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc = in ci_dpm_init()
6078 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in ci_dpm_init()
6213 ret = amdgpu_irq_add_id(adev, 230, &adev->pm.dpm.thermal.irq); in ci_dpm_sw_init()
6217 ret = amdgpu_irq_add_id(adev, 231, &adev->pm.dpm.thermal.irq); in ci_dpm_sw_init()
6222 adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED; in ci_dpm_sw_init()
6223 adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED; in ci_dpm_sw_init()
6224 adev->pm.dpm.forced_level = AMDGPU_DPM_FORCED_LEVEL_AUTO; in ci_dpm_sw_init()
6238 INIT_WORK(&adev->pm.dpm.thermal.work, amdgpu_dpm_thermal_work_handler); in ci_dpm_sw_init()
6243 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps; in ci_dpm_sw_init()
6313 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps; in ci_dpm_suspend()
6626 adev->pm.dpm.thermal.high_to_low = false; in ci_dpm_process_interrupt()
6631 adev->pm.dpm.thermal.high_to_low = true; in ci_dpm_process_interrupt()
6639 schedule_work(&adev->pm.dpm.thermal.work); in ci_dpm_process_interrupt()
6705 adev->pm.dpm.thermal.irq.num_types = AMDGPU_THERMAL_IRQ_LAST; in ci_dpm_set_irq_funcs()
6706 adev->pm.dpm.thermal.irq.funcs = &ci_dpm_irq_funcs; in ci_dpm_set_irq_funcs()