916 	u32 sclk, mclk;  in ci_apply_state_adjust_rules()  local
945 			if (ps->performance_levels[i].mclk > max_limits->mclk)  in ci_apply_state_adjust_rules()
946 				ps->performance_levels[i].mclk = max_limits->mclk;  in ci_apply_state_adjust_rules()
955 		mclk  = ps->performance_levels[ps->performance_level_count - 1].mclk;  in ci_apply_state_adjust_rules()
958 		mclk = ps->performance_levels[0].mclk;  in ci_apply_state_adjust_rules()
965 		if (mclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk)  in ci_apply_state_adjust_rules()
966 			mclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk;  in ci_apply_state_adjust_rules()
970 	ps->performance_levels[0].mclk = mclk;  in ci_apply_state_adjust_rules()
976 		if (ps->performance_levels[0].mclk < ps->performance_levels[1].mclk)  in ci_apply_state_adjust_rules()
977 			ps->performance_levels[0].mclk = ps->performance_levels[1].mclk;  in ci_apply_state_adjust_rules()
979 		if (ps->performance_levels[1].mclk < ps->performance_levels[0].mclk)  in ci_apply_state_adjust_rules()
980 			ps->performance_levels[1].mclk = ps->performance_levels[0].mclk;  in ci_apply_state_adjust_rules()
2414 static int ci_populate_mvdd_value(struct amdgpu_device *adev, u32 mclk,  in ci_populate_mvdd_value()  argument
2422 			if (mclk <= adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries[i].clk) {  in ci_populate_mvdd_value()
2505 						  u32 mclk,  in ci_populate_phase_value_based_on_mclk()  argument
2513 		if (mclk < limits->entries[i].mclk) {  in ci_populate_phase_value_based_on_mclk()
2630 						u32 mclk,  in ci_populate_memory_timing_parameters()  argument
2637 	amdgpu_atombios_set_engine_dram_timings(adev, sclk, mclk);  in ci_populate_memory_timing_parameters()
2643 	ci_register_patching_mc_arb(adev, sclk, mclk, &dram_timing2);  in ci_populate_memory_timing_parameters()
2709 		    boot_state->performance_levels[0].mclk) {  in ci_populate_smc_initial_state()
2896 				    SMU7_Discrete_MemoryLevel *mclk,  in ci_calculate_mclk_params()  argument
2972 	mclk->MclkFrequency = memory_clock;  in ci_calculate_mclk_params()
2973 	mclk->MpllFuncCntl = mpll_func_cntl;  in ci_calculate_mclk_params()
2974 	mclk->MpllFuncCntl_1 = mpll_func_cntl_1;  in ci_calculate_mclk_params()
2975 	mclk->MpllFuncCntl_2 = mpll_func_cntl_2;  in ci_calculate_mclk_params()
2976 	mclk->MpllAdFuncCntl = mpll_ad_func_cntl;  in ci_calculate_mclk_params()
2977 	mclk->MpllDqFuncCntl = mpll_dq_func_cntl;  in ci_calculate_mclk_params()
2978 	mclk->MclkPwrmgtCntl = mclk_pwrmgt_cntl;  in ci_calculate_mclk_params()
2979 	mclk->DllCntl = dll_cntl;  in ci_calculate_mclk_params()
2980 	mclk->MpllSs1 = mpll_ss1;  in ci_calculate_mclk_params()
2981 	mclk->MpllSs2 = mpll_ss2;  in ci_calculate_mclk_params()
3883 				  state->performance_levels[0].mclk,  in ci_trim_dpm_states()
3884 				  state->performance_levels[high_limit_count].mclk);  in ci_trim_dpm_states()
3977 	u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;  in ci_find_dpm_states_clocks_in_dpm_table()  local
3996 		if (mclk == mclk_table->dpm_levels[i].value)  in ci_find_dpm_states_clocks_in_dpm_table()
4014 	u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;  in ci_populate_and_upload_sclk_mclk_dpm_levels()  local
4025 		dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value = mclk;  in ci_populate_and_upload_sclk_mclk_dpm_levels()
5089 	adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk =  in ci_set_private_data_variables_based_on_pptable()
5603 	pl->mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);  in ci_parse_pplib_clock_info()
5604 	pl->mclk |= clock_info->ci.ucMemoryClockHigh << 16;  in ci_parse_pplib_clock_info()
5626 		pl->mclk = pi->vbios_boot_state.mclk_bootup_value;  in ci_parse_pplib_clock_info()
5736 		u32 sclk, mclk;  in ci_parse_power_table()  local
5742 		mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);  in ci_parse_power_table()
5743 		mclk |= clock_info->ci.ucMemoryClockHigh << 16;  in ci_parse_power_table()
5745 		adev->pm.dpm.vce_states[i].mclk = mclk;  in ci_parse_power_table()
6076 	    (adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))  in ci_dpm_init()
6092 	u32 mclk = ci_get_average_mclk_freq(adev);  in ci_dpm_debugfs_print_current_performance_level()  local
6097 		   sclk, mclk);  in ci_dpm_debugfs_print_current_performance_level()
6113 		       i, pl->sclk, pl->mclk, pl->pcie_gen + 1, pl->pcie_lane);  in ci_dpm_print_power_state()
6135 		return requested_state->performance_levels[0].mclk;  in ci_dpm_get_mclk()
6137 		return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk;  in ci_dpm_get_mclk()