Lines Matching refs:pi
57 struct cz_power_info *pi = adev->pm.dpm.priv; in cz_get_pi() local
59 return pi; in cz_get_pi()
73 struct cz_power_info *pi = cz_get_pi(adev); in cz_construct_max_power_limits_table() local
83 table->mclk = pi->sys_info.nbp_memory_clock[0]; in cz_construct_max_power_limits_table()
96 struct cz_power_info *pi = cz_get_pi(adev); in cz_parse_sys_info_table() local
113 pi->sys_info.bootup_sclk = in cz_parse_sys_info_table()
115 pi->sys_info.bootup_uma_clk = in cz_parse_sys_info_table()
117 pi->sys_info.dentist_vco_freq = in cz_parse_sys_info_table()
119 pi->sys_info.bootup_nb_voltage_index = in cz_parse_sys_info_table()
123 pi->sys_info.htc_tmp_lmt = 203; in cz_parse_sys_info_table()
125 pi->sys_info.htc_tmp_lmt = igp_info->info_9.ucHtcTmpLmt; in cz_parse_sys_info_table()
128 pi->sys_info.htc_hyst_lmt = 5; in cz_parse_sys_info_table()
130 pi->sys_info.htc_hyst_lmt = igp_info->info_9.ucHtcHystLmt; in cz_parse_sys_info_table()
132 if (pi->sys_info.htc_tmp_lmt <= pi->sys_info.htc_hyst_lmt) { in cz_parse_sys_info_table()
138 pi->enable_nb_ps_policy) in cz_parse_sys_info_table()
139 pi->sys_info.nb_dpm_enable = true; in cz_parse_sys_info_table()
141 pi->sys_info.nb_dpm_enable = false; in cz_parse_sys_info_table()
145 pi->sys_info.nbp_memory_clock[i] = in cz_parse_sys_info_table()
147 pi->sys_info.nbp_n_clock[i] = in cz_parse_sys_info_table()
152 pi->sys_info.display_clock[i] = in cz_parse_sys_info_table()
156 pi->sys_info.nbp_voltage_index[i] = in cz_parse_sys_info_table()
161 pi->caps_enable_dfs_bypass = true; in cz_parse_sys_info_table()
163 pi->sys_info.uma_channel_number = in cz_parse_sys_info_table()
208 struct cz_power_info *pi = cz_get_pi(adev); in cz_construct_boot_state() local
210 pi->boot_pl.sclk = pi->sys_info.bootup_sclk; in cz_construct_boot_state()
211 pi->boot_pl.vddc_index = pi->sys_info.bootup_nb_voltage_index; in cz_construct_boot_state()
212 pi->boot_pl.ds_divider_index = 0; in cz_construct_boot_state()
213 pi->boot_pl.ss_divider_index = 0; in cz_construct_boot_state()
214 pi->boot_pl.allow_gnb_slow = 1; in cz_construct_boot_state()
215 pi->boot_pl.force_nbp_state = 0; in cz_construct_boot_state()
216 pi->boot_pl.display_wm = 0; in cz_construct_boot_state()
217 pi->boot_pl.vce_wm = 0; in cz_construct_boot_state()
224 struct cz_power_info *pi = cz_get_pi(adev); in cz_patch_boot_state() local
227 ps->levels[0] = pi->boot_pl; in cz_patch_boot_state()
240 struct cz_power_info *pi = cz_get_pi(adev); in cz_parse_pplib_clock_info() local
251 if (pi->caps_sclk_ds) { in cz_parse_pplib_clock_info()
384 struct cz_power_info *pi = cz_get_pi(adev); in cz_process_firmware_header() local
391 &tmp, pi->sram_end); in cz_process_firmware_header()
394 pi->dpm_table_start = tmp; in cz_process_firmware_header()
401 struct cz_power_info *pi; in cz_dpm_init() local
404 pi = kzalloc(sizeof(struct cz_power_info), GFP_KERNEL); in cz_dpm_init()
405 if (NULL == pi) in cz_dpm_init()
408 adev->pm.dpm.priv = pi; in cz_dpm_init()
418 pi->sram_end = SMC_RAM_END; in cz_dpm_init()
422 pi->active_target[i] = CZ_AT_DFLT; in cz_dpm_init()
424 pi->mgcg_cgtt_local0 = 0x0; in cz_dpm_init()
425 pi->mgcg_cgtt_local1 = 0x0; in cz_dpm_init()
426 pi->clock_slow_down_step = 25000; in cz_dpm_init()
427 pi->skip_clock_slow_down = 1; in cz_dpm_init()
428 pi->enable_nb_ps_policy = 0; in cz_dpm_init()
429 pi->caps_power_containment = true; in cz_dpm_init()
430 pi->caps_cac = true; in cz_dpm_init()
431 pi->didt_enabled = false; in cz_dpm_init()
432 if (pi->didt_enabled) { in cz_dpm_init()
433 pi->caps_sq_ramping = true; in cz_dpm_init()
434 pi->caps_db_ramping = true; in cz_dpm_init()
435 pi->caps_td_ramping = true; in cz_dpm_init()
436 pi->caps_tcp_ramping = true; in cz_dpm_init()
438 pi->caps_sclk_ds = true; in cz_dpm_init()
439 pi->voting_clients = 0x00c00033; in cz_dpm_init()
440 pi->auto_thermal_throttling_enabled = true; in cz_dpm_init()
441 pi->bapm_enabled = false; in cz_dpm_init()
442 pi->disable_nb_ps3_in_battery = false; in cz_dpm_init()
443 pi->voltage_drop_threshold = 0; in cz_dpm_init()
444 pi->caps_sclk_throttle_low_notification = false; in cz_dpm_init()
445 pi->gfx_pg_threshold = 500; in cz_dpm_init()
446 pi->caps_fps = true; in cz_dpm_init()
448 pi->caps_uvd_pg = (adev->pg_flags & AMDGPU_PG_SUPPORT_UVD) ? true : false; in cz_dpm_init()
449 pi->caps_uvd_dpm = true; in cz_dpm_init()
451 pi->caps_vce_pg = (adev->pg_flags & AMDGPU_PG_SUPPORT_VCE) ? true : false; in cz_dpm_init()
452 pi->caps_vce_dpm = true; in cz_dpm_init()
454 pi->caps_acp_pg = (adev->pg_flags & AMDGPU_PG_SUPPORT_ACP) ? true : false; in cz_dpm_init()
455 pi->caps_acp_dpm = true; in cz_dpm_init()
457 pi->caps_stable_power_state = false; in cz_dpm_init()
458 pi->nb_dpm_enabled_by_driver = true; in cz_dpm_init()
459 pi->nb_dpm_enabled = false; in cz_dpm_init()
460 pi->caps_voltage_island = false; in cz_dpm_init()
462 pi->need_pptable_upload = true; in cz_dpm_init()
479 pi->dpm_enabled = true; in cz_dpm_init()
480 pi->uvd_dynamic_pg = false; in cz_dpm_init()
508 struct cz_power_info *pi = cz_get_pi(adev); in cz_dpm_debugfs_print_current_performance_level() local
539 seq_printf(m, "uvd %sabled\n", pi->uvd_power_gated ? "dis" : "en"); in cz_dpm_debugfs_print_current_performance_level()
540 if (!pi->uvd_power_gated) { in cz_dpm_debugfs_print_current_performance_level()
550 seq_printf(m, "vce %sabled\n", pi->vce_power_gated ? "dis" : "en"); in cz_dpm_debugfs_print_current_performance_level()
551 if (!pi->vce_power_gated) { in cz_dpm_debugfs_print_current_performance_level()
668 struct cz_power_info *pi = cz_get_pi(adev); in cz_reset_ap_mask() local
670 pi->active_process_mask = 0; in cz_reset_ap_mask()
686 struct cz_power_info *pi = cz_get_pi(adev); in cz_dpm_upload_pptable_to_smu() local
704 if (!pi->need_pptable_upload) in cz_dpm_upload_pptable_to_smu()
807 struct cz_power_info *pi = cz_get_pi(adev); in cz_init_sclk_limit() local
817 pi->sclk_dpm.soft_min_clk = 0; in cz_init_sclk_limit()
818 pi->sclk_dpm.hard_min_clk = 0; in cz_init_sclk_limit()
828 pi->sclk_dpm.soft_max_clk = clock; in cz_init_sclk_limit()
829 pi->sclk_dpm.hard_max_clk = clock; in cz_init_sclk_limit()
835 struct cz_power_info *pi = cz_get_pi(adev); in cz_init_uvd_limit() local
845 pi->uvd_dpm.soft_min_clk = 0; in cz_init_uvd_limit()
846 pi->uvd_dpm.hard_min_clk = 0; in cz_init_uvd_limit()
856 pi->uvd_dpm.soft_max_clk = clock; in cz_init_uvd_limit()
857 pi->uvd_dpm.hard_max_clk = clock; in cz_init_uvd_limit()
863 struct cz_power_info *pi = cz_get_pi(adev); in cz_init_vce_limit() local
873 pi->vce_dpm.soft_min_clk = table->entries[0].ecclk; in cz_init_vce_limit()
874 pi->vce_dpm.hard_min_clk = table->entries[0].ecclk; in cz_init_vce_limit()
885 pi->vce_dpm.soft_max_clk = clock; in cz_init_vce_limit()
886 pi->vce_dpm.hard_max_clk = clock; in cz_init_vce_limit()
892 struct cz_power_info *pi = cz_get_pi(adev); in cz_init_acp_limit() local
902 pi->acp_dpm.soft_min_clk = 0; in cz_init_acp_limit()
903 pi->acp_dpm.hard_min_clk = 0; in cz_init_acp_limit()
913 pi->acp_dpm.soft_max_clk = clock; in cz_init_acp_limit()
914 pi->acp_dpm.hard_max_clk = clock; in cz_init_acp_limit()
920 struct cz_power_info *pi = cz_get_pi(adev); in cz_init_pg_state() local
922 pi->uvd_power_gated = false; in cz_init_pg_state()
923 pi->vce_power_gated = false; in cz_init_pg_state()
924 pi->acp_power_gated = false; in cz_init_pg_state()
930 struct cz_power_info *pi = cz_get_pi(adev); in cz_init_sclk_threshold() local
932 pi->low_sclk_interrupt_threshold = 0; in cz_init_sclk_threshold()
1083 struct cz_power_info *pi = cz_get_pi(adev); in cz_program_bootup_state() local
1088 pi->sclk_dpm.soft_min_clk = pi->sys_info.bootup_sclk; in cz_program_bootup_state()
1089 pi->sclk_dpm.soft_max_clk = pi->sys_info.bootup_sclk; in cz_program_bootup_state()
1092 pi->sclk_dpm.soft_min_clk, in cz_program_bootup_state()
1095 pi->sclk_dpm.soft_max_clk, in cz_program_bootup_state()
1131 struct cz_power_info *pi = cz_get_pi(adev); in cz_do_enable_didt() local
1134 if (pi->caps_sq_ramping) { in cz_do_enable_didt()
1142 if (pi->caps_db_ramping) { in cz_do_enable_didt()
1150 if (pi->caps_td_ramping) { in cz_do_enable_didt()
1158 if (pi->caps_tcp_ramping) { in cz_do_enable_didt()
1171 struct cz_power_info *pi = cz_get_pi(adev); in cz_enable_didt() local
1174 if (pi->caps_sq_ramping || pi->caps_db_ramping || in cz_enable_didt()
1175 pi->caps_td_ramping || pi->caps_tcp_ramping) { in cz_enable_didt()
1213 struct cz_power_info *pi = cz_get_pi(adev); in cz_update_current_ps() local
1216 pi->current_ps = *ps; in cz_update_current_ps()
1217 pi->current_rps = *rps; in cz_update_current_ps()
1218 pi->current_rps.ps_priv = ps; in cz_update_current_ps()
1225 struct cz_power_info *pi = cz_get_pi(adev); in cz_update_requested_ps() local
1228 pi->requested_ps = *ps; in cz_update_requested_ps()
1229 pi->requested_rps = *rps; in cz_update_requested_ps()
1230 pi->requested_rps.ps_priv = ps; in cz_update_requested_ps()
1240 struct cz_power_info *pi = cz_get_pi(adev); in cz_apply_state_adjust_rules() local
1248 pi->video_start = new_rps->dclk || new_rps->vclk || in cz_apply_state_adjust_rules()
1253 pi->battery_state = true; in cz_apply_state_adjust_rules()
1255 pi->battery_state = false; in cz_apply_state_adjust_rules()
1257 if (pi->caps_stable_power_state) in cz_apply_state_adjust_rules()
1260 if (mclk > pi->sys_info.nbp_memory_clock[CZ_NUM_NBPMEMORY_CLOCK - 1]) in cz_apply_state_adjust_rules()
1497 struct cz_power_info *pi = cz_get_pi(adev); in cz_dpm_pre_set_power_state() local
1502 cz_apply_state_adjust_rules(adev, &pi->requested_rps, in cz_dpm_pre_set_power_state()
1503 &pi->current_rps); in cz_dpm_pre_set_power_state()
1510 struct cz_power_info *pi = cz_get_pi(adev); in cz_dpm_update_sclk_limit() local
1515 clock = pi->sclk_dpm.soft_min_clk; in cz_dpm_update_sclk_limit()
1517 if (pi->caps_stable_power_state) { in cz_dpm_update_sclk_limit()
1523 if (clock != pi->sclk_dpm.soft_min_clk) { in cz_dpm_update_sclk_limit()
1524 pi->sclk_dpm.soft_min_clk = clock; in cz_dpm_update_sclk_limit()
1531 if (pi->caps_stable_power_state && in cz_dpm_update_sclk_limit()
1532 pi->sclk_dpm.soft_max_clk != clock) { in cz_dpm_update_sclk_limit()
1533 pi->sclk_dpm.soft_max_clk = clock; in cz_dpm_update_sclk_limit()
1542 pi->sclk_dpm.soft_max_clk, in cz_dpm_update_sclk_limit()
1552 struct cz_power_info *pi = cz_get_pi(adev); in cz_dpm_set_deep_sleep_sclk_threshold() local
1554 if (pi->caps_sclk_ds) { in cz_dpm_set_deep_sleep_sclk_threshold()
1567 struct cz_power_info *pi = cz_get_pi(adev); in cz_dpm_set_watermark_threshold() local
1571 pi->sclk_dpm.soft_max_clk); in cz_dpm_set_watermark_threshold()
1579 struct cz_power_info *pi = cz_get_pi(adev); in cz_dpm_enable_nbdpm() local
1582 if (pi->nb_dpm_enabled_by_driver && !pi->nb_dpm_enabled) { in cz_dpm_enable_nbdpm()
1590 pi->nb_dpm_enabled = true; in cz_dpm_enable_nbdpm()
1609 struct cz_power_info *pi = cz_get_pi(adev); in cz_dpm_update_low_memory_pstate() local
1610 struct cz_ps *ps = &pi->requested_ps; in cz_dpm_update_low_memory_pstate()
1612 if (pi->sys_info.nb_dpm_enable) { in cz_dpm_update_low_memory_pstate()
1638 struct cz_power_info *pi = cz_get_pi(adev); in cz_dpm_post_set_power_state() local
1639 struct amdgpu_ps *ps = &pi->requested_rps; in cz_dpm_post_set_power_state()
1647 struct cz_power_info *pi = cz_get_pi(adev); in cz_dpm_force_highest() local
1650 if (pi->sclk_dpm.soft_min_clk != pi->sclk_dpm.soft_max_clk) { in cz_dpm_force_highest()
1651 pi->sclk_dpm.soft_min_clk = in cz_dpm_force_highest()
1652 pi->sclk_dpm.soft_max_clk; in cz_dpm_force_highest()
1656 pi->sclk_dpm.soft_min_clk, in cz_dpm_force_highest()
1667 struct cz_power_info *pi = cz_get_pi(adev); in cz_dpm_force_lowest() local
1670 if (pi->sclk_dpm.soft_max_clk != pi->sclk_dpm.soft_min_clk) { in cz_dpm_force_lowest()
1671 pi->sclk_dpm.soft_max_clk = pi->sclk_dpm.soft_min_clk; in cz_dpm_force_lowest()
1675 pi->sclk_dpm.soft_max_clk, in cz_dpm_force_lowest()
1686 struct cz_power_info *pi = cz_get_pi(adev); in cz_dpm_get_max_sclk_level() local
1688 if (!pi->max_sclk_level) { in cz_dpm_get_max_sclk_level()
1690 pi->max_sclk_level = cz_get_argument(adev) + 1; in cz_dpm_get_max_sclk_level()
1693 if (pi->max_sclk_level > CZ_MAX_HARDWARE_POWERLEVELS) { in cz_dpm_get_max_sclk_level()
1698 return pi->max_sclk_level; in cz_dpm_get_max_sclk_level()
1703 struct cz_power_info *pi = cz_get_pi(adev); in cz_dpm_unforce_dpm_levels() local
1709 pi->sclk_dpm.soft_min_clk = dep_table->entries[0].clk; in cz_dpm_unforce_dpm_levels()
1712 pi->sclk_dpm.soft_max_clk = dep_table->entries[level].clk; in cz_dpm_unforce_dpm_levels()
1714 pi->sclk_dpm.soft_max_clk = in cz_dpm_unforce_dpm_levels()
1722 pi->sclk_dpm.soft_min_clk, in cz_dpm_unforce_dpm_levels()
1730 pi->sclk_dpm.soft_max_clk, in cz_dpm_unforce_dpm_levels()
1736 pi->sclk_dpm.soft_min_clk, in cz_dpm_unforce_dpm_levels()
1737 pi->sclk_dpm.soft_max_clk); in cz_dpm_unforce_dpm_levels()
1786 struct cz_power_info *pi = cz_get_pi(adev); in cz_dpm_get_sclk() local
1787 struct cz_ps *requested_state = cz_get_ps(&pi->requested_rps); in cz_dpm_get_sclk()
1798 struct cz_power_info *pi = cz_get_pi(adev); in cz_dpm_get_mclk() local
1800 return pi->sys_info.bootup_uma_clk; in cz_dpm_get_mclk()
1805 struct cz_power_info *pi = cz_get_pi(adev); in cz_enable_uvd_dpm() local
1808 if (enable && pi->caps_uvd_dpm ) { in cz_enable_uvd_dpm()
1809 pi->dpm_flags |= DPMFlags_UVD_Enabled; in cz_enable_uvd_dpm()
1815 pi->dpm_flags &= ~DPMFlags_UVD_Enabled; in cz_enable_uvd_dpm()
1833 struct cz_power_info *pi = cz_get_pi(adev); in cz_dpm_powergate_uvd() local
1836 if (pi->uvd_power_gated == gate) in cz_dpm_powergate_uvd()
1839 pi->uvd_power_gated = gate; in cz_dpm_powergate_uvd()
1842 if (pi->caps_uvd_pg) { in cz_dpm_powergate_uvd()
1852 if (pi->caps_uvd_pg) in cz_dpm_powergate_uvd()
1856 if (pi->caps_uvd_pg) { in cz_dpm_powergate_uvd()
1858 if (pi->uvd_dynamic_pg) in cz_dpm_powergate_uvd()
1876 struct cz_power_info *pi = cz_get_pi(adev); in cz_enable_vce_dpm() local
1879 if (enable && pi->caps_vce_dpm) { in cz_enable_vce_dpm()
1880 pi->dpm_flags |= DPMFlags_VCE_Enabled; in cz_enable_vce_dpm()
1887 pi->dpm_flags &= ~DPMFlags_VCE_Enabled; in cz_enable_vce_dpm()
1899 struct cz_power_info *pi = cz_get_pi(adev); in cz_update_vce_dpm() local
1904 if (pi->caps_stable_power_state) { in cz_update_vce_dpm()
1905 pi->vce_dpm.hard_min_clk = table->entries[table->count-1].ecclk; in cz_update_vce_dpm()
1908 pi->vce_dpm.hard_min_clk = table->entries[0].ecclk; in cz_update_vce_dpm()
1914 pi->vce_dpm.hard_min_clk, in cz_update_vce_dpm()
1921 struct cz_power_info *pi = cz_get_pi(adev); in cz_dpm_powergate_vce() local
1923 if (pi->caps_vce_pg) { in cz_dpm_powergate_vce()
1924 if (pi->vce_power_gated != gate) { in cz_dpm_powergate_vce()
1936 pi->vce_power_gated = true; in cz_dpm_powergate_vce()
1939 pi->vce_power_gated = false; in cz_dpm_powergate_vce()
1952 if (! pi->vce_power_gated) { in cz_dpm_powergate_vce()