Lines Matching refs:afmt
1422 if (!dig || !dig->afmt || !dig->afmt->pin) in dce_v10_0_afmt_audio_select_pin()
1425 tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset); in dce_v10_0_afmt_audio_select_pin()
1426 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id); in dce_v10_0_afmt_audio_select_pin()
1427 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp); in dce_v10_0_afmt_audio_select_pin()
1441 if (!dig || !dig->afmt || !dig->afmt->pin) in dce_v10_0_audio_write_latency_fields()
1469 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, in dce_v10_0_audio_write_latency_fields()
1484 if (!dig || !dig->afmt || !dig->afmt->pin) in dce_v10_0_audio_write_speaker_allocation()
1506 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset, in dce_v10_0_audio_write_speaker_allocation()
1519 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, in dce_v10_0_audio_write_speaker_allocation()
1550 if (!dig || !dig->afmt || !dig->afmt->pin) in dce_v10_0_audio_write_sad_regs()
1601 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp); in dce_v10_0_audio_write_sad_regs()
1682 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset); in dce_v10_0_afmt_update_ACR()
1684 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp); in dce_v10_0_afmt_update_ACR()
1685 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset); in dce_v10_0_afmt_update_ACR()
1687 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp); in dce_v10_0_afmt_update_ACR()
1689 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset); in dce_v10_0_afmt_update_ACR()
1691 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp); in dce_v10_0_afmt_update_ACR()
1692 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset); in dce_v10_0_afmt_update_ACR()
1694 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp); in dce_v10_0_afmt_update_ACR()
1696 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset); in dce_v10_0_afmt_update_ACR()
1698 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp); in dce_v10_0_afmt_update_ACR()
1699 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset); in dce_v10_0_afmt_update_ACR()
1701 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp); in dce_v10_0_afmt_update_ACR()
1718 WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset, in dce_v10_0_afmt_update_avi_infoframe()
1720 WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset, in dce_v10_0_afmt_update_avi_infoframe()
1722 WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset, in dce_v10_0_afmt_update_avi_infoframe()
1724 WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset, in dce_v10_0_afmt_update_avi_infoframe()
1739 if (!dig || !dig->afmt) in dce_v10_0_audio_set_dto()
1772 if (!dig || !dig->afmt) in dce_v10_0_afmt_setmode()
1776 if (!dig->afmt->enabled) in dce_v10_0_afmt_setmode()
1786 dig->afmt->pin = dce_v10_0_audio_get_pin(adev); in dce_v10_0_afmt_setmode()
1787 dce_v10_0_audio_enable(adev, dig->afmt->pin, false); in dce_v10_0_afmt_setmode()
1791 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1793 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */ in dce_v10_0_afmt_setmode()
1795 WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000); in dce_v10_0_afmt_setmode()
1797 tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1822 WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1824 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1828 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1830 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1835 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1837 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1840 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1842 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1845 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1847 WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */ in dce_v10_0_afmt_setmode()
1849 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1854 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1856 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1859 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1861 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1870 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1874 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1876 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1878 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1880 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1882 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1889 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1893 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset, in dce_v10_0_afmt_setmode()
1914 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1919 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1921 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1923 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1925 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1928 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1930 WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF); in dce_v10_0_afmt_setmode()
1931 WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF); in dce_v10_0_afmt_setmode()
1932 WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001); in dce_v10_0_afmt_setmode()
1933 WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001); in dce_v10_0_afmt_setmode()
1936 dce_v10_0_audio_enable(adev, dig->afmt->pin, true); in dce_v10_0_afmt_setmode()
1946 if (!dig || !dig->afmt) in dce_v10_0_afmt_enable()
1950 if (enable && dig->afmt->enabled) in dce_v10_0_afmt_enable()
1952 if (!enable && !dig->afmt->enabled) in dce_v10_0_afmt_enable()
1955 if (!enable && dig->afmt->pin) { in dce_v10_0_afmt_enable()
1956 dce_v10_0_audio_enable(adev, dig->afmt->pin, false); in dce_v10_0_afmt_enable()
1957 dig->afmt->pin = NULL; in dce_v10_0_afmt_enable()
1960 dig->afmt->enabled = enable; in dce_v10_0_afmt_enable()
1963 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id); in dce_v10_0_afmt_enable()
1971 adev->mode_info.afmt[i] = NULL; in dce_v10_0_afmt_init()
1975 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL); in dce_v10_0_afmt_init()
1976 if (adev->mode_info.afmt[i]) { in dce_v10_0_afmt_init()
1977 adev->mode_info.afmt[i]->offset = dig_offsets[i]; in dce_v10_0_afmt_init()
1978 adev->mode_info.afmt[i]->id = i; in dce_v10_0_afmt_init()
1988 kfree(adev->mode_info.afmt[i]); in dce_v10_0_afmt_fini()
1989 adev->mode_info.afmt[i] = NULL; in dce_v10_0_afmt_fini()
3536 dig->afmt = adev->mode_info.afmt[dig->dig_encoder]; in dce_v10_0_encoder_prepare()