Lines Matching refs:afmt
1410 if (!dig || !dig->afmt || !dig->afmt->pin) in dce_v11_0_afmt_audio_select_pin()
1413 tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset); in dce_v11_0_afmt_audio_select_pin()
1414 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id); in dce_v11_0_afmt_audio_select_pin()
1415 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp); in dce_v11_0_afmt_audio_select_pin()
1429 if (!dig || !dig->afmt || !dig->afmt->pin) in dce_v11_0_audio_write_latency_fields()
1457 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, in dce_v11_0_audio_write_latency_fields()
1472 if (!dig || !dig->afmt || !dig->afmt->pin) in dce_v11_0_audio_write_speaker_allocation()
1494 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset, in dce_v11_0_audio_write_speaker_allocation()
1507 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, in dce_v11_0_audio_write_speaker_allocation()
1538 if (!dig || !dig->afmt || !dig->afmt->pin) in dce_v11_0_audio_write_sad_regs()
1589 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp); in dce_v11_0_audio_write_sad_regs()
1670 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset); in dce_v11_0_afmt_update_ACR()
1672 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp); in dce_v11_0_afmt_update_ACR()
1673 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset); in dce_v11_0_afmt_update_ACR()
1675 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp); in dce_v11_0_afmt_update_ACR()
1677 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset); in dce_v11_0_afmt_update_ACR()
1679 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp); in dce_v11_0_afmt_update_ACR()
1680 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset); in dce_v11_0_afmt_update_ACR()
1682 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp); in dce_v11_0_afmt_update_ACR()
1684 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset); in dce_v11_0_afmt_update_ACR()
1686 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp); in dce_v11_0_afmt_update_ACR()
1687 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset); in dce_v11_0_afmt_update_ACR()
1689 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp); in dce_v11_0_afmt_update_ACR()
1706 WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset, in dce_v11_0_afmt_update_avi_infoframe()
1708 WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset, in dce_v11_0_afmt_update_avi_infoframe()
1710 WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset, in dce_v11_0_afmt_update_avi_infoframe()
1712 WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset, in dce_v11_0_afmt_update_avi_infoframe()
1727 if (!dig || !dig->afmt) in dce_v11_0_audio_set_dto()
1760 if (!dig || !dig->afmt) in dce_v11_0_afmt_setmode()
1764 if (!dig->afmt->enabled) in dce_v11_0_afmt_setmode()
1774 dig->afmt->pin = dce_v11_0_audio_get_pin(adev); in dce_v11_0_afmt_setmode()
1775 dce_v11_0_audio_enable(adev, dig->afmt->pin, false); in dce_v11_0_afmt_setmode()
1779 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1781 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */ in dce_v11_0_afmt_setmode()
1783 WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000); in dce_v11_0_afmt_setmode()
1785 tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1810 WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1812 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1816 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1818 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1823 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1825 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1828 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1830 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1833 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1835 WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */ in dce_v11_0_afmt_setmode()
1837 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1842 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1844 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1847 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1849 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1858 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1862 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1864 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1866 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1868 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1870 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1877 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1881 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset, in dce_v11_0_afmt_setmode()
1902 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1907 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1909 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1911 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1913 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1916 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1918 WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF); in dce_v11_0_afmt_setmode()
1919 WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF); in dce_v11_0_afmt_setmode()
1920 WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001); in dce_v11_0_afmt_setmode()
1921 WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001); in dce_v11_0_afmt_setmode()
1924 dce_v11_0_audio_enable(adev, dig->afmt->pin, true); in dce_v11_0_afmt_setmode()
1934 if (!dig || !dig->afmt) in dce_v11_0_afmt_enable()
1938 if (enable && dig->afmt->enabled) in dce_v11_0_afmt_enable()
1940 if (!enable && !dig->afmt->enabled) in dce_v11_0_afmt_enable()
1943 if (!enable && dig->afmt->pin) { in dce_v11_0_afmt_enable()
1944 dce_v11_0_audio_enable(adev, dig->afmt->pin, false); in dce_v11_0_afmt_enable()
1945 dig->afmt->pin = NULL; in dce_v11_0_afmt_enable()
1948 dig->afmt->enabled = enable; in dce_v11_0_afmt_enable()
1951 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id); in dce_v11_0_afmt_enable()
1959 adev->mode_info.afmt[i] = NULL; in dce_v11_0_afmt_init()
1963 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL); in dce_v11_0_afmt_init()
1964 if (adev->mode_info.afmt[i]) { in dce_v11_0_afmt_init()
1965 adev->mode_info.afmt[i]->offset = dig_offsets[i]; in dce_v11_0_afmt_init()
1966 adev->mode_info.afmt[i]->id = i; in dce_v11_0_afmt_init()
1976 kfree(adev->mode_info.afmt[i]); in dce_v11_0_afmt_fini()
1977 adev->mode_info.afmt[i] = NULL; in dce_v11_0_afmt_fini()
3530 dig->afmt = adev->mode_info.afmt[dig->dig_encoder]; in dce_v11_0_encoder_prepare()